JP3217576B2 - Integrated audio decoder device and operation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION This invention relates generally to the field of electronic systems and, more particularly, to an improved integrated audio decoder system and method of operation.

[0002]

[Prior Art] Motion Picture Expert Group (Motion Picture
Experts Group: MPEG) is an ISO-11172 MPEG audio and video standard (hereinafter the "MPEG standard") for compression and decompression algorithms used for digital transmission and reception of audio (or audio) and video (or video) broadcasts. ). The MPEG standard efficiently compresses data according to established psychoacoustic models and enables real-time compression, decompression, and broadcast of CD-quality audio and video images. The MPEG standard offers three possible data transfer modes. First
The modes include audio and visual (or visual) data as well as information used to synchronize the broadcast of the audio and video portions. A second mode of possible data transmission includes audio information and information that can be used to synchronize this audio information with a video system operating in parallel. The third and last mode of possible data transmission consists only of audio data. The MPEG compression / decompression standard uses data streams that must be received and processed at rates up to 15 megabits / second. Previous systems used to implement MPEG decompression operations required expensive digital signal processors and extended support memory. Soon the MPEG audio and video standard will be used in large-scale transmission systems for television and radio broadcasts.

[0003]

SUMMARY OF THE INVENTION Accordingly, there is a need to provide a system capable of performing a defined MPEG audio decompression operation at a lower cost than that associated with a system centralized around a programmable digital signal processor. Exists. In accordance with the teachings of the present invention, an integrated audio decoder system is disclosed that substantially reduces or eliminates the deficiencies associated with conventional systems, and a method for implementing MPEG audio decompression operations. A data processing system according to one embodiment of the present invention includes a microprocessor host system, an audio decoder system, and a digital-to-analog converter. The audio decoder receives the encoded data stream, extracts and decodes the selected encoded audio data,
It is operable to filter the data and provide it as input data to a digital to analog converter. An audio decoder system according to an alternative embodiment of the present invention comprises:
It comprises a system decoder, an audio decoder, and an arithmetic unit implemented on a single semiconductor substrate. The system decoder is operable to receive the encoded compressed bitstream and extract information indicating to the remainder of the system the compression algorithm used to form the bitstream. The audio decoder includes a micro-coding engine operable to convert the bit stream into discrete samples and sub-band filter coefficients. The arithmetic unit is operable to receive the sample and subband filter coefficients, generate PCM data, and provide this data as an output from the system to a digital to analog converter.

[0004] The technical advantages of the present invention will be more fully understood from the following description with reference to the accompanying drawings. In the accompanying drawings, the same elements are denoted by the same reference numerals.

[0005]

EXAMPLES Introduction The present invention is encoded by using the MPEG syntax, comprising a stream of compressed data from system operable to efficiently decoded. To achieve real-time processing of a data stream, the system of the present invention can receive a bit stream that can be transmitted at a variable bit rate up to 15 Mbit / s, and is time-shared with other data in the bit stream. It must be able to identify and retrieve the particular audio data set that is present.
The system must then decode the retrieved data and provide ordinary pulse code modulated (PCM) data to the digital-to-analog converter. This digital-to-analog converter produces a normal analog audio signal that is comparable to other digital audio technologies. The system of the present invention must present the synchronized and decoded audio data in the bitstream and the decoded audio data simultaneously (eg, of the digitally encoded video image associated with the audio). The synchronization with other data streams must also be monitored. Furthermore, MPEG
The data stream may also include auxiliary data that can be used as system control information or to transmit related data such as song titles and the like. The system of the present invention must recognize this auxiliary data and alert other systems of its existence. General Architecture The audio decoding system 10 shown in FIG. 1 includes a microprocessor host 12 coupled to an integrated audio decoder system 14. Audio decoder system 14 receives either a serial bit stream from microprocessor host 12 or parallel data after host 12 converts the serial data to a parallel format. In each case, the data received by audio decoder system 14 comprises audio and visual data that has been encoded using an MPEG audio-visual compression algorithm. The audio decoder system 14 retrieves the appropriate information indicating the format of the audio portion of the bitstream and uses this information to decode the audio data to produce pulse code modulated (PCM) data. 1 to the digital / analog converter 16 shown in FIG.

In accordance with one embodiment of the present invention, audio decoder system 14 is formed as a monolithic structure on a single semiconductor substrate. The audio decoder system 14 includes a microprocessor host 12
And a host interface block 18 for receiving a control signal from the controller and an encoded bit stream. The host interface block 18 passes the encoded bit stream to the system decoder block 20. The host interface block 18 routes all communications to and from the microprocessor host 12 for both compressed audio data and control information. Host interface block 18 may comprise, for example, a conventional 8-bit microprocessor interface, a direct memory access (DMA) interface, a serial data input interface, and a plurality of control lines. The host interface block 18 communicates the interrupt signal to the microprocessor host 12, which will be described later in detail. A compressed audio stream can be input using one of three modes. This input can be a serial bit stream through the serial data input of host interface block 18. Further, data may be input in a byte-parallel format on eight data pins coupled to host interface block 18. Parallel data

[0007]

[Outside 1] It is similar to ordinary DMA by the microprocessor host 12. If parallel data is DATA If writing into the IN register, the data must be addressed before each byte can be accessed using normal register addressing. The compressed data received by host interface block 18 can be in one of three formats. This format corresponds to two bits in the control status register block 22.
STR It is controlled by the host 12 by changing the contents of the SEL register. The compressed data stream can be MPEG audio information alone, MPEG audio packets, or a fully multiplexed MPE that can contain one or more audio and video streams.
G Can consist of system streams. In the case of a fully multiplexed MPEG system stream, an additional control register enables or disables decoding of the audio identification field. If this feature is enabled, the identification field in the MPEG system stream will be AUD It is compared with the contents of the ID register, and if the identification field matches, only the audio is decoded. Generally speaking, the control status register block 2
The registers in 2 are written by the microprocessor host 12 to control the operation of the audio decoder system 14. Enable the audio identification function,
Disabling operation is an example of this control.

[0008]

[Outside 2] Access registers in control status register block 22 using SADDR

[0009]

[Outside 3] There is no default setting of the control status register in lock 22. Accumulation

[0010]

[Outside 4] It can be reset by host writing to the RESET register in the register block 22. In either case, the interrupt buffer and all data buffers in integrated audio decoder system 14 are cleared.
The system decoder block 20 identifies and retrieves the appropriate encoded data from the bitstream and loads this information into the input buffer 24 shown in FIG. The input buffer 24 is located on the same semiconductor substrate as the rest of the structure in the audio decoder system 14, and is therefore relatively small. An important advantage of the present invention is that the external buffer 2 can be comprised, for example, of dynamic random access memory (DRAM).
6 is obtained by the fact that the storage capacity of the system can be increased. External buffer 26
The integrated audio decoder system 14 is operable with a video decoding system.
Since decoding video information requires much longer time than decoding audio information, when operating the audio decoding system 10 and the video decoding system together, the audio decoding system 10 adds a delay to the decoding process. Must be able to insert. The external buffer 26 allows the audio decoder system 14 to stay,
This allows video decoding to proceed. In addition, the external buffer 26 also allows the audio decoder system 14 to perform a very sophisticated error concealment strategy if it has the ability to store the last audio information frame that contains no errors. . If the external buffer 26 is available, the audio decoder system 14 will output the last good frame of audio information.
(last good frame: LGF) to hide intermediate frames that have deteriorated during the transmission process. Integrated audio decoder system 14 automatically detects whether external buffer 26 is present and adjusts the error concealment strategy accordingly. In other words, if there is storage capacity to store the last undegraded frame,
Integrated audio decoder system 14 takes advantage of its capacity to implement a more sophisticated error concealment strategy.

The encoded audio data is retrieved from an input buffer 24 and an external buffer 26 by an audio decoder block 28. The audio decoder block 28 includes a programmable arithmetic logic unit (
ALU). This unit retrieves the bitstream from buffers 24 and 26 and truncates the bitstream into coded samples associated with the subband used in the encoding and compression process. The audio decoder block 28 has the final PCM
It also retrieves the subband filter coefficients used to generate the output data. During encoding and compression formats, audio information is converted from PCM audio into subband data in units called frames. A frame consists of real-time audio information at set intervals (e.g., corresponding to an audio playback time on the order of 24 milliseconds). The frame is subdivided into 12 blocks.
According to one form of data transmission, a single block is subdivided into three sets. Each set consists of 32 stereo samples. Each sample is either 16 or 18 information bits and is a sub-band fragment (or slice) of approximately 750 Hz in the frequency range from 0 kHz to 20 kHz.
Corresponding to This roughly corresponds to the audible frequency range. The MPEG compression algorithm first converts the samples into subband samples, and then normalizes or "scales" the scaled samples so that they fall in the range of +1 to -1. Further, each sample may encode a particular sample using a variable number of bits. For example, in some frequency bands, the quantization noise in that frequency band is inaudible to the human ear, so there is no need to use all 16 precise bits. In these cases, the samples can be encoded using fewer bits. Audio decoder block 2
8 extends these samples to 16-bit values and stores these samples and the scale factor index values associated with these samples in an arithmetic unit (AU) buffer 30 shown in FIG. The scale factor index value can be used to search for a scale factor to "denormalize" or dequantize the subband data. The arithmetic unit buffer 30 outputs the sample and the scale coefficient index to the hardware filter arithmetic unit block 32 shown in FIG. The hardware filter operation unit block 32 functions to complete the decoding of the audio information from 16 bits by dequantizing, transforming and filtering the subband samples to form ordinary PCM audio information. I do. This PCM audio information is output to the PCM buffer 34 shown in FIG. PC
The M buffer 34 retrieves data from the PCM buffer 34 and converts the data to an ordinary digital-to-analog converter 1.
6 is accessed by a PCM output block 36 which outputs to

The components of the audio decoder system 14 at the subsequent stage from the arithmetic unit buffer 30 comprise a hard wired system. Due to the time division of the MPEG data stream, all the preceding components from the arithmetic unit buffer 30 must be able to handle the unknown instantaneous bit rate received by the host interface block 18. The arithmetic unit buffer 30 buffers the data stream so that the PCM audio information can be continuously supplied to the digital-to-analog converter 16. Digital-to-analog converter 16 requires PCM audio data at around 1.5 Mbit / s. On the other hand, the instantaneous bit rate of the bit stream received by the host interface block 18 can be as high as 15 Mbit / sec in the MPEG standard.
PCM audio information to digital / analog converter 16
In order to keep supplying the PCM data to the digital / analog converter 16, the audio decoder system 14 controls the PCM buffer 3 until some PCM data is output to the digital / analog converter 16.
4. Decode enough data to insert 4 blocks of data into 4. Due to the provision of these four blocks of cushions, the PCM buffer 34 never emptied,
Audio data is always digital-to-analog converter 1
6 is output. Control and status register The control status register block 22 is a control IN
Contains registers. Microprocessor host 1
2 is DATA during memory mapping mode Data can be input to audio decoder system 14 using the IN register. The control status register block 22 includes:
"CRC error concealment mode" or CRC to specify "error concealment mode" used by audio decoder system 14 to process CRC errors Also includes ECM registers. The microprocessor host 12 may disable CRC detection, mute the output if a CRC error is detected, or repeat the last valid frame of audio data if a CRC error is detected. The audio decoder system 14 can be programmed to skip any frame if a CRC error is detected.

Similarly, the microprocessor host 12
Is used to specify the "error concealment mode" used by the audio decoder system 14 to handle synchronization errors. Use the ECM register. If a synchronization error is detected, the synchronization error is ignored, or the main error is silenced; if a synchronization error is detected, the last valid frame of the audio data is repeated, or a synchronization error is detected. The audio decoder system 14 may be instructed to skip any frame. The PLAY register in the control status register block 22 is decrypted.

[0014]

[Outside 5] Audio data can be output from the audio decoder system 14 only if both of the power lines are asserted by the microprocessor host 12. The value of the PLAY register does not affect the silenced audio data output. On the other hand, the MUTE register in the control status register block 22 is PCM
Force silence of data output. MUTE register or
Or audio decoder

[0015]

[Outside 6] If asserted, the output from audio decoder system 14 is silenced. The silence of the output data does not affect the decoding process taking place within the audio decoder system 14. The microprocessor host 12 can instruct the audio decoder system 14 to skip the next audio frame using the SKIP register. After skipping the next audio frame, the audio decoder system 1
4 resets the REPEAT register. The REPEAT register stores the input buffer 24 or the external buffer memory 2
Only if the capacity of 6 is enough, it becomes active. As described above, RESET in the control status register block 22
Register resets audio decoder system 14

[0016]

[Outside 7] Reset when any of the input lines are asserted. This reset resets the interrupt (INTR) register and flushes all data buffers. Further, at the time of reset, the audio decoder system 1
4 detects the external buffer 26 (if present) and checks its size. Control status register block 2
The RESTART register in 2 causes the audio decoder system 14 to flush all data buffers without affecting the control registers. The microprocessor host 12 selects the string selection or STR in the control status register block 22. Use the SEL register to identify the MPEG format of the bit stream at any one time. An important technical advantage of the integrated system of the present invention is its ability to switch between different bitstream formats without requiring a reset. MPEG
The audio compression / decompression standard allows the system to be reset if the format of the bitstream changes. Even if the format allows such a reset, the system of the present invention has the unique ability to change the decoding process in real time on a frame-by-frame basis. Control status register block 22
"Audio identification enabled" or AUD ID EN
The register enables or disables the audio stream identification function described above.
"Audio identification" or AUD The ID register is a 5-bit register that specifies one to 32 possible audio streams to be decoded in the MPEG system layer. This register is ignored if the audio stream identification function has not been enabled.

The microprocessor host 12 has a "PCM order" or PCM order. Use the ORD register to specify the order of the PCM output data. This register specifies whether the first output is the most or least significant bit of each PCM sample. "Synchronous state" or SYNC
The ST register is a constantly updated register that communicates the synchronization state of the audio decoder system 14.
The system may be either locked to synchronization, unlocked, or attempting to recover synchronization without locking. “Synchronous lock” or SYNC in the control status register block 22 The LCK register specifies the number of sufficient sync words that must be found before system 14 itself can be considered locked. The compressed input bitstream must be synchronized before the decoding process can occur correctly. Synchronization is achieved by looking for a synchronization word that is inserted into the data stream during encoding. Synchronization must be performed at the audio frame and at the system layer level (if this layer is present). Audio decoder system 14 performs synchronization acquisition at initial start-up and whenever synchronization is lost due to errors in the data stream. For the process used to locate the data used for synchronous acquisition, see FIG.
This will be described in detail when describing the system decoder block 20 based on.

HEADE in the control status register block 22
The R register is a 20-bit register, currently being decoded
Used to store the header of the frame. 33
Bit PTS register is also in control status register block 2.
2 and related to the frame currently being decoded
Presentation (or presentation) time stamp
Includes a time stamp. Control status register block
"Buffer", which is a 15-bit register in
Or BUFF register is a 32-bit word increment
Contains the amount of data held in the input buffer. This cash register
The value in the star is a 32-bit data
Updated each time it is written to Control status register block
BALE in ku 22 The LIM register is a 15-bit register
The microprocessor host 12
The “almost full” limit of the input buffer 24 using the
Set. Similarly, the microprocessor host 12
E Using the LIM register, the input buffer 24
Set the "empty" limit. In the control status register block 22
The “auxiliary data” register or ANC register
The last 32 bits of ancillary data in the data stream.
32-bit FIFO (or first-in first-out)
It is a register. In the MPEG standard, the same data stream
Auxiliary data as audio and video data in the system
Allows transmission. The auxiliary data register is
Can be used to monitor and control system activity
Audio decoder system 14
I have to. Auxiliary data buffer is full
Sometimes it can be replaced with new data bit by bit,
Or if auxiliary data is read from the ANC register,
Or the microprocessor until the interrupt is masked.
A full interrupt to the host 12 is generated and audio data is generated.
The further processing of the data can also be stopped. ANC AV
 Registers are the available auxiliary data in the ANC registers
Holds the number of bits. ANC AV register is ANC register.
Before the register is read, the microprocessor host 12
Must be read by

The audio decoder system 14 uses a compression
Externally synchronized to the audio bitstream
Clock input (PCM CLK). This
The lock signal is the actual PCM output bit rate and
Or an integer multiple of that bit rate,
Is also good. The audio decoder system 14 uses PCM CLK
The input is stored in the control status register block 22.
PCM By dividing by the value of the DIV register (PCM
Derived from CLK input). PCM DIV register is 11
Register of bits, integer value from 1 to 1,024
I remember. PCM PCM bit clock from CLK input
The oversampling di
A digital-to-analog converter can be used. LATE
The NCY register enables the synchronous prefetch function of the present invention
Used to select the decoder latency that has the effect of
Used. Once the sync prefetch feature is operational, the audio
The audio decoder system 14 decodes a frame of data.
Before detecting multiple synchronization words. Control status register block
FREE in the lock 22 The FORM register is an 11-bit register.
If it is a register and free format decoding is in progress
In this case, the microprocessor host 12 uses this register.
To specify the frame length (if known). Ma
Microprocessor host 12 is SIN Use EN register
The parallel data into the audio decoder system 14
Data or input serial data
Is specified.

ATTEN in control status register block 22
L register and ATTEN The R registers are 6-bit registers each and function to hold an integer value between 0 and 63 for the left or right channel attenuation, respectively. These registers are used during the decoding and decompression processes to allow the balance between left and right channels of stereo audio data to be programmed. PCM in control status register block 22 The 18 register is used to specify the definition of the output of the PCM output block 36. The output definition can be either 16-bit PCM output or 18-bit PCM output. PCM The FS register is a 2-bit register that sets the sampling rate to 32 kHz, 44.1 kHz, or 48 kHz.
Specify one of kHz. The DMPH register is a two-bit register that specifies the mode of de-emphasis used during encoding of the audio stream. SRC and
The IRC registers are both 33-bit registers that are used to store the system reference clock value and the internal reference clock value, respectively. IRC The LOAD register loads the decoded system reference clock value into the IRC register.

DRAM The EXT register is stored in the external buffer 26
Used to specify if is present. If outside
If the internal buffer 26 does not exist, a 256-byte internal input
Only the force buffer 24 is used. As mentioned earlier,
The value in the register of
Used (especially when the audio decoder block 28
Has the ability to play the last frame decoded without
Change the error concealment strategy (used depending on whether or not
Let it. The EOS register marks the end of the stream code.
Indicate whether it has been detected. "Interrupt" or INTR
The register is a 16-bit register, and various interrupts
To the microprocessor host 12. INTR レ
Bit 0 of the register is
Is set when a change occurs in the synchronization state of. INTR レ
Bit 1 of the register indicates that the effective header is audio.
Set when registered by the decoder system 14
It is. Bit 2 of the INTR register is the valid presentation time
Tamp registered by audio decoder system 14
Set when done. Bit 3 of the INTR register is
The input buffer is BALE as described above Stored in LIM register
It is set when it is almost below the sky limit. INTR
 Bit 4 of the register is the BAL
E Almost full limit stored in LIM register
It is set when you get it. Bit 5 of the INTR register is set to CR
C Set when an error is detected. INTR register
Bit 6 indicates that the auxiliary data is an audio decoder system
Set when registered by 14. INTR register
Bit 7 is set when the auxiliary register is full
You. When bit 7 of the INTR register is set,
Ancillary data is read by the microprocessor host 12.
Issued or interrupt bit 7 is masked
Until the additional auxiliary data is placed in the auxiliary data FIFO
Is prohibited. Bit 8 of the INTR register is set to PC
Set when the M-buffer 34 enters the lower-order overflow state.
It is. Bit 9 of the INTR register is the bit stream
Is set when the sampling frequency changes. As well
Bit 10 of the INTR register is the bit stream
Is set when the de-emphasis mode changes. IN
Bit 11 of the TR register indicates the end of the stream character.
Is set when is detected. INTR The EN register is
This is a 16-bit register corresponding to the TR register.
INTR When any position of the EN register becomes 1, INTR
The corresponding bit in the register is enabled.System decoder block FIG. 2 shows a more detailed circuit of the system decoder block 20.
It is a road map. As shown in FIG.
The block 20 receives data from the host interface block 18.
Data into the FIFO 38. FIFO 38 has five 8
Bit words can be stored. The bottom word of FIFO 38
Are loaded into the shift register 40. Then this
Data from shift register 40 one bit at a time.
It is fed (or shifted) into the lid detector 42
You. Data received by the system decoder block 20
Will identify the various data sequences that must be detected
Contains. These data sequences are of variable length
Therefore, the data is shifted by the shifter detector 42 at one time.
You have to look it up bit by bit. Shift register 40
Is controlled by the control counter 50 through the control logic block 46.
Is controlled. How many in the shift register 40
Shifter counter to track if bits are left
Data 44 is used. As shown in FIG.
Counter 44, shift register 40, and shifter detector 4
2 are all controlled by the control logic block 46.

The operation will be described. The bit length of the next expected data field is loaded into the control counter 50 and the shift register 40 shifts one bit at a time to the shifter detector 42 until the control counter 50 decrements to zero. Shifter detector 42 is 33 bits wide. A shifter copy register 48 is used to hold a copy of the number of bits sent to the shifter detector 42. The shifter copy register 48 is used at the end of the bit stream to temporarily store the incomplete data sequence until further data is received and the shifter detector 42 is fully loaded. For example, 32
The data stream may end when only 16 bits of the bit data structure are shifted into the shifter detector 42. These 16 bits are loaded into shifter copy register 48 until the remaining bits of the 32-bit data structure are found. When the remaining bits are found, the contents of shifter copy register 48 are reloaded into shifter detector 42, and the remaining bits of the data structure are shifted out of shift register 40. The shifter copy register 48 is controlled using a control counter 50 and a control counter copy register 52.

When shifter detector 42 receives 32 bits of information, the data is loaded in parallel to buffer interface block 54, which can be loaded into input buffer 24 or external buffer 26. An address indicating where data is to be written in the input buffer 24 is retrieved from the data address counter 56 or the PTS address counter 58. Normal audio data is loaded using the data address counter 56. The data address counter 56 is incremented as each 32-bit portion of data is written into the input buffer 24.
The "presentation timestamp" is stored in a different part of the input buffer 24, which is stored in the PTS address counter 58.
Indicated by the value in The control logic block 46
It has a state machine controller that controls the overall execution of the system decoder block 20. Control logic block 4
The first function of 6 is to perform start code detection as indicated by block 60 in FIG. The shifter detector 42 outputs, for example, 23 0s as the syntax of the start code,
Detect the specific code that follows. Upon detecting the start code, shifter detector 42 communicates this fact to control logic block 46.

The system decoder block 20 can decode data in three different modes. The data stream may be an audio stream, a packet stream, or a complete system stream. System decoder block 20
Is the STR set by the microprocessor host 12. Reading the SEL register configures for the appropriate mode. For an audio-only stream, the system decoder block 20 simply receives the data into the FIFO 38 and places it in the shift register 40.
And directly to the input buffer 24 through the shifter detector 42. For audio-only streams, system decoder block 20 does not perform detection. The flow diagram in the control logic block 46 of FIG.
The operation of the system decoder block 20 in the remaining two modes, either the MPEG packet stream or the MPEG complete system stream, is shown. MP
For an EG complete system stream, control logic block 46 looks for the pack header and system reference clock in block 62 of FIG. According to the MPEG standard,
The pack includes a plurality of audio and video packets and synchronization information including a presentation time stamp and a system reference clock. Each packet in the pack contains only audio data or only video data with a presentation timestamp. In the full system mode, the system decoder block 20 of the present invention proceeds to step 64 after decoding the pack and SRC to decode the system header information. The system decoder block 20 of the present invention then begins to look for a packet start code at step 66.

In the case of an MPEG packet stream, ie, the second mode of operation, control logic block 46 proceeds directly to step 66 to begin searching for a packet start code. The system of the present invention, no matter what the user wants,
It is flexible enough to work with the microprocessor host 12 to split the decoding task. If the microprocessor host 12 performs all decoding tasks and sends only the desired audio stream to the system decoder block 20, the microprocessor host 1
2 is STR The system decoder block 20 can be instructed to simply pass data using the SEL register. In contrast, the microprocessor host 12 can pass the entire MPEG system stream to the system decoder block 20 without performing any system decoding function. In this case, the control logic block 46
Detects the beginning of a pack of data, and upon detecting the beginning of a pack, begins searching for a packet header in the desired audio stream that has been instructed by the microprocessor host 12 to decode. The packet header is decoded in step 68 of FIG. Step 68 is
It also decodes the presentation timestamp and decodes the timestamp in the packet header. In the MPEG standard, packet headers are used to identify a set of audio data that can be multiplexed between auxiliary data, video data, and other audio data. In step 68, the control logic block 46 determines the audio identification, AUD
A comparison is made with the value stored in the ID register to determine whether the detected packet is part of an audio stream to be decoded. If the packet is to be decoded, control logic block 46 proceeds to step 7 of FIG.
0 and the data in the packet is input to buffer 2
4, or external buffer 26 (if present)
Write in. In step 70, the packet data byte count is extracted from the packet header and loaded into the packet byte counter 72 of FIG.

The system reference clock is retrieved from the header at step 62 and loaded into the CRC register and incremented at a rate of 90 kHz. This allows the audio decoder system 14 to:
Maintain a copy of the external system reference clock that is updated with each new pack that is decoded. Similarly, at step 68, the PTS is extracted from the packet header and loaded into the input buffer 24 at the address indicated by the PTS address counter 58. The presentation timestamp indicates when to play a particular frame of audio information relative to the system reference clock. The system decoder block 20 receives the pack header with the system reference clock at least every 0.07 seconds and maintains accurate synchronization with the rest of the system. The system of the present invention determines that every packet sent to the system decoder block 20 is the correct audio stream to decode. It also has an optional mode of operation, as indicated by the value in the SEL register. In this case, the packet header is identified in step 68, but the audio stream identification in the packet header and the AUD There is no need to compare with the value stored in the ID register. Under these circumstances, the microprocessor host 12 or other external system already decodes the bitstream, extracts packets for a particular audio stream, and combines these packets with their packet headers into the audio decoder system 14. Has been sent to

In step 70, the number of bytes in the packet is determined by the shifter detector 42 from the packet byte counter 7.
2 is loaded. The packet byte counter 72 includes a three-bit extension at the least significant end of the counter so that each bit can be decremented as shifted by the shift register 40. The extension of 3 bits has the effect of changing the packet byte count to a packet bit count. The packet byte counter 72 includes the ability to detect that the bit count is all zeros. All contents of the packet byte counter 72 are 0
If so, control logic block 46 returns to step 60 to search for a start code. Control logic block 46 also includes an end of stream handler 74. At the end of the packet, control logic block 46 looks for the end-of-stream code in the data stream. If this code is found, control logic block 46 returns to step 60 to begin detecting the start code for the new pack. If the end of the packet is reached but the end of stream code does not exist, control logic block 4
6 returns to step 66 to search for the next suitable start code for the next packet to be decoded. Block 74 is shown in parallel with steps 60-70 because the end of the stream may be presented asynchronously in the middle of the audio stream. For example, microprocessor host 12 may send an end-of-stream status to indicate to audio decoder system 14 that the data that follows is irrelevant to the data that precedes the end of the stream. In this case, control logic block 46 loads the data in shifter detector 42 into input buffer 24 and then stores the value of the data address in data address counter 56.

The audio decoder block 28
Data located at the end of the ream code
If you try to address
The coder block 28 performs a restart and sends a hardware file.
The filter operation unit block 32 is set to zero. to this
Data before the end of the stream
Data will not be affected since the end of the
You. If end of stream character is microprocessor
If received from host 12, system decoder block
20 is FIFO 3 before performing end-of-stream processing.
Clear 8 The shifter A copy register 48 receives
Data stream less than 32 bits, intermediate control
When information is in the bitstream,
To store the tabit in shifter A copy register 48
Used for For example, the end of the frame is
Of the 32-bit group preceding the
It can contain only the middle 16 bits. this
These 16 bits are stored in shifter A copy register 48.
It is done. The control logic block 46 includes the control counter 5
The information in the shifter detector 42 is
Determine whether the value is a cut value. This controls the number 32
Load into counter 50, then one bit is shifted
Each time the signal is fed into the detector 42, the control counter 50
Is achieved by decrementing Control cow
When the counter 50 reaches 0, the contents of the shifter detector 42
To the buffer interface block 54 in parallel
I do. Less than 32 bits incomplete in shifter detector 42
If all values exist, the contents of the control counter 50 are
Copied into control counter copy register 52. Control power
Counter 50 is the bit length field specified from the heading.
Also used to search for code. For example, if the system
6 packets from a packet, pack, or frame header
If a request field is required, the value 6 is added to the control counter 5
Load into 0 and shift register 40
Decremented every time it is fed into shifter detector 42
Let it. The control counter 50 counts from 6 to 0
The content of the shifter detector 42 is
Of the desired 6 bits. Audio decoder block FIG. 3 shows a possible implementation of the audio decoder block 28.
It is a circuit diagram of an example. Audio decoder block 28
Is the microprogram read-only memory (or R
OM) 80, and the ROM 80 is an instruction multiplex.
To the instruction pipe register 82 through the
Supply instructions. The instruction multiplexer 84 stores a constant.
From the device 86, data bus 88, and accumulator bus 90.
Input is also being received. Micro program read only
The memory 80 is stored in a program counter 92
Is accessed using the current value. Program counter
92 reads the 11-bit pointer by microprogram.
It is stored in the delivery-only memory 80. Program counsel
The counter 92 includes an incrementer 96, a constant storage device 98,
From the routine stack 100 and the branch bus 102
A program counter multiplexer 94 for receiving the
Loaded through. Output of program counter 92
Is the incrementer 96 and the subroutine stack 10
0 can optionally be loaded. Constant memory
Device 98 has addresses for reset and restart operations.
And the operation of the audio decoder block 28.
Multiple programs that can be used to set a fork in
Remember break points that can be rammed. Instruction multiplexer 8
4 and the program counter multiplexer 94
Controlled by control state machine 104.

The 18-bit instruction format used by audio decoder block 28 includes a 5-bit instruction sent through control multiplexer 108 to control arithmetic logic unit 106. Control multiplexer 108 receives a 5-bit instruction from either instruction pipe register 82 or execution control state machine 104. Arithmetic logic unit 106 is a 16-bit full-function arithmetic logic unit that receives one operand (or operand) from accumulator bus 90 coupled to accumulator 110. The other input of arithmetic logic unit 106 is connected to data register 1 coupled to data bus 88.
Multiplexer 11 receiving one input from 14
Receive from 2. The remaining inputs of multiplexer 112 are
It is received from the constant register 118 and the address bus 120. Multiplexer 112 may also concatenate values received from constant register 118 and address bus 120. Multiplexer 112 is used to control execution control state machine 10.
4. The output of multiplexer 112 is coupled to the input of program counter multiplexer 94 via branch bus 102. Further, the output of multiplexer 112 is a bypass multiplexer 122
Is passed to the accumulator 110 through the
6 is provided. The contents of accumulator 110 can be transferred to data bus 88 through multiplexer 124. Accumulator 110 may also operate to receive bits from data shifter 126 that are 32 bits long. The data shifter 126 receives the data from the data register 114 through the multiplexer 112.
It can be loaded in bit increments. The data shifter 126 is controlled by a shift counter 128, which shift control state machine 10
4. To keep track of how many bits are shifted out of data shifter 126,
A bit load counter 130 is used. The load counter 130 is controlled by the execution control state machine 104. The value in load counter 130 can be transferred to data bus 88 through multiplexer 124.

The operation will be described. Audio decoder block 28 receives a 32-bit data field from input buffer 24 through DRAM / SRAM controller 132 and DRAM interface 134. The 32-bit data field is accessed by a 16-bit sequential read operation. The processing data is loaded into the arithmetic unit buffer 30. Further, the arithmetic unit buffer 30 can be used as a scratch pad memory (or a working storage device) to retrieve a value through the data bus 88. The arithmetic unit buffer 30 is addressed from the address bus 120 through the address multiplexer 136. The address multiplexer 136 determines whether the arithmetic unit buffer 30 is accessed by the audio decoder block 28 or the hardware filter arithmetic unit block 32. Data bus 88 and address bus 120 are each coupled to control status register block 22. Further, the data bus 88 and the address bus 120
Is a special register block 138 consisting of CRC register, subband counter, end of stream register, etc.
Is joined to. In short, special register block 1
38 includes registers used internally by the audio decoder system 14, and the control status register block 22 includes registers accessed by both the audio decoder system 14 and the microprocessor host 12. For example, special register block 138 includes a register that stores the current header of the frame being decoded.
Information from this heading can be found in the nBAL and BPCW read-only memory tables 140 and 1
Used to access 44. Further, special register block 138 includes a register for storing the subband count. This counter is incremented as each subband is activated. The number of subbands is also used to access memories 140 and 144.
Further, the data register 88 and the address register 12
0, and the accumulator bus 90 provides the number of bits allocated per sample used during decoding of the audio bitstream and the number of bits per codeword (bits / bit).
Used to store values for codewords)
nBAL and BPCW are coupled to read only memory table 140.

Data bus 88 and address bus 120
Are also coupled to a random access memory scratchpad 142 comprising memory for storing 256 16-bit words. The data bus 88 and the address bus 120
Is also coupled to a read-only memory table 144 that stores values used to calculate frame lengths and other constants used during decoding of the audio bitstream. The operation will be described. Audio decoder block 28 may include a 5-bit instruction field, a 2-bit field that specifies the operand type, and immediate operands or regular or indirect address references.
Execute 18-bit microcode instructions with 11-bit fields. Audio decoder block 28
Performs the following set of instructions to perform the necessary routines to decode the bit stream received from input buffer 24. Instruction Op. Type (10) Description of operation Abbreviation Bit (00) (01) Indir. Reg. Imm. ADD 00000 yyy Acc + Op-> Acc SUB 00001 yyy Acc-Op-> Acc AND 00010 yyy Acc AND Op-> Acc OR 00011 yyy Acc OR Op-> Acc XOR 00100 yyy Acc XOR Op-> Acc GSYN 00101 yyy Synchronized word search SRL 01000 yyy Logical right shift Acc SLL 01001 yyy Logical left shift Acc SRC 01010 yyy Cyclic right shift Feed Acc SRA 01011 yyy Arithmetic right shift Acc GBT 01100 yyy Obtain bits from input buffer or external buffer GBTC 01101 yyy Obtain bits from input buffer or external buffer and CRC check GBTF 01110 yyy Flush / input shifter Get bits from buffer or external buffer GANC 01111 yyy Get bits and write to ANC buffer Instruction Op. Type (10) Description of operation Abbreviation Symbol Bit (00) (01) Indir. Reg. Imm. ADD 00000 yyy Acc + Op-> Acc SUB 00001 yyy Acc-Op-> Acc BZ 10000 yyy Branch BNZ 10001 yyy Branch at non-zero BO 10010 yyy Branch at overflow BNEG 10011 yyy Branch at negative BC 10100 yyy Branch at carry-out BPOS 10101 yyy Branch at greater than 0 B 10110 yyy Unconditional branch CALL 10111 yyy Branch and change PC Push to stack READ 11000 yny Read buffer WRT 11001 yny Write buffer RET 11010 nnn Remove PC from stack GTBL 11101 nnn ROM table-> Acc (obtain table) LDA 11110 yyy Op- > Acc STA 11111 yny Acc-Memory input buffer 24 Each time is accessed, the DRAM / SRAM
The controller 132 and the DRAM interface 134 are 32
Return bits, these bits are loaded into data register 114 and multiplexer 1 by a continuous 16-bit load operation.
12 to the data shifter 126. For example, in a "get bit" or GBT instruction, the number of bits to retrieve is loaded into the load counter 130 by the execution control state machine 104. The data shifter 126 is then filled with the next 32 bits from the input buffer 24. When the load counter 130 is decremented to 0, the specified number of bits has been transmitted from the data shifter 126 into the accumulator 110. Once the requested number of bits has entered accumulator 110, these bits are manipulated by an arithmetic logic unit (or ALU) or routed as desired. In this manner, any specified number of bits can be retrieved from input buffer 24 with a single instruction. The audio decoder block 28 receives signals from the input buffer 24
Two bits are always read to reduce system traffic. This is due to the fact that the system decoder block 20 must also access the input buffer 24. Indeed, in order to allow the system decoder block 20 to handle bursts of input data up to 15 Mbit / s, the system decoder block 20 prioritizes access to the input buffer 24 over the audio decoder block 28. Must have. Since the data shifter 126 operates as a 32-bit buffer, the audio decoder block 2
8 can continue the operation therein without requiring access to the input buffer 24 many times.

The GBT instruction extracts the next N bits from the incoming bit stream stored in the input buffer 24. This instruction first returns a 16-bit word, which is stored in accumulator 110. This instruction is first executed by the accumulator 11
Clear a zero and then shift the required number of data bits from the accumulator into the data shifter 126. If there are not enough bits in the data shifter 126, reading of the input buffer 24 is automatically started. When the instruction is executed, the value in the load counter 130 is stored. This value is stored in the RAM scratchpad 142 and is used to calculate the bit offset of the data stream. When a new 32 bits are read from input buffer 24, number 32 is loaded into load counter 13
Loaded into 0. The GBTC instruction uses the input buffer 24
Identical to the GBT instruction, except that the CRC error of the bits retrieved from is automatically checked. The GBTF instruction also
The data bits present in the data shifter 126 are identical to the GBT instruction, except that the instruction is first flushed and the instruction begins reading a new 32 bits of the input buffer 24. The GSYN instruction is used to find a synchronization word in the input bitstream. This instruction operates similarly to the GBT instruction except that it stops when a sync word is detected or the value in the digit counter 128 reaches zero. The detection of the synchronization word is performed by the accumulator 110. The GANC command is used to retrieve auxiliary data. This instruction operates similarly to the GBT instruction, except that the bits are also stored in an auxiliary buffer register in the control status register block 22. This instruction can be halted during execution if the auxiliary buffer overflows. As described below, the GANC instruction sets the appropriate interrupt whenever the auxiliary buffer overflows or 16 bits of auxiliary data become available.

The GTBL instruction is used to return various MPEG audio related constants from tables in read only memories 140 and 144. The GTBL instruction is nBAL,
Can return the value of BPCW, binding length or frame length. The information needed for this instruction is derived from the value stored in the header register in special register block 138. Additionally, when retrieving a BPCW value, a number for the BAL must be present in accumulator 110. The remaining instructions in the instruction set behave normally. The GANC instruction causes the audio decoder block 28 to retrieve the specified number of auxiliary data bits and place them in the auxiliary data buffer in the control status register block 22. This buffer register
It is 32 bits long and functions as a FIFO. When a predetermined number of bits have been loaded into the buffer, an interrupt is signaled to microprocessor host 12 that auxiliary data is present. When the microprocessor host 12 attempts to read the auxiliary data, the auxiliary data in the buffer is transferred into the auxiliary data register. This process allows more auxiliary data to be loaded into the buffer. In one optional mode of operation, if the auxiliary buffer is full, an interrupt is generated that stops all processing until the microprocessor host 12 reads the auxiliary data. In this mode, the auxiliary data buffer behaves like a FIFO, so no auxiliary data is lost. Another register is used to keep track of how many counts of auxiliary data bits are in the auxiliary data buffer. When the microprocessor host 12 reads this count, the value in the auxiliary data buffer is transferred to the auxiliary data register in the control status register block 22.

The operation of the audio decoder block 28 in decoding a data stream, obtaining synchronization with the data stream, concealing errors in the data stream, and managing buffers and other control functions will be described below with particular reference to FIGS. The description will be made based on a flowchart showing the details. Hardware filter operational unit 4 is a hardware filter arithmetic unit block 3
2 is a circuit diagram of one embodiment. FIG. In summary, the arithmetic unit block 32 functions to dequantize the samples retrieved from the arithmetic unit buffer 30 and store the results in the sample memory 150 shown in FIG. The arithmetic unit block 32 then retrieves a sample from the sample memory 150 and performs a fast cosine transform on the data,
The result of the conversion is written into a finite impulse response (FIR) memory 152 shown in FIG. Next, the operation unit block 32
Retrieves data from the FIR memory 152, performs an FIR filter operation on the data, and writes the result to the PCM buffer. The MPEG specification states that this dequantization process is a large 32x32 matrix operation. In accordance with the teachings of the present invention, large matrix operations have been replaced by fast Fourier transform operations implemented in the system shown in FIG. Hardware filter operation unit hardware theory
The bright operation unit block 32 comprises a mathematical unit 154 that receives one operand from the accumulator 156 and a second operand from the register 158. Accumulator 156 is loaded through multiplexer 160. One input of the multiplexer 160 is coupled to the output of the math unit 154. Multiplexer 160
Are coupled to a 16-bit bus connecting the arithmetic unit block 32 to the arithmetic unit buffer 30. A third input of multiplexer 160 receives a value from sample memory or SBB RAM 150. The fourth input of multiplexer 160 is either input a constant zero or is retrieved from multiplexer 162, which functions to provide a feedback path from the output of accumulator 156.

Register 158 is loaded through multiplexer 164. The multiplexer 164 is connected to the FIR RA
It has a first input coupled to the output of M152. The second input of multiplexer 164 is SBB RAM 1
It is coupled to 50 outputs. A third input of the multiplexer 164 is coupled to an output of the math unit 154. The fourth and last input of multiplexer 164 is coupled to the output of multiplexer 166.
A first input of multiplexer 166 is coupled to an output of multiplexer 164. Multiplexer 166
Is coupled to the output of scale factor read only memory 168. Scale factor read-only memory 168
Is a table of scale factors that contains 64 28-bit values and is used to combine subband values. The scale factor read only memory 168 is accessed using the scale factor index values generated by the audio decoder block 28 and located in the arithmetic unit buffer 30. A third and last input of multiplexer 166 is coupled to the output of C / D coefficient read only memory 170. Read-only memory 170 stores the C and D coefficients, which are also used to combine the subband data. Read only memory 170 is addressed using the value stored in address register 172. The scale factor read only memory 168 is addressed using the value stored in the address register 174. Register 17
The value input into 2,174 is retrieved from the 12 bits of the value output from arithmetic unit buffer 30. The arithmetic unit buffer 30 has a 9-bit CSBB
Accessed using ADDR address.

The mathematical unit 154 comprises a multiplier part and an adder / subtractor part in parallel therewith. The multiplier portion of the math unit 154 stores the first input in register 1
58 directly and a second input to multiplexer 176
Received from. A first input of multiplexer 176 is coupled to the output of accumulator 156, and a second input is coupled to the output of coefficient memory 178. Coefficient memory 178
Stores the 464 22-bit coefficients and the 9-bit coefficients
COEFF Addressed using ADDR value. The math unit 154 is configured to use a 3-bit CMD field and a 2-bit STATE field. The output of math unit 154 is buffer register 18
0, and these values are stored in buffer register 180
Is transferred into the PCM buffer 34. FIG. 5 is a block diagram of a system used to generate the addresses used by the arithmetic unit 32 shown in FIG. The address generator, generally indicated at 182 in FIG. The sequence generator 184 includes a state machine (or a state machine) operable to generate a state value output to the address read-only memory 186. Address read only memory 186 contains 416 5-bit index values output to three sets of address logic blocks. The first address logical block stores the STATE value output from the sequence generator 184 and the address read-only memory 1
9-bit CSBB from index output output from 86
CSBB address logic block 188 for generating ADDR value
It is. Similarly, the FIR address logic block 190
10-bit FIR Generates an ADDR value and the SBB address logic block 192 generates a 5-bit SBB Generate an ADDR value. The coefficient address logic block 194 directly generates a 9-bit COEF from the STATE value generated by the sequence generator 184. Generate an ADDR value.

FIG. 6 is a block diagram of one possible embodiment of the mathematical unit block 154 described with reference to FIG. The multiplier portion of math unit 154 receives the B operand. The B operand is a 22-bit value, which is divided into 6-bit values and input to the multiplexer 200. Multiplexer 200 outputs a 7-bit value to Booth encoder 202. Booth encoder 202 includes partial product generators 204, 206,
And 208 are driven. Partial product generator 204 is coupled to carry / store adder 210. Similarly,
Partial product generator 206 carry / store adder 21
2 and the partial product generator 208 carries /
It is coupled to a save adder 214. The A operand is input to partial product generators 204, 206, and 208. The carry / save adder 214 outputs a 29-bit carry output and a 30-bit save output to the 34-bit pipeline register 216. Pipeline register 216 outputs one carry output to multiplexer 218 and a 30-bit stored output to multiplexer 220. The carry and store output of pipeline register 216 is also provided to the input of partial product generator 204.

Multiplexer 218 functions to select any of the carry output from pipeline register 216 and the adder A operand received from accumulator 156 described with respect to FIG. Multiplexer 218
Outputs the selected value to the carry / save adder 222. The carry / store adder 222 is a multiplexer 22.
0 to the second input and the multiplexer 22
A value of 0 selects one of the carry output from the pipeline register 216 and a constant equal to 0. Carry / save adder 222 receives a third input from multiplexer 224, which outputs either constant storage 225 or the adder B operand received from R1 register 158 described with respect to FIG. select.
The carry / store adder 222 is a carry propagation adder 2
26, and outputs a carry output and a save output. The carry propagation adder 226 is a saturation detection / zero forced block 228.
Supplies a 31-bit value to The saturation detection and forcing block 228 receives the CMD signal and makes its output 0, or responds to the saturation condition or the CMD signal.
It can be the highest or lowest number representable by a bit field. Carry propagation adder 226 receives a signal from carry-in logic block 230. Carry-in logic block 230 receives the signal from carry storage register 232 and the CMD signal. Carry storage register 232 receives signals from carry logic block 234 which are combined into two separate 6-bit fields stored in pipeline register 216.

The mathematical unit 154 performs the functions of addition and subtraction. The math unit 154 may either pass the unchanged A operand or force its output to zero. The math unit 154 can also multiply the A and B operands to produce a 28 or 22 bit result. Math unit 154
Can round the value at its input to 16 or 18 bits. The operands to the adder / subtractor portion of math unit 154 are both in 3.25 format, indicating that three bits represent the whole number and 25 bits represent the fractional part of the number. The A operand to the multiplier portion of math unit 154 is also a 3.25 format number. The B operand to the multiplier part is a number in 2.20 format. Addition / subtraction, A-pass, zero-force, and full multiplication all produce results in 3.25 format. twenty two
Bit multiplication results in a 2.20 format. 16
Bit rounding and 18-bit rounding operations are
Yields a number of 1.15 and 1.17 formats. The multiplier portion of math unit 154 is a multi-cycle multiplier with a 5-cycle latency. Four clock cycles are spent on operations preceding pipeline register 216, and one cycle is spent on the remainder of math unit 154. Carry / save adder 222 and carry propagation adder 226 perform a full carry prefetch addition operation to produce the final result. The bottom part of the math unit 154 is also used for addition / subtraction, A-pass, 0-force and 16 and 18 bit rounding operations. The result of the multiplication is rounded by adding one to the bit position next to the least significant bit position. The round to 16 and round to 18 operations also add one to the bit position following the least significant bit position, then perform a range check on the result, and output the largest positive number or the least negative number. To numbers. Operation of the Hardware Filter Operation Unit In summary, the hardware filter operation unit block 32 is used in three modes. The first mode of operation is the dequantization of encoded samples using the scale factor index values retrieved from the bitstream and the coefficients stored in a read-only memory table. Second
Is the fast cosine transform. The third mode of operation is finite impulse response filtering. These three sequential operations result in PCM output data which is stored in PCM buffer 34 for retrieval by PCM output block 36.

In the notation used in the following description, Subban
d [k] is an input subband vector after decoding. N
[I] [k] is a composite matrix, and v [i] is a result of multiplication of the matrix N and the vector Subband [k]. v is a vector of dimension 64. In the MPEG audio decoder of the present invention, v is replaced by v 'of dimension 32 as described below.
This substitution offers two advantages. That is, since the dimensions of the problem to be solved (the number of multiplications / additions and the size of the memory) are reduced by half and the matrix is of the direct cosine transform, the product is realized using the fast direct cosine transform. This further reduces the number of multiplications and additions and the size of the memory. The subband synthetic MPEG specification specifies the following conversions: i = [0, 6
3], v [i] = SUM {N [i] [k] * Subband [k]} / k = [0, 31] where N [i] [k] = cos ((i + 16) * (2 * k + 1) * (pi / 64) = detCoef [i + 16] [k] Therefore, for i = [0, 63], v [i] = SUM ｛detCoef [i + 16] [k] * Subband [k] ｝ / K = [0,31] The equivalent shape is as follows: For i = [0,31], v ′ [i] = SUM ｛detCoef [i] [k] * Subband [k] ｝ / K = [0, 31] This is effectively realized as follows.

V ′ [32] = Fast. Cosine. Transform {Subband [k]} where v '= v' [i + 16] 0≤i≤15 v [i] = 0 i == 16 v [i] =-v '[48-i] 17≤i≤48v [I] = − v [i−48] 49 ≦ i ≦ 63 Due to the symmetry of the DCT coefficient, v ′ exhibits the following symmetry. v '[i] = v' [-i] v '[64-i] =-v' [i] v '[32] = 0. In the following description, V is an array of dimensions 1024 as described in the subband synthesis flow diagram of the MPEG specification. V is the input to the 16 tap FIR filter. Vector U of dimension 512 is the memory of the FIR filter. In the operation of the hardware filter of the present invention, V is replaced by V 'of dimension 512 and U is unchanged. The MPEG specification specifies that a vector V [1] configured as a FIFO containing a sequence of 16 consecutive vectors v [64].
024] is defined.

The vector U [512] is defined as follows. For i = [0,31] and j = [0,7], U [i + 64 * j] = V [i + 128 * j] and i = [32,63] and j = [0,7] U [i + 64 * j] = V [i + 64 + 128 * j] Therefore, the output sample S is, for i = [0, 31], S [i] = SUM ｛U [i + 32 * j] * D [i + 32 * j]｝ / j = [0,15] The actual instantiation is derived as follows. U as a function of V can be rewritten as: i =
[0,31], j = [0,14], and when j is an even number, U [i + 32 * j] = V [i + 64 * j] i = [0,31], j = [0,15] ], And j is an odd number, U [i + 32 * j] = V [i + 64 * j-32] Similarly to V, V '[512] is also 16 continuous vectors V'.
[32] representing the sequence (as defined above).

Using the above equation and the symmetry of V ', U can be expressed as a function of V' by the following equation:
If i = [0,15], j = [0,14], and j is even, U [i + 32 * j] = V '[i + 16 + 32 * j] i = 16, j = [0, 14], and if j is even, U [i + 32 * j] = 0 i = [0,16], j = [1,15], and if j is odd, U [i + 32 * j] = -V '[16-i + 32 * j] When i = [17,31], j = [0,14], and j is an even number, U [i + 32 * j] =-V' [48-i + 32 * j] When i = [17, 31], j = [0, 15], and j is odd, U [i + 32 * j] =-V '[i-16 + 32 * j] operation of the FIR filter During use, addressing of the FIR RAM 152 is simplified by using an address table. In the FIR filter equation, S [i] = SUM {U [i + 32 * j] * D [i + 32 * j]} / j = [0,15] or S [i] = SUM S (±) V '[Index + 32 * j] * D [i + 32 * j]} / j = [0,15] The index is calculated as follows. If i = [0,16] and j are even, index = i + 16 i = [0,16] and j is odd, index = 16−i i = [17,31] and j is even , Index = 48-i i = [17, 31] and j is odd, then index = i-16 Vindextable [32] contains the index for i = [0, 31].

In the formula of the FIR filter, S [i] = SUM ± (±) V '[index + 32 * j] * D [i + 32 * j] / j = [0,15] depends on the value of the index. Addition / subtraction operations (according to the expression of U as a function of V ') can be replaced by successive additions by changing the D of the FIR coefficients. Further, the size of the coefficient table is anti-symmetric, that is, D [i] =-D [512
-I] can be reduced by half. As a result, the coefficient table of 256 elements is calculated as follows. i = [0, 15], j = [0,
14], and if j is even, firCoef [i + 32 * j] = D [i + 32 * j] i = [0,16], j = [1,15], and j is odd, and i = [17,31], j = [0,15], firCoef [i + 32 * j] =-D [i + 32 * j] j = [0,14], and if j is even, firCoef [ 16
+32 j] = 0 must be included in the FIR filter as an exception.

Thus, FIR filtering is embodied as follows. For i + 32 * j ≦ 256, S [i] = SUM ｛V ′ [Vindextable [i]] + 32 * j] * firCoef [i + 32 * j] For i + 32 * j> 256, S [ i] = SUM {V '[Vindextable [i]] + 32 * j] * firCoef {512- (i + 32 * j)} Also, i = 16 and j = 0, 2, 4, 6, 8, 10, 12 ,
Or at 14, firCoef is forced to zero. Calculating embodiment of fast cosine transform reduces the coefficient table to 32 elements from 1k, also the amount of computation is greatly reduced, thus because it is possible to slower clock speed, unlike the matrix, Use flow and graph techniques. In the specific operation described above, the coefficients included are +1 and -1.
And fixed-point can be employed for a given required precision.

The computational flow involves two operators, a "butterfly" operator and a "subtraction" operator. The "butterfly" operator has the form y1 = x1 + x2 y2 = (x1-x2) * d, and the "subtraction" operator has the form y1 = x1 y2 = x2-x1. Here, the vector x [32] is the result of the preceding repetition, and the vector y [32] is the result of this repetition. There are 5 repetitions. The vector x [32] is initialized by the subband vector after its dequantification. However, then x
To simplify the addressing of the / y vector, it is first reordered to the "Hadamard order". x [i] = subband [h [i]] Here, h [i] is configured using the following algorithm. (K = 1; k <32; k * = 2), h

[0] = 0, (i = k-1; i ≧ 0; i ...), h [2 * i] = h [i]; h [2 * i + 1] = 2 * k-1-h [I]; this table is stored in some ROM and used by hw to reorder them when dequantizing subband samples.

Therefore, at each iteration, the vector x [32
] And y [32] must be addressed non-sequentially. In the hw embodiment, the address calculation at each stage of the repetition is replaced with a table lookup for simplicity. The butterfly and subtraction operators are applied sequentially and repeatedly as follows. for (channel = 0; channel <2; chanell ++) ｛for (k = 0; k <5; k ++) ｛for (i = 0; i <16; i ++) butterflyOperator (& subbandVector [channel] [butterflyOp1 [k] [I], & subbandVector [channel] [butterflyOp2 [k] [i], & subbandVector [channel] [butterflyOp1 [k] [i], & subbandVector [channel] [butterflyOp2 [k] [i], & FCTcoef [k] [i] ); for (i = 0; i <16; i ++) if (subOp1 [k] [1]) subOperator (& subbandVector [channel] [subOp1 [k] [1]], & subbandVector [channel] [subOp2 [k] [ i], & subbandVector [channel] [subOp1 [k] [i], & subbandVector [channel] [subOp2 [k] [i];｝} Here, the channels are the left and right channels, and “ butterflyOperator "and" subOperato
The first two independent variables of r "are y1 and y2, and the last two independent variables are x1 and x2.

K is a repetition counter from 0 to 4. butterflyOp1, butterflyOp2, subOp1, and sub
Op2 is an address table implemented in the hardware operation unit. These tables are configured as follows. ButterflyOp1 and butterflyOp2: for (k = 1, stage = 0; k <32; k * = 2, stage ++) for (j = 0; j <32−k; j + = 2 * k) for (i = 0 I <k; i ++) ｛butterflyOp1 [stage] [i + j / 2] = i + j; butterflyOp2 [stage] [i + j / 2] = i + j + k;｝ subOp1 and subOp2: for (k = 1, stage = 0; k <32 K * = 2, stage ++) for (j = 0; j <32−k; j + = 2 * k) ｛subOp1 [stage] [j / 2] = 0; subOp2 [stage] [j / 2] = 0; for (i = 1; i <k; i ++) ｛subOp1 [stage] [i + j / 2] = i + j; subOp2 [stage] [i + j / 2] = j + 2 * ki;｝ にROM with d-coefficient used
And is calculated as follows.

[0049] Subband Sample Dequantization Before use in the FCT, the subband sample code extracted from the bitstream is dequantized as follows. s' = c * scf (s + d) s = (sample code) / 2 ＾ (n-1) c = 2 ＾ n / step d = − (step-1) / 2 ＾ nn = number of bits of sample code scf = Scale factor associated with the sample Stage = Maximum number of stages used to encode the subband samples The value of the stage depends on the particular data stream and layer n associated with the grouping condition. Stage table is M
Given in the PEG specification.

The coefficients c and d are stored in a ROM table addressed by the layer, the number of bits, and the code completed by grouping (or no grouping).
The coefficients c and d are calculated as follows. if (layer == LAYER1) j = 15; else if (layer == LAYER2) j = 19; for (i = 1; i <j; i ++) ｛if (layer == LAYER1) n = bit tbl [1]; else if (smp tbl [1]! = 3) n = bit tbl [i] / 3; else n = bit tbl [i] +2/3; c [i] = (1 << n) / step tbl [i]; d [i] = (1-step tbl [i] / (1 <<n); step For each index i, step tbl represents the number of stages available for encoding the subband samples, bit tbl represents the number of bits used to encode the subband samples, and smp tbl is = 3 if the coding is grouped, 1 otherwise. And
i is the encoding characteristic of each subband sample. This is the "bit allocation" extracted from the bitstream.
(BAL) "information.

These three tables are given in the MPEG specification. Scale factor decoding table The scale factor is encoded when extracted from the bitstream. These are decoded by the hardware filter operation unit 32 using a decoding table configured as follows. rs = 1/2 ＾ (1/3) scftbl

[0] = 2; for (i = 1; i <63; i ++) scfTbl [i] = scfTbl [i-1] / rs; quantification release process The quantification release process is represented by the formula s = scf × c × ( SBB CODE
Perform -d). The math unit 154 receives the index value from the arithmetic unit buffer 30 and stores the index value in FIG.
This operation is performed by storing in registers 172 and 174, described above. The index values are obtained from the ROM tables 170 and 168 by using the c and d coefficients,
Search for a value related to the scale factor. The coded samples are retrieved from the arithmetic unit buffer 30, and the mathematical unit 154 performs successive multiplications after performing the subtraction to calculate the dequantized samples. The dequantized samples are stored in the SBB RAM 150 described with reference to FIG. Each sample is dequantized until all 32 quantized samples have been inserted into SBB RAM 150.

FIG. 7 is a flowchart showing the dequantization operation performed by the hardware filter operation unit block 32. The operation initializes the count equal to 0 step 25
It starts from 0. In step 252, the coded sample is selected using the index value retrieved from the arithmetic unit buffer 30, and the selected coded sample is loaded into the accumulator 156. In step 254, the D coefficient is retrieved from ROM 170 using the index value and R
One register 158 is loaded. In the next step 256, the math unit 154 computes R from the value in accumulator 156
1 register 158 is subtracted, and the difference is subtracted from the accumulator 15
Load into 6. In step 258, the C coefficient is retrieved from ROM 170 using the index value and the value of the C coefficient is
Loaded into register 158. In step 260, math unit 154 determines the product of the value stored in accumulator 156 and the value stored in R1 register 158. This product is again stored in accumulator 156. In the next step 262, the appropriate scale factor is scale factor ROM 168.
Is loaded into the R1 memory 158. In step 264, the math unit 154 compares the value in the accumulator 156 with R
One multiplies with the value in register 158 and loads the final dequantized sample into SSB RAM 150 at the location where the first value was found. In the next step 266, the CO
The UNT variable is incremented. In step 268, COU
Examine the NT variable and determine if it is equal to 32. If the COUNT variable is not yet equal to 32, the process returns to step 252 to retrieve a new index value from the arithmetic unit buffer 30. If the COUNT variable is equal to 32, perform the fast cosine transform described below with reference to FIG. It should be understood that the index values into the arithmetic unit buffer 30 are non-linear and are determined using the normal Hadamard order which selects the appropriate encoded samples in the appropriate order. The C and D coefficients and the scale coefficients are calculated using the Hadamard index.
Index from 0 to the value retrieved. Fast Cosine Transform Process After all of the dequantized samples have been inserted into SSB RAM 150, the arithmetic unit block changes modes and begins performing the fast cosine transform process. The fast cosine transform process effectively transforms 32 28-bit samples representing 32 different frequency levels at a single instant into 32 samples. These samples can be used sequentially to drive an external speaker for a period of 22 milliseconds. 32 sequential samples are 16 or 18
Output in any of the bits in PCM data format.

FIG. 8 is a flowchart showing a fast cosine transform operation performed by the hardware filter operation unit block 32. The method begins at step 270 with the COUNT1 variable set equal to zero. In the next step 272
The COUNT2 variable is also set equal to 0. Step 274
Initializes index values X and Y. In step 276, SS
The sample stored at location X in BRAM 150 is loaded into accumulator 156. In the next step 278, SS
The sample stored at position Y in B RAM 150 is R
1 Loaded into register 158. In step 280, math unit 154 sums the values stored in accumulator 156 and R1 register 158, and sums this sum to SSB R
Return to position X in AM 150 and load. Step 282
The math unit 154 determines the difference between the values stored in the accumulator 156 and the R1 register 158 and calculates this difference as R1
Return to register 158. In step 284, math unit 154 determines the difference stored in R1 register 158,
The product with the coefficient retrieved from the coefficient memory 178 is obtained.
This product is stored at location Y in SSB RAM 150. In step 286, the next values of the X and Y variables are set.
At step 288, the COUNT2 variable is incremented. In step 290, it is checked whether the value of COUNT2 has reached the value 16. If not, step 276
If the COUNT2 variable has reached 16, go to step 292 where the COUNT2 variable is again set equal to zero.

In step 294, variables X and Y are initialized again. At step 296, the sample stored at location X in SSB RAM 150 is loaded into accumulator 156. In the next step 298, the sample stored at location Y is loaded into R1 register 158.
In step 300, math unit 154 determines the difference between the values stored in accumulator 156 or R1 register 158,
This difference is loaded into location Y in SSB RAM 150.
In step 302, the next values of the X and Y variables are set. In step 304, the COUNT2 variable is incremented. In step 306, it is determined whether the value of COUNT2 has reached the value 16. If not, step 29
Returned to 6. If the COUNT2 variable has reached 16, go to step 308 and the COUNT1 variable is incremented. In step 310, it is determined whether the COUNT1 variable has reached the value 5. If value 5 has not been reached, step 2
Returned to 72. If the COUNT1 variable has reached the value 5, the FCT operation has been completed, and the FIR operation shown in FIG. 9 is started. When the fast cosine transform of the finite impulse response filtering data is completed, the arithmetic unit block 32 performs its final operation on the data, ie, the finite impulse response filtering operation. The first step in the finite impulse response filtering operation is to place the SSB into the FIR RAM block 152 (see FIG. 4) that stores 1024 24-bit values.
Copying the contents of the RAM 150. SSB RAM 1
The 24 most significant bits of each of the 32 values stored in 50 are copied into FIRRAM block 152. FIR filtering effectively averages the signal actually output to the PCM buffer by using not only the frame currently being decoded, but also a predetermined number of previous frames, and the actual PCM output from the arithmetic unit 32. Calculate the data.
When decoding starts, FIR RAM 152 is filled with zeros. Thus, the first sample output from the arithmetic unit 32 to the PCM buffer will necessarily filter out the zeros stored in the FIR RAM 152. The sound output by the decoder system of the present invention will gradually rise due to the operation of finite impulse response filtering. Similarly, sharp changes in the audio encoded in the bitstream are mitigated by the finite impulse response performed by the arithmetic unit block 32. FIR RAM 152 operates as a circular buffer, constantly updating the values stored in RAM by writing the latest set of received samples over the oldest set of samples stored in RAM 152. to continue. FIR RAM 152 is separated into two sections, each consisting of 512 24-bit values. The left channel is stored in one section and the right channel is stored in the other section.

Operation Performed by Operation Unit Block 32
Is in order on one channel and then on the other
Should be understood that In other words, a set of
 32 samples correspond to only one channel
Before processing the 32 samples corresponding to the left channel
32 samples for the right channel are dequantized and transformed
It is converted and filtered. FIR filtering is cumulative
It begins by loading 0 into the unit 156. Next
Sample is sequentially searched from the FIR RAM 152,
Multiplied by the coefficient retrieved from the number memory 178, the accumulator
It is added to 156. Then, in accumulator 156
The value is rounded to 16 bits. After rounding, this value
It can be checked whether it has been saturated during the accumulation process. Next
Weighted sum as a 16-bit PCM sample
 Output to PCM buffer 34. The filtering is FIR RAM 1
Performed for each 32 samples stored in 52
You. Therefore, each sample uses its own value
To the other 15 weighted sums output earlier.
Is added. FIG. 9 shows the hardware filter operation unit.
Impulse response filtering performed by the block 32
FIG. FIR operation sets COUNT1 variable to 0
The process starts from the setting step 312. At step 314
Is the SBB RAM 150 identified by the COUNT1 variable.
The value stored at the position in the [COUNT1 variable + LAST B
LOCK variable] to an address in FIR RAM 152
Be moved. LAST The BLOCK variable is the FIR operation shown in FIG.
Write to FIR RAM 152 from the previous point where the work was performed
To one position after the address of the last value
I have. LAST BLOCK variable is greater than or equal to 0
Smaller than 512. Written to FIR RAM 152 2
The four bit value is stored in SSB RAM 150
Consists of the 24 most significant bits of an 8-bit value.

From step 314, the routine proceeds to step 316, where the COUNT1 variable is incremented. Step 318
In, it is determined whether the COUNT1 variable has reached the value 32. If the COUNT1 variable has not reached the value 32, all of the values stored in SSB RAM 150 are still
It has not been copied into FIR RAM 152 and is returned to step 312. If the COUNT1 variable has reached a value of 32, The BLOCK variable is updated by adding it to its last value. In the next step 322, the COUNT1 variable is set to zero. In step 324, the COUNT2 variable is set to zero. Then step 32
At 6, the value 0 is loaded into accumulator 156.
In step 328, specified by the INDEX variable
A value is retrieved from a location in FIR RAM 152. This value is loaded into R1 register 158. The INDEX variable is equal to [COUNT1 variable + (COUNT2 variable x value 32)]. Step 328 effectively retrieves one sample from each set of 32 values present in FIR RAM 152. In step 330, the value in R1 register 158 is stored in coefficient memory 1
The coefficient retrieved from 78 is multiplied and the product is stored in R1 register 158. In step 332, accumulator 1
The value in 56 is added to the value in R1 register 158 and the sum is returned in accumulator 156. Step 332 is an FIR
All values (coefficient memory 178) retrieved from RAM 152
, Which is appropriately scaled by the coefficients retrieved from).

Next, proceeding to step 334, the COUNT2 variable is incremented. Step 336 is when the COUNT2 variable has the value 1
Check to see if you have reached 6. If not, the process returns to step 328. If the COUNT2 variable has the value 16
Is reached, the value stored in accumulator 156 is rounded in step 338 and saturation is checked in mathematical unit 154. In step 340, the rounded value is stored in PCM buffer 34. Next stage 34
In 2, the COUNT1 variable is incremented. Stage 3
44 checks whether the COUNT1 variable has reached the value 32. If the COUNT1 variable has not yet reached the value 32, return to step 324. If 32 has been reached, the routine is complete and the next 32 sample blocks shown in FIG.
The dequantization process described in (1) is started. The next block is the remainder for that channel corresponding to the block that has been processed so far, or in either the next set of audio samples of the opposite channel to be dequantized, transformed, and filtered. is there. FIG. 10 is a pin-out diagram showing one possible package that can accommodate the system of the present invention. The following table describes the contents of the signals shown in this pinout diagram. Pin name Pin number I / O Description A9 58 A8 63 A7 64 A6 65 A5 66 O DRAM address bus output A4 68 A3 69 A2 71 A1 72 A0 74 [BOF] bar 27 O Start of frame signal [CAS] bar 48 O DRAM column address strobe CLK90 28 I 90 kHz Reference clock input CLKOUT 8 O Buffered 24 MHz oscillator output D3 51 D2 52 I / O DRAM data bus D1 56 D0 57 [DCS] bar) 94 I Chip selection Pin name Pin number I / O Description DMPH1 26 O Decoded de-emphasis selection output DMPH0 25 [DSTRB] bar 93 I Data strobe FS1 23 O Decoded sampling frequency output FS0 22 GND (see drawing) Ground [IRQ] bar 101 O Interrupt request LRCLK 17 O Left / right channel selection output [MUTE] bar 117 I Audio output silence forced [OE] bar 44 O DRAM output enabled [OSCEN] bar 6 I Buffered oscillator output enabled OSCIN 3 I 24 MHz oscillator input Or crystal connection OSCOUT 4 O crystal connection (crystal low side) PCMCLK 14 I PCM clock input PCMDATA 20 O PCM serial data output [PLAY] bar 118 I Enable output of decoded audio [PTS] bar 11 O PCM output related to audio the presence of PTS No. [RAS] bar 50 O DRAM row address strobe [REQ] bar) 99 O data request [RESET] bar 116 I reset signal RD / [WR] bar 95 I read / write select Pin Name Pin Number I / O Description SADDR6 114 SADDR5 112 SADDR4 111 SADDR3 109 I Register Address Bus SADDR2 108 SADDR1 107 SADDR0 103 SCLK 19 O PCM Clock Output SDATA7 77 SDATA6 78 DATA DATA80 DATA use SDATA3 83 8-bit parallel data bus SDATA2 85 SDATA1 86 SDATA0 87 SIN 88 I serial compressed audio data input TCK 35 I JTAG clock input TDI 40 I JTAG data input TDO 37 O JTAG data output tEST 42 I tests enabling TMS 39 I JTAG Mode selection input VCC (see drawing) I 5V power [WAIT] bar 100 O Waiting request ... 3-state output [WE] bar 43 O DRAM read / [write] bar control audio decoding operation Flow chart Outline of operation

FIG. 11 shows the audio decoder block 28.
5 is a flowchart showing a high-level activity of FIG. The process begins at step 400, after a reset, where the system checks for the presence of the external buffer 26. Block 400
Figure 1 shows the process used to complete
2 will be described later. In step 402, the variables used by audio decoder block 28 are reset. The process used to reset the variables is described below with reference to FIG. Decision stage 40
4, the audio decoder block 28 outputs the data to be decoded to the input buffer 24 or the external buffer 2.
6 is determined. If no data is available, the system continues to check until data is available, and then proceeds to step 406 where the system attempts to restore synchronization in the data stream.
The process used by audio decoder block 28 to restore synchronization is described below with reference to FIGS. In step 408 after the synchronization is restored, the bit stream received by the audio decoder block 28 is decoded and passed to the arithmetic unit buffer 30. The process used to complete step 408 of FIG. 11 is described below with reference to FIG. Decoding loop 408 continues until all data in input buffer 24 or external buffer 26 has been decoded or an end-of-stream condition occurs. Initial DRAM Check Process FIG. 12 details the process used by audio decoder block 28 to check the size of available buffer memory. The process starts at step 410 where the DRAM flag is set. In step 412, 32 of predetermined bit strings (or strings) P2 and P1
Bit values are written to three different addresses. Next, in step 414, a READ operation from the first address is performed. In step 416, the value retrieved from address 149 is compared with the P2 variable. If this comparison is not valid, it means that address 149 does not exist,
It also indicates that there is no external DRAM. Accordingly, a branch is made to step 418, where the process is set up to use the internal SRAM buffer 24. The size of the PTS buffer is set equal to two words operable to store a single PTS in the input buffer 24. The process proceeds from step 418 to step 420, where the DRAM flag is cleared. The DRAM test process is completed at step 420.

In step 416, if address location 1
If the P2 value is retrieved from 49, the process proceeds to step 422.
Proceed to and the system is set up to use a 600 byte buffer. The size of the PTS buffer is 60
Set to 4 words in the 0 byte buffer. Step 424
At, the system checks for the presence of additional DRAM address locations by attempting to read from address location 8191. In step 426, the value retrieved from address 8191 is compared with the P1 value. If the comparison is not valid, branch to step 434 and TEST REG
The variables are tested. If TEST If the REG variable is not equal to one, the process ends. If TEST If the REG variable is equal to 1, proceed to step 436 where the size of the PTS buffer is set equal to 32 words. If stage 42
If the comparison at 6 is valid, then at step 428 the system is set to use a buffer size of 256 kilobits. The size of the PTS buffer is set to 1640 words in a 256 Kbit buffer. The next step 430 tests whether there is more DRAM by reading address 32767. Step 432
In step 2, the value retrieved from address 32767 is compared with the P2 variable. If the comparison in step 432 is not valid, proceed to step 434 again and test The REG variable is tested. If the comparison in step 432 is valid, then in step 433 the system is set to use a one megabit buffer. The size of the PTS buffer is set to 6554 words in a 1 megabit buffer.
Now go to step 434, TEST The REG variable is tested. Variable Initialization and Reset FIG. 13 shows the process of clearing and initializing registers used by the audio decoder block 28 and variables used in the audio decoding process. This process is
Beginning at step 438, setting the header register equal to zero. In step 440, the PTS register is set to zero. In step 442, the audio input word count
AIWC is set equal to zero and the second audio input word count AIWC2 is set equal to one. In the next step 444, the INTERNAL FLAG register is set equal to zero. This INTERNAL FLAG register contains NO RE
Includes AD, REPLAY, REPEAT, MUTE, EC, SYNTAX, and PTS flags. In step 446, the size of the audio buffer is determined by the PTS pointer (PTS pointer). PTR).
This sets the PTS in the first location that can be used to store the presentation timestamp value. Place PTR.

The INTERNAL FLAG register is a dedicated part of the audio decoder RAM 148 used by the audio decoder. NO The READ flag is set when no frame is read. The REPLAY flag indicates that the audio decoder block 28 is playing the last good frame. The REPEAT flag is an instruction from the microprocessor host 12 that normally repeats the last good frame so that some delay can be introduced to regain synchronization. The MUTE flag is set whenever the audio decoder block 28 outputs "no sound" or 0 frames. The error concealment (EC) flag is set in the audio decoder block 28.
Is set when it detects an error and performs some kind of error concealment. The SYNTAX flag is set when the audio decoder block 28 detects a syntax error. The PTS flag is set when a presentation timestamp is detected in the bitstream. In step 448, the audio pointer (AUDIO PTR) is set to 0. In the next step 450, the last good frame pointer (LGF
PTR) and the size of the last good frame (LGF SIZE
) Are set equal to zero. Stage 45
2, the current frame pointer (CF PTR) Variable and current frame size (CF SIZE) variable is set equal to 0. In step 454, the next frame pointer (
NF PTR) variable and next frame size (NF SIZE)
The variable is set equal to 0. In step 456, the reproduction count (REPLAY CNT) and skip counting (SKIP CNT)
Are set equal to zero. In step 458,
Bad bit count (BAD BIT CNT) Value is set equal to 0. In a final step 460, the leading header register is set equal to zero. The audio decoder block 28 now exits the process used to reset the variables and proceeds to step 404 described in FIG. 11, where the audio decoder performs an "audio input word count" (AIWC).
It waits for the data to be decoded by repeatedly testing a variable (which indicates that the data to be decoded has been placed by the system decoder block 20 in the input buffer 24 or the external buffer 26). Synchronization Acquisition FIGS. 14 and 15 illustrate the manner in which the audio decoder block 28 searches for synchronization characters and acquires synchronization in the incoming bit stream. The process uses the sync count (SYNC
CNT) variable as (SYNC LCK register value +1] is loaded at step 462. SYNC The LCK register value is used to specify how many sync words the audio decoder block 28 must detect before the audio decoder block 28 can be considered to have locked itself synchronously. This value is used by the microprocessor host 12. In step 464, the GSYN instruction is executed using 65,535 bit parameters. As described above, the GSYN instruction sequentially searches for bits in the bitstream until it finds a synchronization word or reaches the value specified in the immediate operand. 65,535 is the maximum value of the immediate operand of the GSYN instruction.

At step 466, a determination is made whether a synchronization word has been found at step 464. If a sync word has not been found, a determination is made at step 468 as to whether the automatic word counting function has been enabled.
If the automatic word counting function is enabled, step 478
Proceed to AUDIO PTR moves back by 11 bits. AUDIO
PTR is input buffer 24 or external buffer 26
The audio decoder block 28 points to a position currently being read. (If the sync word is found, the GSYN instruction sets the carry bit in the control status register block 22.) The automatic word count function is used when the system has not stored a good frame and
Also, using the microcode detailed in FIG.
BAD BIT Indicates that the CNT is not being tracked. Thus, if the automatic word counting function is enabled, the process simply returns to step 464 to perform another GSYN instruction. If it is determined in step 468 that the automatic word count function has not been enabled, the bad bits in input buffer 24 must be freed so that system decoder block 20 can overwrite these bits. . So go to step 470, BAD BI
T CNT and LGF The SIZE variable is used to free multiple bits in input buffer 24. Next, in step 472, the 6 in the input buffer 24 or the external buffer 26
5,524 bits are released. The number 65,524 is 11 bits smaller than the number used as the independent variable in the GSYN instruction. Since the sync word is 12 bits long, the last 11 bits retrieved can be 11 bits in the sync word.

In step 474, BAD BIT CNT variable is 0
Is set equal to The SIZE variable is set equal to 0. In step 478, the pointer pointing to the input buffer 24 or the external buffer 26 is manipulated to move backward in the bit stream by 11 bits. As mentioned above, these 11 bits must be re-examined when returned to step 464 since the last 11 bit read may be part of the incomplete synchronization. If a sync word has been detected in step 466, then in step 480 CF PTR [AUDIO PTR-12
Bit]. CF The PTR is used to actually point to the beginning of the frame starting from the sync word. Stage 482 uses the GBT and GBTL instructions to generate the next two bits of the header information bit stream.
Search for 0 bit. These 20 bits are stored in a header register in the control status register block 22. In step 484, the necessary routines to set up the frame are performed. These routines will be described later with reference to FIGS. The set up frame routine performs all necessary calculations before the audio decoder block 28 can begin decoding audio frames.

In step 486, the SYNTAX flag is examined. If the SYNTAX flag is 1, step 4
Go to 88. The SYNTAX flag is set in step 484 of this route.
Indicates that a syntax error was detected during frame setup. In step 488, the AUDIO PTR is
Decreased by 31 bit positions. The process is step 489
Continue to BAD BIT The CNT is incremented by one and returned to step 462. Step 488 effectively returns the pointer to a position one bit beyond the beginning of the sync word found in step 464. If the SYNTAX flag is not set in step 486, step 490
Go to SYNC Branches occur depending on whether the LOOKAHEAD flag is set or not. If SYNC LOOKAHEA
If the D flag is set, then in step 492 A
UDIO PTR to NF The value of PTR is loaded. Then, in step 494, the next 12 bits are searched to determine whether these bits consist of a sync word. If these bits do not consist of a sync word, step 49
AUDIO at 6 PTR is [CF PTR + 1 bit]. The process proceeds to step 489 and BAD
BIT Step 4 after the CNT is incremented by one
Returning to step 62, the synchronization word is searched again. At step 494, if the next 12 bits were a sync word, then at step 498 AUDIO PTR is [CF [PTR + 32 bits]. Next, in step 500,
The synchronization count is decremented. At step 490,
If SYNC If the LOOKAHEAD flag is not set, the process proceeds directly to step 500.

The process proceeds to FIG. 15 and at step 502 the synchronization count variable is examined to determine if it is equal to zero. If the synchronization count variable after decrement in step 500 is equal to zero, step 504 sets the synchronization state variable to one.
Set equal to 1. The value of this synchronization state variable indicates to the rest of the system that the required number of synchronization words have been detected, and that the system is in a locked synchronization state. If the sync count variable is not equal to 0 in step 502, the error concealment mode (ECM) variable is loaded in step 506 with the contents of the sync error concealment mode register set by the microprocessor host 12. The sync error concealment mode specifies what to do with the existing data while the audio decoder block 28 is searching for the required number of sync words before reaching the sync lock state. After the hidden mode is set, an error concealment routine is performed at step 508. The error hiding routine will be described later with reference to FIG. In summary, error concealment can use the last good frame of data, use the current frame, skip the current frame, or silence the output during the current frame. As explained below,
These options are controlled by the false-hiding mode variable.
Alternatively, it is specified by the presence or absence of the external buffer 26.
In step 510, the error concealment mode variable is examined. If the error concealment mode is MUTE, REPLAY or nothing, the audio frame is decoded at step 512. The process used by the audio decoder block 28 will be described later with reference to FIGS. The process proceeds from step 512 to step 514, where the audio decoder block 28 performs buffer management. If the error concealment mode indicates that the audio frame should be skipped, the process proceeds from step 510 to step 514. The method used by audio decoder block 28 to perform buffer management will be described later with reference to FIGS.

In step 516, SYNC LOOKAHEAD
The flags are checked. If SYNC LOOKAHEAD flag is set
If so, step 518 skips the audio bit stream.
Causes the next 12 bits in the stream to be skipped. Then
The process is returned from branch point C to step 482 in FIG.
You. If SYNC at step 516 LOOKAHEAD flag
If it is determined that is not set, step 520 proceeds to
Examine the 12 bits of the
Set. If the next 12 bits contain a sync word,
The process returns from branch point C to step 482 of FIG.
You. If the next 12 bits do not contain a sync word,
In step 522, the audio pointer
Pointer-11]. with this
The process returns from connection point B to step 489 of FIG.
You.Frame setup operation FIG. 16 shows when a headline is detected in a bit stream.
Audio decoder to set up the frame in
The process used by double lock 28 is shown. This process
Starts at step 524 of setting the heading interrupt.
It is. In step 526, the size of the frame is calculated and CF
Loaded into SIZE field. Frame size
See Figure 18 for the process used to calculate the
This will be described in detail. In step 528, CF SIZE is 0
Be compared. If CF If SIZE is equal to 0, then
Does not specify the size of the frame in the
Microprocessor host 12 specifies frame size
That you did not
Reams are free frames without specifying the frame size.
It means that it is a format. At step 530
Sets the synchronization count variable equal to 1 and then steps
532 at SYNC LOOKAHEAD flag is cleared
You. SYNC The LOOKAHEAD flag indicates that the audio decoder
Lock 28 finds another sync word at end of current frame
Whether or not to take preemption. Audio deco
Block 28 does not know the size of the current frame
From SYNC There is no way that the LOOKAHEAD process can be performed.
Does not exist. So in step 534 there is external DRAM
Is determined. If DRAM is present, input
Equals the number of frames that can be stored in the buffer
Variable N is set equal to 5 in step 536.
If no DRAM is present, go to step 538.
And the variable N is set equal to zero.

Returning to step 528, if CF SIZE is 0
Otherwise, step 540 sets variable N to [buffer size の CF SIZE] is set equal to the nearest rounded integer. In the next step 542, the variable N is compared with the value 1. If N is less than one, it means that there is not enough memory to store a good frame, so MAX at step 544. REPLAY variable is set equal to 0 and SYNC LOOKAHEAD flag is set equal to 0. If N is greater than or equal to 1, then at step 546 SYNC The LOOKAHEAD flag is set by the SYNC set by the microprocessor host 12. Set equal to LOOKAHEAD control register. In step 548, the current frame is a layer 1 MPEG
With or without audio data (or layer 2
(Including MPEG audio data). If the frame contains layer 2 MPEG audio data, step 550 sets the variable K equal to three. In step 548, if the current frame contains layer 1 MPEG audio data, in step 552, the variable K is set to 5
Is set equal to K represents the number of frames that must be able to be stored in input buffer 24 or external buffer 26 to allow maximum playback.

The process proceeds from steps 550 and 552 to steps
Proceeding to 554, the variable N and the variable K are compared. If N
If less than K, step 556 is MAX REPLAY variable
Set equal to 0. If N is smaller than K,
Note that the last good frame of the data can be played
Means that there are not enough resources. If N is K
If equal to or greater than, in step 558
 MAX The REPLAY variable is set equal to K-2. MA
X The REPLAY variable determines the action performed in step 558.
It is always either 1 or 3 as a result of the crop. Professional
Seth moves from steps 556, 558 and 544 to the steps of FIG.
Proceed to 560. Step 560 is a SYNC LOOKAHEAD flag
And MAX Determine if both REPLAY variables are equal to 0
I do. If both are 0, step 562 proceeds to “Automatic
A by examining the buffer size (ABS) flag
A determination is made whether the BS function is enabled.
If this feature is disabled, go to step 564
LGF SIZE is checked. If LGF SIZE goes to 0
If not, in step 566 the auto-input word count is
Is decremented. This count indicates that the heading has already been read.
It is decremented because it is done. Step 564
If LGF SIZE is determined to be equal to 0
If the input buffer 24 or the external
A plurality of bits in the buffer 26 are released. Released
The number of bits PTR-LGF PTR]
No. Then, in step 570, BAD BIT CNT goes to 0
Set equal, and in step 572 the LGF SIZE
Is set equal to 0. The process includes steps 566 and
Proceed from step 572 to step 574 where the ABS flag equals 1
Set properly. In the next step 576, NF PTR is
[CF PTR + frame size]
You. If the ABS flag is equal to 1 in step 562
Also, when it is determined that the process is completed, the process reaches step 576. Stage 56
SYNC at 0 LOOKAHEAD flag and MAX REPLAY
 If the variables are not simultaneously equal to 0, step 578 will again
 Check the ABS flag. If the ABS flag equals 0
If so, the program proceeds directly to step 576. if
 If the ABS flag is equal to 1, step 580 is an audio
The input word count is incremented, step 582 is ABS
 Clear the flag. Now the process goes to step 576
move on.Calculation of frame size FIG. 18 shows an audio file for calculating the frame size.
The process used by the decoder block 28 is shown. Step
Processes examines MPEG audio bits in headings
Beginning at floor 584. If MPEG audio bit
Is not set and the frame is MPEG audio
Step 5 if it indicates that it does not contain an
At 90, the SYNTAX ERROR flag is set. Also
If the MPEG audio bit is set,
586 checks the sampling frequency code. If sun
If the pulling frequency code is equal to 11, the process is
Go back to 590 and set the SYNTAX ERROR flag
You. It is invalid that the sampling frequency code is 11
It is a code. If the sampling cycle
If the wavenumber code is not 11, the layer code
The code is inspected. If the layer codes are 00 and 01,
Return to floor 590 and set the SYNTAX ERROR flag
You. If the layer code is 00 and 01, the layer code is null
It is effective. If the layer code is valid, step 592 is
Test the bit rate index. Bitrate index is 111
If 1, the process returns to step 590 again and returns to SYNTA
X ERROR flag is set. 1111 bitrate
Index is invalid. If the bit rate indexes are all 0
Then, in step 594, CF Microphone in the SIZE variable
Of the frame specified by the
The contents of the size control register are loaded. Bitley
If the index value is all 0, the bit stream
Is a free format bitstream
are doing. The microprocessor host 12
Use the size control register to set the audio decoder
Communicating the actual size of the frame to the lock 28
it can. If the microprocessor host 12
Step 5 if no value is inserted into the size control register of
94 indicates that the content of the frame size control register is CF
CF when loaded into SIZE variable SIZE variable set to 0
Set equal to All other bitrate values
If so, the process proceeds from step 592 to step 596
From the header information using the GET TABLE instruction.
Search the size of the system. When this operation is completed,
The size of the team would be in accumulator 110. Stage
596 stores the contents of the accumulator 110 in CF In the SIZE variable
Load.False concealment behavior FIG. 19 shows that when an error is detected in a certain frame,
Is in any state when the synchronization lock state has not yet been achieved.
The error concealment used by the audio decoder block 28
Indicate the process. The process uses the error concealment mode variable and
Start at step 600 comparing with the value 10 representing raw mode
Is done. If the playback mode is the current error concealment mode
If, for example, stage 602 Check SIZE. If LGF
If SIZE is not equal to 0, then in step 604 REP
LAY To the maximum regeneration value where CNT is either 1 or 3
Determine if they are equal. If REPLAY CNT is up to
If not, in step 606 the audio
The decoder 28 is LGF AUDIO PTR value PT
Later in the bitstream by loading into R
Repel. Step 608 is a REPLAY Increment CNT variable
Let me The process then proceeds to step 610, where
Load the next 32 bits into the read control register. Stage
At 612, the playback flag is set and the error concealment flag is set.
Set.

In step 600, if there is an error regarding the reproduction,
If it is determined that the hidden flag is not set,
At 614, silence mode is indicated by the 01 value.
Check error concealment mode to see if If wrong
If the hidden mode is the silence mode, step 616
NO READ flag is set. If step 602
At LGF SIZE is equal to 0 or step 6
REPLAY at 04 Even if CNT equals maximum regeneration
Step 616 is reached. Therefore, the error concealment method of the present invention
Is that if step 602 does not have the last good frame
If judged, silence the output of the current frame, or
If it is determined at 604 that the maximum number of plays has been reached
The output will be silenced. The process proceeds to step 616
Goes to step 618 and sets the COUNT variable equal to 0
Is done. In step 620, the value H003F is
It is written to address 0 in the buffer. Value H003F (hex
The number 003F) corresponds to two linked values. H3F is scaled
It consists of a coefficient index value.
SSB in the hardware filter operation unit block 32
Silences the output effectively when multiplied by a value. H00 is
Corresponding to a bit value of 0 per word
I have.

In step 622, the COUNT variable and the ADDRESS
Variable is incremented. In the next step 644, the COUNT variable is compared to the value 192. If still value
If not, return to step 620 and return to H00
3F is written to the next addressed location in arithmetic unit buffer 30. If the count in step 644 is 19
If so, step 646 sets the error concealment flag equal to one. At step 648,
Set error concealment mode equal to code 01 to indicate that silence was selected. Thus, if the silence operation has been reached from a failure in either the play or skip operation, the error concealment mode is reset, indicating that silence operation should continue in the future. If step 614 determines that the error concealment mode value is not equal to 01, step 650 determines whether the error concealment mode is equal to 11 which indicates a skipping process. If the error concealment mode is not equal to 11, it is assumed that the error concealment mode is equal to 00 and terminates the process without taking any action. Step 650
At, if the error concealment mode is determined to be equal to 11, step 652 determines whether the maximum number of frames has been skipped. If the maximum number of frames have been skipped, the process proceeds to step 616 where the silence operation described above is performed. If the maximum number of frames have not been skipped, step 654 is a SKIP CNT
Is incremented. In the next step 656, the SK
The IP and EC flags are set. Audio Frame Decoding Process FIGS. 20 and 21 are flow diagrams illustrating the process used by audio decoder block 28 to decode audio frames. This process involves the audio decoder block 28 examining the silence control register 66
It starts from 0. If the microprocessor host 12
If has set the silence control register, step 662 sets an internal silence flag. If the silence control register has not been set, or after the silence flag has been set in step 662, then in step 664 the audio decoder block 28 checks whether the microprocessor host 12 has set the skip control register. . If the microprocessor host 12 has set the skip control register, this state indicates that the frame should be skipped. Accordingly, the process proceeds to step 666, where the skip control register is cleared. If the skip control register is not set, step 668 decodes the header side information. Details of the process used to decode the header side information will be described later with reference to FIG. After decoding the header side information, at step 670 the audio decoder block 28 determines whether the bitstream is CRC protected. If the audio bitstream is CRC protected,
Step 672 searches for a CRC word using the GBT instruction,
Find the next 16 bits in the data stream. These 16 bits are stored in the CRC word variable. The process proceeds from step 672, or from step 670 if the data stream is not CRC protected, to step 674 where the layers of the data stream are examined. If the data stream is layer 1 data, step 676
Use the first process to decode the bit allocation data. This process will be described later with reference to FIG. If the data stream is Layer 2 data, step 678 decodes the bit allocation data using a second process. This process will be described later with reference to FIG. Then, in step 680, the scale factor selection information (SCFSI) is decoded. The process used to decode the scale factor selection information is described below with reference to FIG.

The process proceeds to step 676 or step 680
From step 682 to the audio decoder block 2
8 is NO Check the READ, REPEAT, and REPLAY flags. If any of these flags are set, the process proceeds from branch point B to FIG. If none of the flags are set, step 684 returns to C
Check RC error hiding mode. If the CRC error concealment mode is equal to 0, the process proceeds to branch point B. The fact that the CRC error concealment mode is equal to 0 means that the microprocessor host 12
Indicates that the command is to ignore CRC errors. If CRC error concealment mode is not equal to 0,
Step 686 examines the heading to determine if a CRC word is present. If the CRC word is not present, the process proceeds to branch point B, and if the CRC word is present, the process proceeds from branch point A to FIG. Referring to FIG. The process proceeds from branch point A to step 688,
Stored CRC retrieved from bitstream
The word and the calculated CRC word are compared. If CRC
If the word does not match the calculated CRC word, there is a CRC error in the bitstream. Thus, at step 690, a CRC error interrupt is set. In step 692, the error concealment mode is set equal to the CRC error concealment mode. In step 694, FIG.
Error concealment is performed according to the process described with reference to FIG.

Following the error concealment process in step 694, step 696 examines the ECM variables. If the ECM variable indicates that the current frame should be skipped, the process ends. If the ECM variable indicates that the last good frame should be played, the process returns to step 660 of FIG. If ECM
If the variable indicates to silence the output for the current frame, step 698 examines the layer. If the current frame is layer 1 audio data, the process proceeds from branch point D to step 716 of the figure (FIG. 21). If the current frame is not a layer 1 MPEG audio, the process proceeds to step 720 for decoding the subband information of the layer 2 audio data as shown. If in step 688 the CRC word and the calculated CRC word match, the process proceeds to step 700. Step 700 is also reached from junction B. At step 700, a determination is made whether the de-emphasis value has changed. If the de-emphasis value has changed, step 702 updates the de-emphasis control register and loads the new de-emphasis bit retrieved from the header register. In the next step 704, a de-emphasis change interrupt is set. Since the de-emphasis mode can change on a frame-by-frame basis in the bitstream, the audio decoder block 28 must check the de-emphasis value and notify the microprocessor host 12 of any changes. Similarly, the sampling frequency may change on a frame-by-frame basis. Accordingly, the process may proceed from step 704 or step 700 to step 706.
And a determination is made whether the sampling frequency has changed. If the sampling frequency has changed, step 708 loads the sampling frequency control register with the new sampling frequency bits retrieved from the index register. Step 710 then sets a sampling frequency change interrupt to notify the microprocessor host 12 that a change in sampling frequency has been detected. The process proceeds from step 710 or step 706 to step 712, where the current frame is branched based on the associated layer. That is, if the current data is layer 1 audio data, the process proceeds to step 714;
The scale factor information is decoded using a first process.
Details of this process will be described later with reference to FIG. The process proceeds from step 714 and branch point D to step 716.
Proceed to and the sub-band information is decoded using the first process. See FIGS. 27 and 2 for details of this process.
8 will be described later. At step 716, the process ends.

If the current data is layer 2 audio data, the process proceeds to step 718, where the scale factor information is decoded using a second process. Details of this process will be described later with reference to FIGS. The process proceeds from step 718 or step 698 to step 720, where the sub-band information is decoded using a second process. See FIGS. 31 and 32 for details of this process.
It will be described later with reference to FIG. The process ends at step 720. Side Information Decoding Process FIG. 22 shows a flowchart of a process used by the audio decoder block 28 to decode side information included in a heading. The process begins at step 722 where audio decoder block 28 checks for a mode contained in the header stored in the header register. If the mode field in the heading contains 00 or 10, it indicates that stereo or dual channel data is included in the audio frame. In step 724, the number of channels (
#CHANNELS) Variable is set equal to 2. Stage 72
6 sets the BOUND variable equal to 32. If it is determined in step 722 that the mode field contains 11, it means that the audio frame contains monaural information. Accordingly, the process proceeds from step 722 to step 728, where the #CHANNELS variable is set equal to one. In step 730, the BOUND variable is set to 0
Is set equal to If it is determined in step 722 that the mode field contains 01, the audio frame contains joint stereo audio data. Full stereo data contains samples separated in all 32 frequency ranges. In contrast, monaural audio data uses the same samples for the right and left channels in all 32 frequency ranges.
The combined stereo data uses the same samples in some frequency bands and separate samples for the right and left channels in other frequency bands,
Bitstream compression has been achieved. The BOUND variable is
It indicates how much of the frequency band R> 32 is separately encoded. Accordingly, the process proceeds from step 722 to step 732, where the #CHANNELS variable is set equal to two. In step 734, a BOUND value associated with the current audio frame is retrieved using a GET TABLE command. Step 726, Step 730, or Step 73
The process ends at 4. Layer 1 Bit Allocation Decoding Process FIG. 23 shows the process used by audio decoder block 28 to decode bit allocation information when the bitstream is layer 1 audio data.
The process begins at step 736 with setting the SBB variable equal to zero. In step 738, the channel variable
(CH) is set equal to 0. Stage 740 is an internal
NO Check the READ flag. If NO If the READ flag is set equal to one, then at step 742 the bit / codeword (BPC) variable is set equal to zero. If NO If the READ flag is not set, step 744 causes the next four bits to be retrieved using the GBTC instruction and stores them in the bit allocation (BAL) variable. In step 746, a GET TABLE instruction is used,
Search BPC using 4 bits stored in BAL variable. The value returned by the GET TABLE command is stored in a BPC variable. In step 748, the BPC variable is shifted 6 bits to the left, allowing it to be linked to the scale count index associated with that sample. Stage 75
At 0, the shifted BPC value is stored in the CH and SBB in the scratch RAM of the audio decoder block 28.
It is stored at the vector position given by the variable.

In step 752, a decision is made based on the channel value. If the channel is equal to 0,
In step 754, the CH variable is incremented.
Then, in step 756, the SBB value is compared to the BOUND variable. If the SBB variable is smaller than the BOUND variable, which means that the SBB value is still within the stereo range of the combined stereo data set, the process loops back for the second channel associated with that SBB value. Perform the same operation. If the SBB value is determined to be greater than or equal to the BOUND variable in step 756, it means that the SBB value is within the mono range of the combined stereo spectrum. Thus, step 758 is a step in which the scratch RAM
The value associated with channel 0 and its SBB value is copied to a location vectorized according to the same SBB and channel 1. The process proceeds from step 758, or directly from step 752 to step 760 if the CH value is equal to one, where the CH value is reset to zero. In the next step 762, the SBB value is incremented. Stage 7
At 64, the SBB value is compared with the number 32. If the SBB value is less than 32, the process loops back to step 740, otherwise the process ends. The process shown in FIG. 23 is a left aligned 64 BP
The C value is stored in the scratch in the audio decoder block 28.
Complete by storing in RAM. Layer 2 Bit Assignment Decoding Process FIG. 24 shows the process used to decode bit assignment data when the frame is layer 2 audio data. The process begins at step 766, where CH
The variable is set equal to 0. In step 768, SB
The B variable is set to 0. In step 770, NO READ
The flags are checked. If NO If the READ flag is set, then at step 772 the BPC value is set equal to zero. NO at step 770 If it is determined that the READ flag has not been set, step 774 is
Use the GET TABLE statement to find the value of nBAL using the SBB value and information from the header. Step 776 uses the GBTC instruction to retrieve a plurality of data bits in the bitstream corresponding to the value of nBAL retrieved in step 774. The next step 778 is to use the value of the BAL variable
Issue a GET TABLE instruction to search for grouping bits / codeword (GBC) values and specify the bits to search. For layer 2 MPEG audio data, a single BPC
Additional compression is achieved by combining the values with groups of three sets of samples. Thus, the BPC becomes a grouping bit / codeword.

In step 780, the GBPC value is shifted to the left by 6
Feed by bit position. Tier 2 has 3 sets of 32 pairs of SBB
The values are grouped into one block (also called granules). Therefore, in step 782, the GBPC value vectorized with the set number, the number of channels, and the SBB value is stored in the location of the scratch RAM. In step 784, the GBPC values for the second and third granules are
Copied at 82 from the stored value. Step 786
In, NO The READ flag is checked again. if
NO If the READ flag is set, then at step 788 the GBPC value is set equal to zero. If NO
If the READ flag has not been set, step 790 compares the current SBB value with the BOUND value. If SBB
If the value is not less than the BOUND value, the SBB value is within the mono range of the combined stereo spectrum, and in step 792 the GBPC value is set equal to the GBPC value associated with the preceding channel. If the SBB value is B
If less than the OUND value, the current SBB value is within the stereo range of the combined stereo spectrum. Therefore step 794
Use the GBTC instruction at to retrieve from the bitstream a number of bits equal to the nBAL variable. The retrieved bits are stored as BAL variables. Step 796 is the GE
Use the T TABLE instruction to retrieve the GBPC value from the BAL variable. In step 798, the GBPC value retrieved in step 796 is shifted left 6 bits. The process proceeds from step 788, step 792, and step 798 to step 800, where the GBPC value is stored in a vector of scratch RAM set numbers, number of channels, and SBB values, similar to the operations performed in step 782. Stage 8
In 02, the values of the second and third sets of GBPC variables are
At 00, the first set is copied from the stored values. The second and third sets of values are also stored in the scratch RAM. In step 804, the SBB value is incremented.
In step 806, it is determined whether the SBB value is greater than or equal to the number 32. If the SBB value is greater than or equal to 32, the process ends. If the SBB value is less than 32, the process proceeds to step 7.
Returning to step 70, the operation for the next SBB value is performed. Scale Factor Selection Information Retrieval Process FIG. 25 shows the process used to retrieve scale factor selection information associated with Layer 2 MPEG audio data. The three sets in a block of layer 2 audio data may use independent scale factors, or may share scale factors with other sets in the block for each subband. The scale factor selection information uses a 2-bit field to indicate the mode of the scale factor shared by each subband. The process begins at step 808, where the SBB variable is set equal to zero. In step 810,
The CH variable is set equal to 0. In step 812, the CH variable is compared to the #CHANNELS variable. if
Step 814 if the CH variable is larger than the #CHANNELS variable
Increments the SBB value. Then step 816
At which the CH variable is set equal to 0. If CH
If the variable is less than the #CHANNELS variable, step 818 compares the GBPC value for the particular granule, channel, and number of subbands to the value zero. If this value is equal to 0, it means that there are no bits / codewords assigned to that subband, and the process does not need to retrieve any scale factor selection information. If the GBPC value for a given set, channel, and subband is not zero, step 820 returns the set, channel, and subband by retrieving the next two bits from the bitstream using the GBTC instruction. For the scale factor selection information of. These two bits are stored in the scratch RAM at the locations vectorized by the #CHANNELS and SBB numbers. In step 822,
CH variable is incremented. In step 818
If the GBPC value is determined to be equal to zero, the process also reaches step 822 directly. The process proceeds from step 822 and from step 816 to step 824, where the SBB value is
Compared to 32. If the SBB value is less than 32, the process returns to step 812 to retrieve the scale factor selection information of the opposite channel or to increment the SBB number. Layer 1 Scale Coefficient Index Decoding Process FIG. 26 shows that the audio decoder block 28
G illustrates the process used to decode the scale factor index of the audio data. The process begins at step 826 where the SBB variable is set equal to zero. Step 828
Now the CH variable is set equal to 0. Step 830
Indexed on CH and SBB variables
The value of BPC is read from the scratchpad memory and a determination is made as to whether the BPC stored at that location is equal to zero. If the value is 0, step 832 is 63
, Ie, set H3F equal to the SCF index variable. Setting the scale index value to 63 will cause the sub-band to be silenced when the hardware filter arithmetic unit 32 retrieves the scale factor from memory using this scale index. If the scale index value is 0, the largest scale factor is searched from the scale factor ROM associated with the hardware filter operation unit 32. If the scale index value is 63, a scale factor of 0 is searched. You. If the BPC value retrieved in step 830 is not equal to 0, step 834 sets the SCF index variable equal to the next 6 bits in the bitstream. Step 836 examines the MUTE flag. If MUTE
If the flag is set, the subband is silenced and the process proceeds to step 832, storing the number 63 as the SCF index variable as described above.

If it is determined in step 836 that the MUTE flag has not been set, then in step 838
The scale index is added to the value of the attenuation control register selected according to the CH variable. The decay control register contains certain values that can be set by the microprocessor host 12. When a value is added to the scale index, the final scale factor (retrieved) for a particular subband increases, the volume of that subband decreases, and one channel is attenuated relative to the other. Become so. Step 838 selects an attenuation control register as a function of the channel. That is, the attenuation control register can be thought of as a right / left balance switch programmable by the microprocessor host 12. According to an alternative embodiment of the present invention, the attenuation control register is selected based on channel and subband. In this manner, the microprocessor host 12 can control a programmable 64-channel equalizer by attenuating various subbands in the first and second channels. This also allows a 64-channel equalizer to be implemented in the digital domain, thereby preventing loss and distortion associated with the equalizer implemented in the analog domain.

At step 840, it is determined whether the attenuated scale factor index is greater than 63. If the scale factor index after adding the contents of the attenuation control register is greater than 63, then in step 832 the SCF index variable is set to 63
Is loaded. The process includes steps 832 and 840
From step 842, the scale factor index of the particular channel and subband is stored in the BFC stored in scratch RAM.
Linked to This connected pair is a scratch RAM
Is re-inserted at the same address position. The process proceeds from step 842 to step 844 where the CH variable is examined.
If the CH variable is not equal to 1, the process proceeds to step 8
Branch to 46 to make the CH variable equal to one. In a next step 848, it is determined whether the audio stream is using two channels. If the audio stream is using two channels, the process returns to step 830 to retrieve the scale factor index associated with the channel 1 subband. If not, the process proceeds to stages 848 to 850 where the BPC and scale factor index pair for channel 0 is copied to the address location associated with the same sub-band of channel 1. Is done. The process then returns to step 844.

In step 844, if the CH variable equals one, step 852 resets the CH variable to zero. At step 854, the SBB variable is incremented. In step 856, the SBB variable is compared to 32. If the SBB variable is less than 32, the process returns to step 830 to decode the next subband scale factor index. In step 856, if the SBB variable is 32
If so, the process ends. Layer 1 Subband Information Decoding Process FIGS. 27 and 28 illustrate the process used by audio decoder block 28 to decode the subband information of Layer 1 MPEG audio data. This process determines whether the hardware filter arithmetic unit block 32 has emptied the arithmetic unit buffer 30 step 8.
It starts from 58. This determination is made by examining the registers in the special register block of the audio decoder block 28. Arithmetic unit buffer 30
If is found empty, step 860 moves the concatenated BPC and scale factor index from the scratch RAM associated with audio decoder block 28 to arithmetic unit buffer 30. In step 862, the BLOCK CNT is set equal to 0. Step 86
At 4, the CH variable is set equal to 0. Step 86
At 6, the SBB variable is set equal to zero. Step 86
8, the BPC value selected by the CH and SBB variables is Loaded in BITS.
The next step 870 is to use the GBT instruction to Causes the bitstream to retrieve a number of bits equal to the value of BITS, and stores the retrieved bits in the SAMPLE variable. Step 872 returns [16-NUM Causes the SAMPLE variable to shift left by the number of bits equal to the value of the BITS variable. This process left justifies subband samples in a 16-bit field.

In step 874, a branch is taken. If block count (BLOCK If the CNT) variable is equal to zero, the shifted sample is stored directly in operation unit buffer 30 at step 876. If BLOCK
If the CNT variable is not equal to 0, the shifted sample is stored in a scratch RAM associated with audio decoder block 28 at step 878. The process proceeds from step 876 or from step 878 to step 880, where a branch is taken depending on the CH variable. If the CH variable is not equal to 1, step 882 is
Set CH variable equal to 1. Step 884 is the SBB
Compare the variable with the BOUND variable. If the SBB variable is B
If so, the current subband is within the stereo range of the combined spectrum and the process returns to step 868 to search for a sample associated with the second channel. If the SBB variable is greater than the BOUND variable, the method proceeds to step 886 where the transmitted sample written to memory is sent to the scratch RAM associated with the opposite channel or any second in the arithmetic unit buffer 30. Is copied to the location. The process is at step 88
6 or from step 880 to step 888, where CH
The variable is set equal to 0. In step 890, the SBB
Variable is incremented. In step 892, SB
The B variable is compared to the value 32. If the SBB value is not greater than or equal to 32, the process returns to step 868. If at step 892 SBB
If the value is greater than or equal to 32, the process proceeds to Node A following FIG.

In step 894 of FIG. The CNT variable is incremented. In step 896, the BLOCK
A branch is taken depending on the CNT variable. If the BLOCK was incremented in step 894 If the CNT variable equals 1, the process proceeds to step 898 where the PTS flag is examined. If the PTS flag is set, at step 900 the PTS interrupt is checked. If PTS interrupts have been enabled, at step 902 the PTS tag is set. Then, in step 904, the start of frame (BOF) tag is set. PC
The M output block 36 uses the PTS and BOF tags to set the BOF signal and PTS interrupt when outputting data on the PCM data pins. If the PTS flag has not been set in step 898 or if the PTS interrupt has not been enabled in step 900, the process proceeds directly to step 904. If step 896 is a BLOCK If you decide that CNT is not equal to 1,
The process proceeds to step 906 and the operation unit buffer 3
Wait until 0 is empty. Arithmetic unit buffer 30
Is emptied by the hardware filter arithmetic unit block 32, step 908 transfers the samples stored in the scratch RAM to the arithmetic unit buffer 30. In step 910, the PTS and BOF tags are cleared. The process proceeds from step 904 or step 910 to step 912 and sets a flag indicating that the arithmetic unit buffer 30 is full. Next Step 91
In 4, BLOCK CNT is compared to the value 12. If BLO
CK If CNT is less than or equal to 12, the process returns to step 866 of FIG. In step 914, if BLOCK If the CNT is greater than 12, the process ends. Layer 2 Scale Coefficient Index Decoding Process FIGS. 29 and 30 show details of the process used by audio decoder block 28 to decode scale coefficient index information for Layer 2 MPEG audio data. The process starts at step 916 where the SBB variable is set equal to zero. In step 918, the SBB variable is compared to the number 32. If the SBB variable is not less than 32, the process ends. If the SBB variable is less than 32,
In step 920, the CH variable is set equal to zero. In step 922, the CH variable is compared with 2. if
If the CH variable is not less than 2, at step 924
The SBB variable is incremented and returns to step 918.
If the CH variable is less than 2, at step 926
The CH variable is compared with the #CHANNELS variable. If the CH variable is not less than the #CHANNELS variable, which means that the data is monaural data, the scale factor index information for channel 0 is copied in step 928 to form the scale factor index information for channel 1. Is done. FIG.
As shown in step 928 of step 9, there is one scale factor index for each subband in each channel in each set of blocks of audio data. The process proceeds from step 928 to step 930 where the CH variable is incremented. The process then returns to step 922.

In step 926, if the CH variable is #CHAN
If so, step 932 compares the GBPC value of set 0 of the current channel of the subband to zero. If the indicated GBPC value is equal to 0, the process proceeds from branch point B to FIG. If instructed
If the GBPC value is not equal to 0, the process branches to stage 4 9
Proceed to 34. This step 934 branches based on the scale factor selection information audio data retrieved using the process described above with respect to FIG. As described in detail above, the scale factor selection information identifies which sets within a block of layer 2 audio data share the same scale factor index value. If the scale factor selection value is 00,
This indicates that each set in a certain block has an independent scale factor index value. In this case, the process proceeds to step 936 where three consecutive GBT instructions have been executed to set 0, associated with the indicated channel and subband values.
Scale factor index information for 1 and 2 is retrieved. 6
The scale factor index values for the bits are stored in the scratch RAM as they are retrieved from the bitstream. If the value of the scale factor selection information is 01, the process proceeds from step 934 to step 938, where the next 6 bits are retrieved to give the given channel and given subband set 0
Is stored as a scale factor index. The same 6 bits are then copied as the scale factor index for the given channel and subband set 1. The next 6 bits are retrieved and stored as the scale factor index for the indicated channel and subband set 2.

When the value of the scale factor selection information is 10, it means that all three sets use the same scale factor index value. In this case, the process proceeds to step 934.
From step 940, the next 6 bits are retrieved from the bitstream and correspond to the scale factor index of sets 0, 1, and 2 associated with the indicated channel and subband.
At one location as a scale factor index. Finally, if the scale factor selection information value is 11, the second and third
, Share the scale factor index values, and the first set has separate scale factor index values. Accordingly, the process proceeds from step 934 to step 942, where the next six bits are retrieved and stored as a scale factor index for the associated channel and subband set 0. The next six bits are then retrieved and stored in two locations corresponding to the set 1 and 2 scale factor index values associated with the indicated channel and subband. The process proceeds from step 936, 938, 940, or 942 to node C, which continues to FIG. FIG.
A zero step 944 is reached from node C and the MUTE flag is checked. If the MUTE flag is set, it indicates that the output of the current frame should be silenced. Accordingly, the process proceeds to step 946, where each set 0, 1, ... associated with the indicated channel and subband.
The value 63 is overwritten on the scale factor index information of (2) and (2).
As mentioned above, if the scale factor index value is 63, a scale factor of 0 is retrieved when processed by the hardware filter operation unit block 32 and the output is silenced.

If the MUTE flag has not been set, step 948 sets the set number variable equal to zero.
In step 950, the indicated set number, number of channels, and subband scale factor index are added to the value of the indicated channel attenuation control register. This process is illustrated in FIG.
Is similar to the process described with respect to step 838 of FIG. The attenuation control register value acts as a balance control to selectively attenuate either the right or left channel. By adding a number to the scale factor index value,
The output volume of a given sub-band is eventually reduced. As also mentioned above, according to an alternative embodiment of the present invention, the attenuation control value can be programmed for each sub-band so that a 64-channel equalizer programmable in the digital domain can be realized. It is. The process proceeds from step 950 to step 952, where the attenuated scale factor index is compared to the value 63. If the adjusted scale factor index is greater than 63, step 954 loads equation 63 as the scale factor index value for the given set number, number of channels, and subband value. If step 952 determines that the adjusted scale factor index is not greater than 63, step 956 increments the set number.
In step 958, the set number and the value 3 are compared.
If the set number is less than 3, the process proceeds to step 950.
And the attenuation control is performed for the next set. Step 960 is reached in step 958 if the set number is not less than 3, or is reached directly from step 946, where the given set number, number of channels, and subband scale factor index indicate that set number, It is linked with the number of channels and the GBPC value of the subband. The concatenated values are stored in a scratch RAM associated with audio decoder block 28. The process then proceeds from connection point A to step 9 in FIG.
It is returned to 30. Layer 2 Subband Information Decoding Process FIGS. 31 and 32 illustrate the process used by audio decoder block 28 to decode the subband information of Layer 2 MPEG audio data. The process starts at step 962 where the audio decoder block 28 waits until the arithmetic unit buffer 30 is emptied by the hardware filter arithmetic unit block 32.
When the arithmetic unit buffer 30 is empty, the concatenated pair of GBPC value and scale factor index value is transferred from the scratch RAM associated with the audio decoder block 28 to the arithmetic unit buffer 30 at step 964.
In step 966, the BLOCK The CNT variable is set equal to 0. In the next step 968 if BLOCK If the CNT variable is not less than 12, the process ends. If B
LOCK If the CNT variable is less than 12, at step 970 the SBB variable is set equal to zero. Step 972
Now the SBB variable is compared to 32. If the SBB variable is
If less than 32, the process proceeds from branch point B to FIG. If the SBB variable is not less than 32, BLOCK at step 974 The CNT variable is incremented. In step 976, the incremented B
LOCK The CNT variable is compared to 1. If BLOCK If the CNT variable equals 1, the process proceeds to step 978 where P
Check the TS flag. If the PTS flag is set, step 980 determines whether PTS interrupts are enabled. If a PTS interrupt is possible,
Step 982 sets the PTS tag. To step 984, if the PTS flag is not set at step 978, or if the PTS interrupt is not enabled at step 980, or directly from step 982, the BOF tag is set. PTS tag and BOF
The tag is used by the PCM output block 36 to output the data to the PCM data pin when the BOF signal and P
Set TS interrupt.

In step 976, if BLOCK CNT variables
If is not equal to one, then at step 986 the audio
The decoder block 28 includes an arithmetic unit buffer 30
The hardware filter operation unit block 32
Wait until empty. Arithmetic unit buffer 30
When is empty, step 988 checks for subband samples.
The scratch associated with the audio decoder block 28
H Transfer from the RAM to the arithmetic unit buffer 30. Step
On floor 990, both PTS and BOF tags are cleared
You. The process starts at step 990 or step 984
Proceed to 992 and the arithmetic unit buffer 30 is full
Is set. Process is a stage
Return to step 968 from 992. The CH variable in FIG.
Step 994, which sets equal to 0, arrives at branch point B
Reach. Step 996 compares the CH variable with 2. if
 If the CH variable is not less than 2, step 998 is SBB
Increments a variable. The process then turns
A returns to step 972 in FIG. In step 996
And if CH variable is less than 2, go to step 1000
Where the CH variable is compared to 1. If CH variable is 1
If they are equal, step 1002 is the current value of the SBB variable and BOUND
 Compare with variable. If the current value of the SBB variable is BOUND
If so, step 1004 is the top level GBPC
Compare the number to the 1 The most significant bit position of GBPC is 1
Is that the audio data is grouped
It is instructed. If audio data is glue
If so, in step 1006 the group decryption
Is performed. Audio decoder block 28
The process used to perform loop decoding is shown in FIG.
It will be described later with reference to FIG.

If the most significant bit of the GBPC value indicates that the bitstream is not grouped, step 1008 performs a GBT instruction using the GBPC value for the indicated channel and subband. Retrieves the first set of samples of the indicated channel and the indicated subband from the bitstream,
Provides the number of bits to be searched by the instruction. The next step 1010 left justifies the retrieved bit by shifting the retrieved bit left by [16- GBPC value]. In step 1012, step 1008
In the same manner as, a second set of samples of the indicated channel and the indicated subband is searched. Stage 101
4 adjusts the searched sample to the left by performing left shift as described above. Stage 101
At 6, a third set of samples corresponding to the indicated channel and the indicated subband is retrieved in the same manner as steps 1008 and 1012. Step 1018
Then, the left position adjustment of the searched sample is performed using the same left shift method. SBB in step 1002
If it is determined that the value is not less than the BOUND value,
The indicated SBB value is within the mono range of the combined stereo and the process proceeds to step 1020 where the samples of channel 0 of the indicated SBB values of sets 0, 1, and 2 are duplicated to form sets 0, 1, and Channel 1 samples of the indicated SBB value of 2 are created. Samples made in step 1020, and steps 1010, 1014, and 101
The samples made at 8 are stored in the scratch RAM 142 associated with the audio decoder block 28 until reaching the step 988 described in FIG. 31, at which point the samples are transferred to the arithmetic unit buffer 30. You. The process comprises steps 1020, 1
006, and proceeds from step 1018 to step 1022, where CH
Variable is incremented. The process is stage 102
2 returns to step 966. Group Decoding Process FIG. 33 shows the process used by audio decoder block 28 to perform group decoding. The samples are group coded when three consecutive samples of the same channel and subband are grouped together,
It is coded using a single value that is 5, 7, or 10 bits long. The process shown in FIG. 33 retrieves a 5, 7, or 10 bit field and decodes that field to provide a given channel and subband set 0, set 1,.
And make the sample associated with set 2. The process uses the GBT instruction to
Beginning at step 1024, the number of bits equal to the PC value is retrieved from the bitstream. The BPC value is the five least significant bits of the GBPC value. These bits are loaded into the CODE variable. In step 1026, various branching is performed again using the BPC value. That is, if the BPC value is 5
If so, the process proceeds to step 1028 where the CODE variable is set equal to [CODE variable $ 3] using integer division. This quotient is stored again as a new CODE variable. In step 1030, the remainder of the integer division is stored and stored as a sample associated with a given channel and subband set 0. In step 1032,
The sample is shifted 14 bits to the left, and the sample is left justified. In step 1034, the CODE variable is again divided by three using integer division. This quotient is new
Store as CODE variable. As shown in step 1036, the remainder of the integer division constitutes a sample of a given set of channel and subband values. At stage 1038, the next sample is shifted left by 14 bit positions and left justified. In step 1040, the final value of the CODE variable is finally stored and constitutes a sample of a given channel and subband set 2. In step 1042, the final sample is shifted 14 bits to the left and the sample is left justified. The process is step 1042
Ends after

If the BPC value for a given channel and subband is equal to 7, the process proceeds to step 1044
To CODE variable by integer division [CODE variable ÷
5]. In step 1046, the samples of the given channel and subband set 0 are
4 is set equal to the remainder of the division performed. Step 1048 adjusts the left position of the sample by shifting left 13 bit positions. Step 1050
Now the integer division divides the CODE variable by 5 again. This quotient is stored as a new CODE variable. In step 1052, the samples of the given channel and subband set 1 are set equal to the remainder of the integer division performed in step 1050. In step 1054, the sample is 1
The sample is shifted left three bit positions, and the left position of the sample is adjusted again. In step 1056, the samples of the given channel and subband set 2 are set equal to the final value of the CODE variable. In step 1058, the final sample is shifted 13 bits to the left and left justification is performed. The process proceeds to step 105
End at 8. In step 1026, if the BPC value for a given channel and subband is equal to 10, the process proceeds to step 1060, where the integer division operation sets the CODE variable equal to [CODE variable $ 9]. In step 1062, the samples of the given channel and subband set 0 are set equal to the remainder of the division.
In step 1064, the left position of the sample is adjusted by shifting left 12 bit positions. Stage 10
At 66, the CODE variable is again divided by 9 by integer division. This quotient is stored as a new CODE variable. In step 1068, the samples of the given channel and subband set 1 are set equal to the remainder of the integer division performed in step 1066. In step 1070, the sample
The sample is shifted left by 12 bit positions, and left adjustment of the sample is performed. In step 1072, the final value of the CODE variable provides the value of the sample for the given channel and subband set 2. In step 1074, the final sample is shifted 12 bits to the left and left justification is performed. The process ends at step 1074. The samples generated by the group decoding process shown in FIG. 33 are stored in a scratch RAM associated with audio decoder block 28 until they are transferred to arithmetic unit buffer 30 as described in step 988 of FIG. You. Buffer Management Process The process used by audio decoder block 28 to perform buffer management on input buffer 24 and external buffer 26 is shown in FIGS. The process starts at step 1076, where R
The EPEAT control register is tested. The REPEAT control register indicates that there is a synchronization error and that the audio decoder block is too far ahead in the bitstream and needs to repeat certain frames to help regain synchronization. It can be set by the processor host 12 notifying the audio decoder block 28. If the REPEAT control register is set, the process proceeds from branch point B to FIG. If the REPEAT control register has not been set, then at step 1078 the REPLAY flag is examined. If the REPLAY flag is set, step 1080 Compare CNT with maximum allowed regeneration count. If REPLAY If the CNT is greater than or equal to the maximum allowed regeneration count, step 1082
In [GF SIZE + CF SIZE + BAD BIT CNT]
Are released in the input buffer 24 or the external buffer 26. In step 1084, the GF
SIZE set equal to 0, good frame pointer
(GF PTR) is set equal to 0 and BAD BI
T CNT is set equal to 0.

In step 1080, if REPLAY CNT
If is less than the maximum allowed regeneration count, the process proceeds to step 10.
From 80 go to step 1086, BAD BIT CNT is [old BAD BIT CNT + current frame size]. If at step 1078 REPLA
If the Y flag has not been set, step 1088 returns R
EPLAY Set the CNT variable equal to 0. Step 109
If 0, the SKIP flag is checked. If the SKIP flag is not set, then in step 1092 the SKIP
The CNT variable is set equal to 0. If step 109
If the SKIP flag is set at 0 or directly from step 1092, the process proceeds to step 1094, where the AUTO BUFFER The SIZE flag is checked. Stage 1
If 0994 AUTO BUFFER If the SIZE function has been enabled, the AUDIO PTR is
NF Set equal to PTR. Process is stage 10
84 and step 1086 also reach step 1096.
In step 1098, the current frame pointer is CF Set equal to PTR. The process proceeds to step 1100 with REPEAT, SKIP, REPLAY, NO READ, MUTE, and EC
Clear the flag and exit.

In step 1094, if AUTO BUFFER
If the SIZE flag is not set, step 110
MAX at 2 The REPLAY value is compared to 0. If M
AX If the REPLAY value is equal to 0, in step 1104
 GF The SIZE variable is examined. If gf SIZE is 0
If not, step 1106 proceeds to [GF SIZE + C
F SIZE + BAD BIT CNT]
Released in buffer 24 or external buffer 26
It is. The process proceeds from step 1106 to 1108, where GF
SIZE is set equal to 0 and BAD BIT CNT is
Set equal to 0. Then proceed to step 1112,
GF PTR is set equal to 0. Process is stage 1
Proceeding from step 112 to step 1096 above. Stage 110
In 4, if GF Stage 1 if SIZE is equal to 0
At 110, a number of bits equal to the size of the current frame
Is in the input buffer 24 or the external buffer 26
Released. Then, the process proceeds to step 1112. If step
MAX at floor 1102 REPLAY value not equal to 0
If it is determined that step 1114 is NO Adjust READ flag
Bell. If NO If the READ flag is set,
The process proceeds to step 1104 above. Stage 111
NO if 4 READ flag is not set
If so, step 1116 determines GF Check SIZE
You. If gf If SIZE is not equal to 0, step 11
18 is in the input buffer 24 or the external buffer 26
[GF SIZE + BAD BIT CNT]
To be released. In step 1120, BAD BIT CN
The T variable is set equal to 0. In stage 1116
Hello GF If SIZE is equal to 0, or step 11
Directly from step 20 to step 1122, where GF PTR is the current frame
GF SIZE is current
Set equal to the size of the Process is stage 1
From 122, the process proceeds to the above step 1096.

Step 1124 in FIG.
And the REPEAT flag is set equal to one. Stage
At 1126, the REPEAT control register is set equal to 0.
Is In the next step 1128, AUDIO PTR value is
Piped. In step 1130, the REPLAY flag is
Can be examined. If the REPLAY flag is set
Step 1132 is AUDIO PTR = LGF PTR + 32
Bit]. Also in step 1130
If the REPLAY flag is not set, step 11
34 is AUDIO Set PTR to [Current frame pointer + 32 bits
G). The process proceeds to step 1132
Otherwise, proceed from step 1134 to step 1136, where the SKIP
Inspect lag. If the SKIP flag is set
If step 1138 is NO Set the READ flag equal to 1
Cut. The process proceeds to step 1136 with the SKIP
If no lugs have been set, or step 1138
Directly from step 1140 to the audio buffer register.
The size of the star is checked. If the audio buffer
If the magnitude function is enabled, step 1142 is NO
Set the READ flag equal to 1. Step 1140
Enabled audio buffer size feature in
If not, or directly from step 1142 to step 11
Proceeding to 44, the audio frame is decoded. Aude
The process of decoding an audio frame is shown in FIG.
This has already been described with reference to FIGS. The process is stage 114
Go from 4 to 1146, AUDIO If the stored value of the PTR is
Will be restored. Then, the process proceeds from the connection point A to the stage of FIG.
Returned to floor 1076.General decryption operation FIG. 36 shows one example performed by the audio decoder block 28.
This shows a general decoding operation. Process audio
The decoder block 28 provides the presentation time stamp (PTS) information.
Beginning at step 1150 of processing a report. PTS data
FIG. 37 for the process used to handle
It will be described later with reference to FIG. The process proceeds from steps 1150 to 11
Proceeding to 52, the audio decoder block 28
Decode the video frame. Decode audio frames
Used by the audio decoder block 28 to
The process has been described with reference to FIGS.
is there. In step 1154, the audio decoder block
The task 28 processes auxiliary data that may be present. Auxiliary day
Figure 3 shows the process used to process the data
8 will be described later. In step 1156, the audio
Decoder block 28 performs buffer management. Bag
The processes used to perform web management
Has already been described with reference to FIGS. Stage 115
8, in the preceding HEADER register from the HEADER register
Is loaded. In step 1160, the SYNC
Decision not made whether LOOKAHEAD feature is enabled
It is. If SYNC If LOOKAHEAD is enabled,
In step 1162, the bit stream is stored in the HEADER register.
The next 32 bits in the frame are loaded. Step 1164
Now, the audio decoder will set the frame for decoding.
Up. Used to set up the frame
The process used has been described with reference to FIGS.
It is. The process proceeds from step 1164 to step 1165
The syntax flag is checked. If the syntax flag is 1
If so, the process proceeds to step 1180 described below. Also
If the syntax flag is 0, step 1166 proceeds to the next frame.
The first word of the system is input buffer 24 or external buffer
26 is determined. If the next frame
The first word of the word must be in the input buffer 24
If so, step 1168 is END OF Check STREAM flag
You. If END OF STREAM flag is not set
If so, the process returns to step 1166. If END
OF If the STREAM flag is set, step 1170
Is SYNC Clear the LOOKAHEAD flag. Then professional
The process proceeds to step 1172 where the MUTE flag is equal to 1
Set. The process then returns to step 1152.

In step 1166, if the next frame
If the first word is in the input buffer 24, the step
1174 is AUDIO PTR to NF Set equal to PTR value
To In step 1176, the
Examine the next 12 bits of
To decide. If the next 12 bits contain the sync word
If so, step 1178 is AUDIO Change PTR to [CF PTR + 3
2 bits]. If the next 12 bits are the same
If not, the process proceeds from step 1176
Proceed to step 1180, AUDIO PTR is [CF PTR +1
Bit]. In step 1181, BAD
BIT CNT is incremented by one. If SYN
C LOOKAHEAD function enabled but SYNC LO
If the OKAHEAD function fails, the process proceeds to step 1180
And step 1181. Then the process is stage 1
From 181 proceed to step 1182 to LOST SYNC interrupt
Must be set. In step 1184,
Audio decoder block 28 performs synchronization recovery.
You. Refer to FIGS. 14 and 15 for the synchronization recovery procedure.
It has already been explained. Similarly, in step 1160, if S
YNC If the LOOKAHEAD feature has not been enabled,
1186 examines the next 12 bits, which contain the sync word.
Decide whether or not to go. If the next 12 bits contain the synchronization word
If not, the process proceeds to step 1180
 AUDIO PTR is set to [current frame pointer + 1 bit].
Is set. In step 1186, if the next 12 bits
Step 1188 proceeds to the HEADER register if the
Load the next 20 bits into the register. At step 1190
Are framed as described with reference to FIGS.
The setup operation of the game is performed. To step 1191
In this, the syntax flag is checked. If the syntax flag is set
If so, the process proceeds to step 1180. So
If not, the process returns to step 1150.Presentation timestamp decoding process FIG. 37 shows the audio to process the presentation timestamp.
The process used by the video decoder block 28 is shown.
The process proceeds to step 1192 where the PTS flag is cleared.
It is disclosed from. In step 1194, the PTS PTR variable
Therefore, a value is read from the indicated address and
Time stamp audio pointer (PTS AUDIO P
TR). In step 1196, the PTS
AUDIO PTR value is checked and the most significant bit position is 1.
Whether it indicates that it is invalid
Is determined. If PTS AUDIO PTR is invalid
If so, the process ends. If PTS AUDIO PTR enabled
If so, step 1198 is the PTS AUDIO PTR
And CF Compare with PTR value. If PTS AUDIO PT
R is CF If it is larger than PTR,
Lock 28 has not yet reached PTS, and
The process ends. If PTS AUDIO PTR is CF
Audio if less than or equal to PTR
The decoder block 28 stores the data associated with the PTS.
Has been reached or has passed
At 1200, the PTS is read. In step 1202
Is the PTS associated with the audio decoder block 28
Stored in the PTS holding register in the special register
You. This PTS is the frame associated with this PTS.
PTS hold level until the program reaches PCM output block 36.
PTS stays in the
From the holding register to the PTS in the control status register block 22.
 Transferred to register. In step 1204, the PTS
Dio pointer to -1 with 1 in the most significant bit position
Set. This value is invalid and will cause the process to
It ends at 1196. In step 1206, the PTS flag
Is set equal to one. In step 1208
Is the PTS PTR is incremented by two. Process
Proceeds to step 1210, where the new PTS PTR is PTS
Is compared with the top value. If PTS PTR is still in PTS
If not, the process proceeds to step 1194
Returned directly. PTS PTR is bigger than PTS top
If PTS in step 1212 PTR is AUDIO BUFFER
Set equal to the value stored in the SIZE register
Is done. The process now proceeds from step 1212 to step 119
Return to 4.Auxiliary data processing process FIG. 38 shows auxiliary data that may be present in a bit stream.
Audio decoder block to decode and process
28 indicates the process used. The process is step 121
Starting from 4, CF SIZE is compared to 0. If C
F If SIZE is equal to 0 and the bitstream is free-form
Process, if indicated
Go to 1215, REPLAY, REPEAT, NO READ, SKIP,
And the EC flag is checked. If any of these flags
If is also not set, the automatic
The word counting function is terminated. Then step 1218 includes:
AUDIO PTR to SAVED AUDIO A variable named PTR
Keep in. In step 1220, the next synchronization word is detected.
GSYN instruction is executed until In stage 1222
ANC If the SIZE variable is [AUDIO PTR-SAVED AUD
IO PTR-12]. Next Step 12
In 24, AUDIO PTR is SAVED AUDIO Stored in PTR
Reset to the value that has been set. In step 1225, CF
SIZE is [BIT CNT + ANC SIZE]
Is done. The system is now ANC G based on the SIZE variable
Use the ET ANCILLARY statement to search for auxiliary data.
Ready.

In step 1215, if REPLAY, RE
PEAT, NO If any of the READ, SKIP, or EC flags are set, step 1217 clears these flags. In step 1219, BAD BIT CNT is BIT
Only the CNT is incremented. In step 1221, the BI
T CNT is set equal to 0. The process then proceeds to step 1223, where the synchronization recovery process described with reference to FIGS. 14 and 15 is performed. In step 1214, if CF If SIZE is not equal to 0, step 1226
Is NO Examine the READ, REPLAY, REPEAT, SKIP, and EC flags. If any of these flags are set, the process ends. If none of these flags are set, then at step 1228 the auxiliary data and auxiliary overflow interrupt are examined. If neither of these has been enabled, the process ends. Step 1 if any interrupts are enabled
At 230, the bit count is CF Compared to SIZE. If the bit count is CF If it is, the process ends. If the bit count is CF If less than or equal to SIZE, A in step 1232
NC If the SIZE variable is [NF PTR- AUDIO PTR]. In step 1234, GET ANCILLARY (G
ANC) using data instructions Retrieve ancillary data from the bitstream based on the SIZE variable. Stage 1
234 is also reached from step 1225 above. In the next step 1236, the auxiliary interrupt is examined. If the auxiliary interrupt has been enabled, then at step 1238 the auxiliary interrupt is set.

The processing of the auxiliary data is controlled by the contents of the auxiliary registers and the auxiliary available registers and the interrupts 6 and 7. If interrupt 6 or 7 is enabled, the incoming auxiliary data is inserted into the auxiliary register.
As described above, the auxiliary register functions as a FIFO that holds at least 32 bits of auxiliary data. If interrupt 7 is masked, the oldest data is replaced bit by bit with new data. If interrupt 7 is enabled, system 1 will be
4 generates an interrupt. If an interrupt is generated, further processing of the audio data is halted until the microprocessor host 12 reads the data or the interrupt is masked. The auxiliary available register always holds the number of available bits in the auxiliary register. An interrupt 6 is generated when 16 or 32 bits of auxiliary data are available in the auxiliary register, or when the end of the frame is reached. Prior to reading the auxiliary example, microprocessor host 12 reads the auxiliary enable register to determine the number of valid auxiliary data bits available. When the microprocessor host 12 reads the auxiliary available register, the contents of the auxiliary register are transferred to a temporary register. The microprocessor host 12 can read auxiliary data from the temporary register by accessing the auxiliary register address. Thus, the microprocessor host 12 can use the auxiliary data without conflicting with any of the additional auxiliary data that can be loaded into the auxiliary registers during the read process.

The following items are disclosed in connection with the above description.
I do. 1. A microprocessor host circuit and the microprocessor
Encoded data coupled to the processor host circuit
And the code selected from the encoded data
Operable to extract encrypted audio data
Yes, and the selected encoded audio data
Data and outputs the decoded audio data.
Integrated audio decoder system operable
System and the integrated audio decoder system
And decodes the decoded audio data
Digital analog operable to convert to analog signals
A data converter comprising:
Place. 2. The integrated audio decoder system comprises:
Connect the integrated audio decoder system to the
Operable to couple to microprocessor host circuit
A host interface circuit and the host interface
Receiving the encoded data,
The encoded audio is converted from the encoded data.
Audio data, and encode the encoded audio
System decoder circuit operable to output data
And the encoded signal coupled to the system decoder.
Receive, store and output the audio data
An input buffer circuit operable to
Connected to the input buffer circuit.
Search the encoded audio data, and
Audio data, and decode the decoded audio data.
Audio deco operable to output audio data
And the audio decoder and the audio decoder.
Receiving and storing the decoded audio data, and
Arithmetic unit buffer circuit operable to output
And the operation unit buffer circuit,
From the arithmetic unit buffer circuit
Search the data and quantify the decoded audio data
De-destroyed, transformed, and filtered, and filtered
Arithmetic unit operable to output audio data
And a filtering circuit coupled to the arithmetic unit circuit and the filtering unit.
Receives, stores, and outputs the waved audio data.
An output buffer circuit operable to output
Connected to the buffer circuit and the digital / analog converter
And the filtered data from the output buffer circuit.
And retrieves the filtered data from the digital
An output circuit operable to output to an analog converter;
2. The data processing device according to claim 1, comprising: 3. The host interface circuit and the system
Coder circuit, input buffer circuit, audio data
Coder circuit, operation buffer circuit, operation unit
Circuit, the output buffer circuit, and the output circuit are all
2 above, which is located on a single semiconductor substrate
A data processing device according to the item. 4. The audio decoder block is
The programmed circuit and the audio decoder circuit are
Stores microcode routines that define actions to be performed
And a microprogram memory operable to
3. The data processing apparatus according to claim 2, wherein 5. The arithmetic unit is adapted to decode the decoded audio
De-quantize, transform, and filter the data sequentially
Operate to form the filtered audio data
3. A method according to claim 2 comprising a possible state machine drive circuit.
Data processing device. 6. The system decoder circuit and the audio deco
Additional encoded audio coupled to the
Operates to receive, store, and output data
It also has an external buffer circuit that can
The decoder circuit and the audio decoder circuit are connected to the external buffer.
Operable to detect the presence of a
If the external buffer circuit is present, additional encoding is performed.
External buffer for storing audio data
Item 3. The data processing device according to the above item 2 using a circuit. 7. The system decoder circuit, the input buffer circuit
And the audio decoder circuit is a first semiconductor circuit.
The external buffer circuit is placed on the
6. The above item 6, which is arranged on the semiconductor substrate 2
A data processing device according to claim 1. 8. The arithmetic unit circuit includes the output buffer circuit.
Pulse-code modulated data for storage in the
Operable to generate and output
・ The analog converter circuit operates the pulse code modulated data
Data, and analyzes the pulse code modulated data.
Note 2 above that is operable to convert to a log signal.
On-board data processing device. 9. The integrated audio decoder system comprises:
The microprocessor host circuit and the audio
Multiple control and status registers accessible by the decoder circuit
3. The data processing device according to claim 2, further comprising a star. 10. The microprocessor host circuit includes a serial code
Receiving the encoded bit stream and performing the serial encoding
The information contained in the extracted bit stream into multiple parallel
Through the signal line to the above audio decoder system
Operable to output the audio
The coded system is coded through the parallel signal lines.
Item 1 operable to receive the received data
The data processing device according to claim 1. 11. The audio decoder system comprises:
Serially encoded bits to the audio decoder system
Receive the encoded data through the stream input
2. The data processing device according to claim 1, operable to
Place. 12. Receive an external signal containing encoded data
Host interface circuit operable as
And is coded as described above.
Receiving the data and encoding from the encoded data
Extracted audio data, and encoded
System that can operate to output
System decoder circuit and the system decoder circuit.
Receiving the encoded audio data,
Input buffer times that are operable to remember and output
And an output buffer circuit coupled to the output buffer circuit.
Search the encoded audio data from the hardware circuit
And decodes the encoded audio data.
Operable to output decoded audio data
Audio decoder circuit and the audio decoder
And receive the decoded audio data
Arithmetic unit operable to store, store, and output
Unit buffer circuit and the arithmetic unit buffer circuit.
Combined and decoded from the arithmetic unit buffer circuit
Search for the decoded audio data, and
Dequantizes, transforms, and filters the Dio data,
And act to output the filtered audio data.
Compatible operation unit circuits and the above operation unit circuits
Receiving the filtered audio data,
Output buffer operable to store and output
And the output buffer circuit coupled to the output buffer circuit.
Search the filtered audio data from the buffer circuit
And operable to output the filtered data.
Audio decoding, comprising: an output circuit.
apparatus. 13. The host interface circuit and the system
Decoder circuit, input buffer circuit, audio
Decoder circuit, operation buffer circuit, operation unit
Circuit, the output buffer circuit, and the output circuit
Above which is located on a single semiconductor substrate
Item 13. The audio decoding device according to Item 12. 14． The audio decoder circuit is a microprocessor
And the audio decoder circuit described above.
Stores microcode routines that define actions to take
And a microprogram memory operable to
Item 13. The audio decoding device according to Item 12, wherein 15. The arithmetic unit is adapted to decode the decoded audio.
Sequentially dequantizes, transforms, and filters the data
To form the filtered audio data
Item 12.
Audio decoding device. 16. The system decoder circuit and the audio decoder
Additional encoded audio coupled to the coder circuit
To receive, store, and output video data.
It also has an external buffer circuit that can be
The decoder circuit and the audio decoder circuit are connected to the external bus.
Operable to detect the presence of a buffer circuit.
If the external buffer circuit is present, additional coding
External buffer to store audio data
Item 13. The audio decoding device according to Item 12, wherein the audio decoding device uses
Place. 17． The system decoder circuit, the input buffer
Circuit, and the audio decoder circuit is a first semiconductor
Placed on the substrate and the external buffer circuit
The above-mentioned 1 which is arranged on a second semiconductor substrate.
Item 7. The audio decoding device according to Item 6. 18. The arithmetic unit circuit includes the output buffer circuit
Pulse code modulated data for storage in the road
Operable to form and output
The decoding system is a digital decoding system coupled to the output circuit.
Digital-to-analog converter circuit.
The analog converter circuit converts the pulse code modulated data.
Data that has been pulse-code modulated
Clause 12, which is operable to convert the
Audio decoding device. 19. Microprocessor host circuit and audio
Multiple controls and states accessible by the audio decoder circuit
3. The audio decoder according to claim 2, further comprising a register.
No. device. 20. The audio decoding system comprises:
Serially encoded bitstream to interface circuit
Receive the encoded data through the
Item 13. The audio decoding device according to Item 12, which is operable
Place. 21. Coupled to the above host interface circuit,
Receives the column-encoded bit stream and returns the serial code
Information contained in the encoded bit stream
The host interface circuit through a parallel signal line
Microprocessor host operable to output to
A plurality of host interface circuits.
Receive the encoded data through the parallel signal lines
13. The audio of claim 12, operable to communicate
Audio decoding device. 22. A method for decoding encoded data, comprising:
Receiving an external signal containing the encoded data;
Audio data encoded from encoded data
Extracting in the system decoder circuit;
Audio decoder circuit for encoded audio data
Within and generate the decoded audio data
And processing the decoded audio data into an arithmetic unit.
Dequantized in the
Generating audio data and dequantizing audio
The audio data is converted in the arithmetic unit circuit and converted.
Generating converted audio data; and
Filtered audio data in the arithmetic unit circuit
Filtering and forming filtered audio data;
Outputting the waved audio data.
A method comprising: 23. System decoder circuit, audio decoder circuit
Circuits and arithmetic unit circuits are all a single semiconductor substrate.
23. The method according to claim 22, wherein the method is arranged on a rate. 24. Digitally filter the filtered audio data.
A stage for converting to an analog signal in a analog converter circuit
23. The method of claim 22, further comprising a floor. 25. The above to decode the encoded audio data
The step is to encode the encoded audio data
Performed by programmed circuit and audio decoder circuit
Stores microcode routines that define actions to take
Operable with microprogram memory
Decoding in the audio decoder circuit
23. The method of claim 22, wherein 26. The steps of dequantization, transformation, and filtering are as follows:
Arithmetic unit with circuit driven by state machine
Dequantize, transform, and filter using circuitry
23. The method of claim 22 comprising the steps. 27. Input buffer for encoded audio data
Storing in the circuit and the decoded audio data
Storing in the arithmetic unit buffer circuit;
Stored in the output buffer circuit.
23. The method of claim 22, further comprising the step of: 28. A search is made from a storage device in the first buffer circuit.
Process the encoded bit stream
Data processing device that outputs data to the second buffer circuit.
Operable to perform arithmetic and logical operations
An arithmetic logic unit and the arithmetic logic unit
Operate to instruct the execution of the above operations and logical operations
Possible execution control state machine and coded bitstream
Microcontroller that the system can execute to process the
An instruction memory for storing a sequence of code instructions.
The instruction memory includes the arithmetic logic unit and the
Execution control
To retrieve data from the first buffer circuit.
Decodes the scaled data, and
To output the sampled information to the second buffer circuit.
Stores the set of microcode instructions operable
A data processing device characterized in that: 29. Frame of data being processed by the above data processing device
Format that stores information indicating the format of the
The instruction memory also has an encoded data.
Processing associated with processing data in different formats
Routine storage, the data processing device is formatted
In the instruction memory in response to the data identifying
Associated with the indicated format remembered
29. Selecting and executing an appropriate routine
Data processing device. 30. The above data frame uses the MPEG standard syntax.
Audio data encoded at a predetermined bit rate
The format register is used for data processing.
The device encodes the frame of audio data being processed
Record data identifying the bit rate used to
29. The data according to above item 29, which is operable to remember.
Processing equipment. 31. The above data frame is related to the MPEG standard syntax.
Audio encoded using a specific layer associated
The format register contains the data
The audio data frame being processed by the
Data identifying the particular layer used to encode
And the instruction memory is operable to store
Processing associated with the processing of the different layers of the encrypted data
Process routines and the above data processing identifies a specific layer
Stored in the instruction memory in response to the data
The appropriate routine associated with the indicated layer
30. The data processing device according to the above item 29, wherein the data processing device selects and executes. 32. A frame of the above data is encoded audio
The instruction memory contains the data currently being processed.
Data processing unit determines that the frame contains an error
If not, the data other than the frame currently being processed
The data processing device can be selected to output
Operable to memorize executable error concealment routines
29. The data processing device according to the above item 28, which is a function. 33. The data processing device may include the error concealment routine.
Valid data frame used in the first buffer
First bank to determine if it can be stored
Operable to determine the size of the buffer
The data processing device responds to the size of the first buffer.
If the determined size of the first buffer is
If the data frame can be stored, the data processing device processes it.
In addition to storing the current frame, storing the valid data frame
Select and execute a specific error concealment routine that also requires
33. The data processing apparatus according to the above item 32, wherein 34. One of the error concealment routines is a data processing device.
Indicates that the frame currently being processed contains an error.
If found, the data processing unit
Last processed valid frame instead of middle frame
The data according to the above item 33 to be output to a data processing device
Processing equipment. 35. One of the error concealment routines is a silenced audio
Output the data corresponding to the audio output to the data processor.
33. The data processing device according to the above item 32, wherein 36. One of the error concealment routines is audio
Data frame is discarded by the data processor and
Above to start processing a new frame of audio data
Item 32. The data processing device according to Item 32. 37. Frames of the above data can be divided into subbands
Command data consisting of various encoded audio data.
Mori is data processing device selectable and executable
Operable to store a processing routine;
The processing routine defines a predetermined relationship associated with each subband.
Access to the numbers and the predetermined coefficients and the audio data
Data frame and combine them for each subband.
The associated volume can be independently determined using the predetermined coefficient
Subbands are scaled by a predetermined factor so that they can be adjusted
Output the processed data to the second buffer
Item 29. The data processing device according to item 28. 38. The above data frame is divided into stereo channels.
Consisting of splittable encoded audio data,
Instruction memory is data processor selectable and executable
Operable to store a possible processing routine;
The above processing routine is associated with each stereo channel.
Access to the specified coefficient, and
Combine with frames of audio data and
The volume associated with the teleo channel is
The above stereo channel can be adjusted independently using
The data obtained by reducing the size of the
29. The data processing device according to the above item 28, which outputs the data to a buffer.
Place. 39. At least one of the microcode instructions is:
A predetermined number of data from the first buffer is sent to the data processing device.
Consisting of an instruction operable to cause a bit to be retrieved
Item 29. The data processing device according to item 28. 40. At least one of the microcode instructions is:
A predetermined number of data from the first buffer is sent to the data processing device.
Causes the bit to be searched and associated with the searched bit
Is the instruction operable to calculate the cyclic redundancy code value?
29. The data processing device according to the above item 28, comprising: 41. At least one of the above microcode instructions is the same
And the synchronization command is transmitted to the data processing device.
1 to retrieve data bits from the
The first buffer is executed by the processor executing the synchronization instruction.
Synchronization within the bit sequence stored in the buffer.
The retrieved bits are set to a predetermined bit
2 above, which is operable to search for turns
Item 9. The data processing device according to Item 8. 42. An auxiliary data register is also provided.
At least one of the load instructions is transmitted to the data processing device by the first
A predetermined number of auxiliary data bits of data from the
And searches the auxiliary data bit for the auxiliary data register.
From an auxiliary data instruction operable to be stored in the
29. The data processing device according to the above item 28. 43. The data processing device is provided in the auxiliary data register.
Select information that indicates that auxiliary data exists
42. The apparatus as in claim 42, wherein the apparatus is operable to output as much as possible.
Data processing equipment. 44. The data processing device is provided in the auxiliary data register.
Overlay auxiliary data stored in
Before writing, audio data processing can be stopped selectively.
43. The data of claim 42 operable to shut down.
Data processing device. 45. A search is made from a storage device in the first buffer circuit.
Process the encoded audio bitstream,
Data to output the processed data to the second buffer circuit.
A processor for performing arithmetic and logical operations.
The operation logic unit that can operate
To perform the above operations and logical operations.
Control state machine operable as
Run by the data processor to process the stream
Instructions that store sequences of possible microcode instructions
And an instruction memory, wherein the instruction memory includes the arithmetic logic unit.
The system including the unit and the execution control state machine execute
Frame of data from the first buffer circuit
Search, decrypt the retrieved data, and scale
The coefficient information and the encoded sample information are stored in a second buffer.
Microcontroller operable to output to the
The data processing device further stores a set of
Layers of audio data frames being processed by the processing unit
For storing information indicating the sampling rate and sampling rate.
A mat register is also provided, and the instruction memory is coded.
Processing rules associated with the processing of different layers of
And the data processing device stores the data to identify the layer.
Command stored in the instruction memory in response to the
Select and execute the appropriate routine associated with the layer
And the instruction memory is selectable by the data processing device;
And act to remember executable error concealment routines.
The error concealment routine can be
The device detects that the frame currently being processed contains an error.
If the data processing unit is determined, the data processing unit
Output data other than the frame currently being processed, and process the data
The device is used for the audio used in the error concealment routine
Storing a valid frame of data in the first buffer;
Size of the first buffer to determine if
A data processing device operable to determine the magnitude;
Responds to the size of the first buffer,
The determined size of the key is stored in the valid data frame.
If possible, record the frame being processed by the data processor.
Identification that requires storage of valid data frames in addition to memory
Selecting and executing the error concealment routine
Data processing device. 46. The data processor can adapt to variable length frames
Audio for each frame in order to hide errors
Before processing the data, the above determined
Operable to compare size to size of each frame
46. The data processing device according to the above item 45, which is a function. 47. One of the error concealment routines is a data processing device.
Indicates that the frame currently being processed contains an error.
If found, the data processing unit
Last processed valid frame instead of middle frame
Item 45. The data described in the above item 45 to be output to a data processing device
Processing equipment. 48. One of the error concealment routines is a silenced audio
Output the data corresponding to the audio output to the data processor.
48. The data processing device according to the above item 47, wherein 49. The above data frame is divided into stereo channels.
Consisting of splittable encoded audio data,
The instruction memory is data processing device selectable and
Operable to store executable processing routines.
The above processing routine is associated with each stereo channel.
Access to the predetermined coefficient,
Combining the audio data with the frame, and
Set the volume associated with each stereo channel to the
The above stereo so that it can be adjusted independently using the coefficients
The data obtained by scaling the channel by the predetermined coefficient
45. The data processing according to the above item 45 for outputting to the buffer 2
Equipment. 50. The above microcode instructions are sent to the data processing device.
A predetermined number of bits of data are retrieved from the first buffer.
And instructs the data processing device to pre-determine data from the first buffer.
Search for a number of bits
The calculated cyclic redundancy code value is calculated and the data processing device
One bit of data is retrieved from one buffer and
The data processing device executes the synchronization instruction to perform the first
Synchronized within the bit sequence stored in the buffer
So that the retrieved bits can be
Different lives operable to make you search for patterns
46. The data processing device according to the above item 45, which comprises an order. 51. An auxiliary data register is also provided.
At least one of the load instructions is transmitted to the data processing device by the first
A predetermined number of auxiliary data bits of data from the
And searches the auxiliary data bit for the auxiliary data register.
From an auxiliary data instruction operable to be stored in the
45. The data processing device according to the above item 45. 52. Code stored in the first data buffer
Process the encoded audio data and process the processed data
In a second data buffer,
Perform arithmetic and logical operations within the arithmetic and logic unit
And execution control coupled to the arithmetic logic unit
A stage for instructing the execution of arithmetic and logical operations using a state machine
Floor and to process the encoded bit stream
The device commands a sequence of executable microcode instructions.
Storage in the command memory and the encoded audio
Retrieving data from the first buffer circuit;
The coefficient information and the encoded sample information are stored in a second buffer.
Output to the audio circuit and the audio data being processed by the device.
Indicates the layer of the data frame and the sampling rate
Storing the information in a format register;
Different tiers associated with the processing of different layers of
Storing the processing routines and storing them in the instruction memory.
The appropriate route associated with the indicated indicated layer
Select and execute a program, and use it for error concealment routines
The effective frame of the audio data to be
To determine if it can be stored in the
Determining the size of one buffer, and
If the frame is determined to contain an error
Error in outputting data other than the frame currently being processed.
Selecting and executing a hidden routine.
The step of selecting and executing the error concealment routine comprises the following steps:
Responds to the size of the buffer and
Certain errors that also require the storage of valid data frames
Select and execute a hidden routine
Law. 53. Selecting and executing the error concealment routine
Found that the frame currently being processed contains errors
If so, process last instead of the frame currently being processed
52. The method according to claim 52, further comprising the step of outputting the effective frame.
The method described in. 54. Selecting and executing the error concealment routine
Outputs data corresponding to the silenced audio output.
53. The method according to the above item 52, comprising the step of causing the step of causing the reaction to occur. 55. The encoded buffer retrieved from the first buffer circuit
Decodes the filtered data, filters it, and processes the processed data.
A data processing device for outputting to the second buffer circuit;
The encoded data stored in the first buffer.
Sample data encoded from within the first block of data
A circuit for retrieving data and scale coefficient information;
Dequantize and dequantize the sample data using
A circuit that forms the sampled data
A circuit for storing sampled data, and a dequantized
Transform the sample data using the fast cosine process,
A circuit for forming the converted sample data;
A circuit for storing the dequantized sample data,
A block of data processed before the first block
Using the pulse code modulated data associated with
Filter the transformed dequantized sample data
A circuit for oscillating and forming pulse code modulated data;
A second buffer circuit for transmitting the pulse code modulated data to a second buffer circuit;
And a circuit for outputting the data to a data processor.
Equipment. 56. The above dequantization circuit, conversion circuit, and filtering circuit
Is a mathematical unit circuit with an addition circuit and a multiplication circuit.
56. The data processing device according to the above item 55, which is configured. 57. The mathematical unit circuit comprises first, second, and
3 through the math unit circuit
Form the product of the first and second operands in a single pass
And form the sum of the product and the third operand
56. The data processing device according to the above item 56, which is configured. 58. The multiplication circuit includes a booth encoder circuit and
A plurality of partial products coupled to the Booth encoder circuit
Item 56. The data according to Item 56, further comprising a generator circuit.
Data processing device. 59. The filtering circuit comprises a number of multiplications and a stored coefficient.
Are higher than those associated with matrix multiplication
Use the butterfly operator to reduce
56. A data processing apparatus according to the above item 55, comprising a circuit for performing conversion.
Equipment. 60. The filtering circuit is a coefficient circuit that stores a filtering coefficient.
And a circuit for accessing the coefficient circuit.
56. The data processing device according to the above item 55. 61. The filtering circuit requires multiple filtering coefficients
It consists of a circuit that performs a linear transformation,
At least two separations performed during the filtering of the block
So that the same coefficient is used for each
55. The data processor of clause 55 wherein the number filtering coefficients are symmetric.
Equipment. 62. Accessible by the above dequantization circuit and conversion circuit
Also has a read-only memory table for storing the effective coefficients
56. The data processing device according to the above item 55, wherein 63. A first buffer, a second buffer, and
Data processing to access the read-only memory table.
Address generator that generates addresses used by the
63. The data processing according to the above item 62, further comprising a data circuit.
apparatus. 64. The encoded data is a sub-band sampler.
Data, scale factor information, and each subband sample
Quantization associated with the number of bits associated
The audio data consists of information used for
Encoded above associated with the bit stream of the
Data is encoded using the MPEG standard syntax.
56. The data processing device according to the above item 55, wherein 65. The encoded buffer retrieved from the first buffer circuit
The decoded data is decoded and filtered, and the processed data is
A data processing device for outputting to a first buffer.
The first block of encoded data stored in the file
Sample data and scale factor encoded from within the lock
A circuit for retrieving information and sampling using scale factor information
De-quantizes the sample data, and de-quantizes the sample data.
Math unit circuit to form the data
A circuit for storing sample data;
The unit circuit converts the dequantized sample data to high
Transformed using the fast cosine process and the transformed sample
It is also operable to form data and converted
A circuit for storing the dequantized sample data is also provided.
Wherein the math unit circuit is provided in the first block.
Pal associated with a previously processed block of data
Using the code-modulated data
De-decoded sample data is filtered and pulse code modulated
Is also operable to form the
Readout storing coefficients accessible by the math unit circuit
Dedicated memory table and the pulse code modulated data
A circuit for outputting data to the second buffer circuit;
Buffer, a second buffer, and the read-only memory
Used by data processing equipment to access cables
Also equipped with an address generator circuit to generate addresses
A data processing device characterized in that: 66. The above mathematical unit circuit includes a multiplication circuit and an addition circuit.
Wherein the mathematical unit circuit comprises first, second, and
Receiving the third operand and passing through the math unit circuit
The product of the first and second operands in a single pass
And sum the product and the third operand
65. The data processing device according to the above 65, which is formed. 67. The multiplication circuit includes a booth encoder circuit and
A plurality of partial products coupled to the Booth encoder circuit
67. The data according to the above item 66, comprising a generator circuit.
Data processing device. 68. The encoded data is a sub-band sampler.
Data, scale factor information, and each subband sample
From information associated with the number of bits associated
Associated with the audio data bit stream.
The above encoded data uses the MPEG standard syntax
67. The data processing device according to item 66, wherein
Place. 69. The encoded buffer retrieved from the first buffer circuit
Decodes the filtered data, filters it, and processes the processed data.
A method for outputting to a second buffer circuit, comprising:
The first of the encoded data stored in the buffer
Sample data and scaler encoded from within the block
Searching for numerical information and using the scale factor information
Dequantizes the pull data and dequantizes the sample
Forming data and dequantized sample data
Data storage and dequantized sample data.
Data using a fast cosine process and the converted
Forming sample data and transformed dequantization
Storing the obtained sample data;
Associated with a block of data processed before the lock
The above conversion using the pulse code modulated data
The filtered dequantized sample data is filtered and pulsed.
Forming code modulated data; and
For outputting signal-modulated data to a second buffer circuit
And a floor. 70. The dequantization step, the transformation step, and the filtering step
Is a mathematical unit circuit with an addition circuit and a multiplication circuit.
70. The method according to claim 69, wherein the method is performed using. 71. The dequantization step comprises the mathematical unit circuit
Receiving the first, second, and third operands at
Steps and a single pass through the math unit circuit above
Forming the product of the first and second operands, and
Forming a sum of the product and the third operand.
71. The method of claim 70, wherein the method comprises: 72. During the dequantization and conversion steps, the read
A step of retrieving coefficients from the memory table for
70. The method of claim 69, wherein 73. First buffer, second buffer, and read
Generates the address for accessing the dedicated memory table.
70. The method of claim 69, further comprising the step of: 74. The encoded data is a sub-band sampler.
Data, scale factor information, and each subband sample
From information associated with the number of bits associated
Associated with the audio data bit stream.
The above encoded data uses the MPEG standard syntax
70. The method according to the above clause 69, which is encoded as follows. 75. Data processing for receiving and processing bit sequences
The received bit sequence data.
Receive the bits, each of the received bit sequence
Store as multiple words consisting of multiple data bits
A first-in first-out (FIFO) register operable to
Coupled to the FIFO circuit for receiving the word and receiving the word;
Operable to output the bits in the transmitted word serially
A shifter circuit, and the bit shifter coupled to the shifter circuit.
A predetermined bit pattern encoded in the can is detected.
Operable to output and within a bit sequence.
Output in parallel the group of selected bits detected by
And a shifter circuit as described above
And the detector circuit, and the shifter circuit and the
Control theory operable to direct the operation of the detector circuit
A logic circuit and the detector circuit coupled to the detector circuit.
To receive the selected group of bits output by
Operable buffer interface circuit
A data processing device characterized by the above-mentioned. 76. Coupled to the shifter circuit and the control logic circuit.
Operable to store the digit feed count;
Also, the shifter circuit serially supplies bits to the detector circuit.
When output, it also works to change the digit feed count value.
The above 75 which also has a possible feed counter circuit
The data processing device according to claim 1. 77. The control logic circuit increases the predetermined digit feed count value.
Operable to load the marked feed counter circuit.
Yes, the digit feed counter circuit detects each bit as described above.
The output digit is decremented when output to the circuit.
Operable to control the
The logic circuit determines the specific bits to be loaded into the detector circuit.
The length of the sequence is calculated using the predetermined digit
78. The data processing device according to the above item 76, which can be designated by specifying. 78. The bit sequence received by the data processing device is
Bit sequence encoded using MPEG standard syntax
The control logic circuit is received by the data processing device.
Receives information indicating the coding layer of the current bit sequence.
75. A data processor according to claim 75 operable to communicate.
Equipment. 79. The control logic circuit and the detector circuit are
Start of a packet of encoded data in the
Operable to detect a start code that indicates
75. The data processing device according to the above 75, wherein 80. The above bit sequence is divided into bit packets.
Divided into each other to form a bit sequence
Time division with several different bitstreams divided
Form a serial bit stream and the control logic is
Indicates which of a number of bitstreams to decode
Operable to receive information, the control logic circuit comprising:
Path and the detector circuit convert the indicated bit stream.
Whether the constituent packet is a time-division serial bit stream
7 operable to detect and retrieve from
6. The data processing device according to 5. 81. The control logic circuit and the detector circuit are
To detect the presentation timestamp in the default sequence
75. The data processing device as recited in claim 75, operable. 82. The control logic circuit and the detector circuit are
Of the part of the bit stream to be decoded in the
Detect end-of-stream code indicating end
And the device is coupled to the detector circuit.
A temporary bit storage circuit,
The storage circuit is activated by one of the end of the stream code.
Incomplete groups interrupted from the bitstream
Received and the remainder of the group of incomplete bits
The incomplete bit glue found from the sequence
Operable to remember until it can be connected to
75. The data processing apparatus according to the above 75, wherein 83. Coupled to the control logic circuit and the detector circuit
Indicates the end of the part of the bitstream to be decoded.
End of a stream operable to receive the information
And the decoding circuit coupled to the detector circuit and the detector circuit.
Information indicating the end of the part of the bitstream to be
Bitstreams for incomplete groups interrupted by
The remaining bits of the incomplete group of bits received from the
Is searched from the bit sequence to find the above incomplete bits.
Remember until you can connect to a group
The above 75 which also comprises an operable temporary bit storage circuit.
A data processing device according to claim 1. 84. Coupled to the buffer interface circuit,
Stores bits received from buffer interface circuit
A buffer circuit operable to perform
Video output from the interface circuit to the buffer circuit
Indicates where the data is stored in the buffer circuit.
A first address operable to generate a first address value
75, further comprising an address counter circuit of
Data processing equipment. 85. The above bit sequence is a presentation time stamp
The control logic circuit and the detector circuit
Part of the bit sequence retrieved from the bit sequence
Check the above indicated time stamp code associated with the minute.
Operable to emit, and the data processing device further comprises:
From the buffer interface circuit to the buffer circuit
The detected and searched presentation time stamp
Indicates where the code is stored in the buffer circuit.
To generate a presentation timestamp address value
It also has a configurable presentation timestamp address circuit.
85. The data processing apparatus according to 84, wherein 86. A complete MPEG syntax multiplex system stream,
A stream consisting of MPEG syntax audio packets,
And uncompressed pulse code modulated audio
Selected from a group consisting of a stream of data
Bits encoded using any of the given encoding syntaxes
Operable to identify and process sequences
75. The data processing device according to item 75. 87. A complete MPEG syntax multiplex system stream,
A stream consisting of MPEG syntax audio packets,
A stream consisting of MPEG syntax audio frames,
And uncompressed pulse code modulated audio
A possible bit sea consisting of a stream of data
At least two bit sequences of a group of sequence
75, operable to identify and process an instance.
A data processing device according to claim 1. 88. Bits encoded using the MPEG standard syntax
Data processing device that receives and processes
To receive the data bits of the received bit sequence.
And each of a plurality of data of the received bit sequence
Operable to store as multiple words of bits
First-in-first-out (FIFO) register and the FIFO
Coupled to a circuit, receiving the word and receiving
Shifter circuit operable to output bits in series
Is connected to the shifter circuit and is output from the shifter circuit.
Operable to receive the input bit sequence.
Is present and is encoded in the bit sequence
It can also operate to detect the bit pattern of
Also selected bits detected in the bit sequence
Detector that can also operate to output multiple groups in parallel
A circuit coupled to the shifter circuit and the detector circuit.
Indicating the operation of the shifter circuit and the detector circuit.
Control logic circuit operable to
Selected bits combined and output by the detector circuit
Buffer interface operable to receive a group of
The face circuit, the shifter circuit, and the control logic circuit
Combined and operable to store the digit feed count.
And the shifter circuit sends a bit to the detector circuit.
When serially output, the above digit count value is decremented.
Operable so that the control logic circuit
The specific bit sequence that should be loaded into the detector circuit
The length of the sense can be specified using the above-mentioned feed count value.
And a feed counter circuit,
The logic circuit determines the bit sequence that the data processing device is receiving.
Operates to receive information indicating the coding layer of the cans
It is possible that the control logic circuit and the detector circuit comprise:
Of a packet of encoded data in a bit sequence
Operable to detect start code indicating start
And the control logic circuit and the detector circuit are
To detect the presentation timestamp in the default sequence
A data processing device, wherein the data processing device is also operable. 89. The above bit sequence is divided into bit packets.
Divided into each other to form a bit sequence
Time division with several different bitstreams divided
Form a serial bit stream and the control logic is
Indicates which of a number of bitstreams to decode
Operable to receive information, the control logic circuit comprising:
Path and the detector circuit convert the indicated bit stream.
Whether the constituent packet is a time-division serial bit stream
8 operable to detect and retrieve from
9. The data processing device according to 8. 90. The control logic circuit and the detector circuit are
Of the part of the bit stream to be decoded in the
Detect end-of-stream code indicating end
And the device is coupled to the detector circuit.
A temporary bit storage circuit,
The storage circuit is activated by one of the end of the stream code.
Incomplete groups interrupted from the bitstream
Received and the remainder of the group of incomplete bits
The incomplete bit glue found from the sequence
Operable to remember until it can be connected to
88. The data processing apparatus according to the above 88, wherein 91. Coupled to the buffer interface circuit,
Stores bits received from buffer interface circuit
A buffer circuit operable to perform
Video output from the interface circuit to the buffer circuit
Indicates where the data is stored in the buffer circuit.
A first address operable to generate a first address value
88, further comprising an address counter circuit of
Data processing equipment. 92. The above bit sequence is a presentation time stamp
The control logic circuit and the detector circuit
Part of the bit sequence retrieved from the bit sequence
Check the above indicated time stamp code associated with the minute.
Operable to dispense, wherein the device further comprises
Output from the buffer interface circuit to the buffer circuit.
The detected and searched presentation time stamp code is
A presentation tag that indicates where in the buffer circuit to store
Operable to generate the timestamp address value
84, which also includes a time stamp address circuit.
A data processing device according to claim 1. 93. A method of receiving and processing a bit sequence.
Receive the data bits of the received bit sequence.
Multiple bits of the received bit sequence.
First-in, first-out (FIF)
O) storing in a register;
Receiving the above words in a shifter circuit coupled to the
Outputs the bits in the word received from the shifter circuit in series
And coupling from the shifter circuit to the shifter circuit
Receive the bits output to the detector circuit
A given bit encoded in the bit sequence
Pattern, and detected in the bit sequence.
Outputting selected groups of selected bits in parallel
Connected to the shifter circuit and the detector circuit.
The shifter circuit and the detection using the control logic circuit
Instructing the operation of the detector circuit;
Receive the selected group of bits, and
In the buffer interface circuit coupled to the circuit
Storing. 94. Coupled to the shifter circuit and control logic circuit
Stores the feed count value in the feed feed counter circuit.
And the shifter circuit outputs bits to the detector circuit in series
As described in 93 above, including the step of changing the melt feed count.
The method described. 95. Predetermined digit feed count in the digit feed counter circuit
Store the value and each bit is output serially to the detector circuit.
When it is decremented, the digit feed count is decremented,
The specific bit sequence to be loaded into the above detector circuit
Specify the length of the distance using the above-mentioned specified digit feed count.
93. The method of claim 93, further comprising the step of enabling
Method. 96. The received bit sequence is an MPEG standard structure.
Consisting of a bit sequence encoded using a sentence,
Indicate the encoded layer of the received bit sequence
93, further comprising the step of receiving
Method. 97. Indicates the start of a packet of encoded data
The start code and presentation timestamp
93. The method of claim 93, further comprising the step of detecting
Method. 98. The above bit sequence is divided into bit packets.
Divided into each other to form a bit sequence
Time division with several different bitstreams divided
Construct a serial bit stream and the method further comprises:
Information indicating which bit stream to decode
Receiving the information and configuring the indicated bit stream.
The resulting packet from a time-shared serial bit stream.
93, further comprising the steps of detecting and searching.
The described method. 99. The bit stream to decode in the bit sequence
End-of-stream code indicating the end of the
At the end of the stream code.
Bit-strapped incomplete groups interrupted by one
Received from the stream and the remaining
The remainder is retrieved from the bit sequence and
Until it can be linked to a group of detectors.
Stage in a temporary bit storage circuit coupled to the path
94. The method as in claim 93, further comprising a floor. 100. My connected to the decryption system (14)
Data processing device including cross-processor host (12)
(10) is disclosed. Host interface block
Block (18) receives the bit stream and
The stream is passed to the system decoder block (20). Shi
Is the stem decoder block (20) a bit stream?
From the input buffer (24) or
Load into optional external buffer (26). Aude
The audio decoder block (28) is an input buffer (24)
From the data, scale counting index, bit / code
Code values and subband samples to generate
In the buffer (30). Hardware fee
The filter operation unit block (32)
Retrieve information from file (30) and dequantize data
Transform, and filter to produce PCM output data
To load into the PCM buffer (34). PCM bag
The data in the file (34) is a PCM output block (36)
Output to the digital / analog converter (16)
It is.

Although the present invention has been described in detail, various changes, substitutions, and alterations can be made to the above-described embodiment without departing from the spirit and scope of the present invention.
It should be understood that the invention is limited only by the claims.

[Brief description of the drawings]

FIG. 1 is a block diagram of an audio decoding system including an integrated audio decoder system of the present invention.

FIG. 2 is a block diagram of a system decoder used in the integrated audio decoder of the present invention.

FIG. 3 is a block diagram of an audio decoder used in the integrated audio decoder of the present invention.

FIG. 4 is a block diagram of a hardware filter operation unit used in the integrated audio decoder system of the present invention.

FIG. 5 is a block diagram showing an address generation system used by the hardware filter operation unit of the present invention.

FIG. 6 is a more detailed block diagram of the math unit used in the hardware filter operation unit of the present invention.

FIG. 7 is a flowchart illustrating a dequantization operation performed by a hardware filter operation unit.

FIG. 8 is a flowchart illustrating a fast cosine transform operation performed by a hardware filter operation unit.

FIG. 9 is a flowchart of a finite impulse response filtering operation performed by a hardware filter operation unit.

FIG. 10 is a top view of the pinout of one embodiment of the audio decoder system of the present invention.

FIG. 11 is a flowchart showing high level activities of the audio decoder block.

FIG. 12 is a flowchart illustrating a process used by an audio decoder block to determine the amount of available buffer memory.

FIG. 13 is a flowchart illustrating a process performed by an audio decoder block to clear and initialize registers and variables used in the audio decoding process.

FIG. 14 is a portion of a flowchart illustrating the process by which an audio decoder block searches for synchronization characters in an incoming bit stream and obtains synchronization.

FIG. 15 is the remainder of the flowchart of FIG.

FIG. 16 is a portion of a flowchart of a process used by an audio decoder block to set up a frame when a headline is found in a bitstream.

FIG. 17 is a remaining part of the flowchart of FIG. 16;

FIG. 18 is a flowchart of a process used by an audio decoder block to calculate a frame size.

FIG. 19 is a flowchart of an error concealment process used by an audio decoder block when an error is detected in a frame or a synchronization lock state is not reached.

FIG. 20 is a portion of a flowchart of a process used by an audio decoder block to decode an audio frame.

FIG. 21 is a remaining part of the flowchart of FIG. 20;

FIG. 22 is a flowchart of a process used by an audio decoder block to decode side information included in a heading.

FIG. 23 is a flowchart of a process used by an audio decoder block to decode bit allocation information when the bitstream is layer 1 audio data.

FIG. 24 is a flowchart of a process used to decode bit allocation information when the frame is layer 1 audio data.

FIG. 25 is a flowchart of a process used to retrieve scale factor selection information associated with Layer 2 MPEG audio data.

FIG. 26 is a flowchart of a process used by an audio decoder block to decode a scale factor index for layer 1 MPEG audio data.

FIG. 27 is a portion of a flowchart of a process used by an audio decoder block to decode subband information of layer 1 MPEG audio data.

FIG. 28 is a remaining portion of the flowchart of FIG. 27;

FIG. 29 is a portion of a flowchart of a process used by an audio decoder block to decode a scale factor index for Layer 2 MPEG audio data.

FIG. 30 is a remaining portion of the flowchart of FIG. 29;

FIG. 31 is a portion of a flowchart of a process used by an audio decoder block to decode subband information of Layer 2 MPEG audio data.

FIG. 32 is a remaining part of the flowchart of FIG. 31;

FIG. 33 is a flowchart of a process used by an audio decoder block to perform group decoding.

FIG. 34 is a portion of a flowchart of a process used by an audio decoder block to perform buffer management for an input buffer and an external buffer.

FIG. 35 is a remaining portion of the flowchart of FIG. 34;

FIG. 36 is a flowchart of a general decoding operation performed by an audio decoder block.

FIG. 37 is a flowchart of a process used by an audio decoder block to process presentation timestamps.

FIG. 38 is a flowchart of a process used by an audio decoder block to decode and process auxiliary data that may be present in a bitstream.

[Explanation of symbols]

 Reference Signs List 10 audio decoding system 12 microprocessor host 14 audio decoder system 16 digital / analog converter 18 host interface block 20 system decoder block 22 control state register block 24 input buffer 26 external buffer 28 audio decoder block 30 arithmetic unit buffer 32 hardware filter operation Unit block 34 PCM buffer 36 PCM output block 38 FIFO 40 shift register (shifter) 42 shifter detector 44 shifter counter 46 control logic block 48 shifter copy register 50 control counter 52 control counter copy register 54 buffer interface block 56 data address counter 58 PTS Address counter 72 Packet bar Counter 80 microprogram ROM 82 instruction pipe register 84 instruction multiplexer 86 constant storage device 88 data bus 90 accumulator bus 92 program counter 94 program counter multiplexer 96 incrementer 98 constant storage device 100 subroutine stack 102 branch bus 104 execution control state machine 106 Arithmetic logic unit 108 control multiplexer 110 accumulator 112 multiplexer 114 data register 118 constant register 120 address bus 122 bypass multiplexer 124 multiplexer 126 data shifter 128 digit feed counter 130 load counter 132 DRAM / SRAM controller 134 DRAM interface 136 address multiplexer 138 special Regis Block 140 nBAL and BPCW ROM 142 RAM Scratchpad 144 ROM 150 Sample Memory 152 Finite Impulse Response (FIR) Memory 154 Math Unit 156 Accumulator 158 Register 160, 162, 164, 166 Multiplexer 168 Scale Factor ROM 170 C / D Factor ROM 172, 174 Address register 176 Multiplexer 178 Coefficient memory 180 Buffer register 182 Address generator 184 Sequence generator 186 Address ROM 188 CSBB address logic block 190 FIR address logic block 192 SBB address logic block 194 Coefficient address logic block 200 Multiplexer 202 Booth encoder 204, 206 , 208 partial product Generator 210, 212, 214 Carry / Save Adder 216 Pipeline Register 218, 220 Multiplexer 222 Carry / Save Adder 224 Multiplexer 225 Constant Storage 226 Carry Propagation Adder 228 Saturation Detection 0 Force Block 230 Carry In Logic Block 232 carry storage register 234 carry logic block

──────────────────────────────────────────────────続 き Continued on the front page (31) Priority claim number 08/054127 (32) Priority date April 28, 1993 (1993. 4.28) (33) Priority claim country United States (US) (72) Inventor Gerard Bambasa France 06570 Saint-Paul-de-Vence Cheman de Saint-Etienne Anne 746 (72) Inventor Kennis Earl Shea United States Texas 75007 Carrollton Collonges Drive 2054 (72) Inventor Steven H. Re United States Texas 75040 Garland Kingsbridge Drive 142 (72) Jonathan El Rowlands Inventor, Texas 75229 Dallas Townsend Drive 3247 (72) Inventor Shoe Wycombe United States of America 75082 Li Chardson Woodbury Place 2101 (72) Inventor Karen El Walker 75082 Texas, United States Richardson Woodglen Drive 2305 (56) References JP-A-61-201526 (JP, A) JP-A-63-7023 (JP, A) JP-A-63-200633 (JP, A) JP-A-3-263925 (JP, A) JP-A-4-104617 (JP, A) JP-A-63-201700 (JP, A) JP-A-4 -104606 (JP, A) JP-A-3-109824 (JP, A) JP-A-3-1771827 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03M 7/30 G10L 19/00

Claims (3)

(57) [Claims] 1. A data stream including sub-band encoded audio data according to a psychoacoustic model is taken into a data processing device, and the encoded audio data is separated from the data stream to form a frame of the sub-band encoded data. And wherein each frame of the sub-band encoded data includes a plurality of sub-band sample codes, using scale factor values derived from said bit stream, and within a data processing device. Dequantizing the sub-frame coded audio data of the latest frame by using the coefficient table stored in the first storage circuit portion of the first storage circuit portion to form the latest sub-band vector having dimension n, Transform the latest subband vector using the transform Form a V ′ vector having the same dimension m as dimension n, including a predetermined number of previous v ′ vectors and said latest v ′ vector to form a V ′ vector, and a set of finite vectors Filtering the V 'vector using an impulse filter to form a set of pulse code modulation (PCM) samples for output from the data processing device. How to decrypt. 2. The method of claim 1, wherein said fast direct cosine transform is a 32-point fast direct cosine transform, and said latest v 'vector has a dimension m of 32. 3. The fast direct cosine transform comprises adding a butterfly operator in a sequential, iterative manner, and adding a subtract operator, said butterfly operator comprising: y1 = x1 + x2 and y2 = (x1- x2) * d [i] in the form of a set of equations (y1 is the first of the most recent subband vector
New value for the second element of the latest subband vector, x1 is the previous value for the first element of the latest subband vector, x2
Is the previous value for the second element of the current subband vector, and d [i] is a coefficient having one value in the range bounded by positive and negative values). 3. The method of claim 2, operating on the current subband vector, and wherein said subtract operator corresponds to a set of equations of the form y1 = x1 and y2 = x2-x1.