JP3215215B2 - Logic cell parallel arrangement processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for automatically arranging cells or blocks using a computer in an automatic layout design of a gate array type or standard cell type semiconductor integrated circuit.

[0002]

2. Description of the Related Art A semiconductor integrated circuit device is constructed by arranging cells or blocks having a logical function or a memory function in a chip so as to obtain a desired circuit operation, and wiring the input / output terminals thereof. I have.

FIG. 12 shows a schematic configuration of a semiconductor integrated circuit chip according to a general gate array system. On the chip, an area 51 where cells are arranged, an area 52 where wiring between cells is provided, and an area 53 where peripheral input / output circuits are arranged are arranged. In general, a plurality of wiring layers can be used for wiring, and different layers are generally assigned to horizontal and vertical wirings.

In such a layout design of a semiconductor integrated circuit, it is common to automatically optimize the arrangement of cells and the wiring between terminals by using a computer. When deciding the cell arrangement in the arrangement processing, , An arrangement process is performed so as to facilitate the subsequent wiring process. For example, an appropriate evaluation function is set for the purpose of minimizing the virtual wiring length and equalizing the degree of wiring congestion, and optimizing the cell arrangement position. In a placement process by a computer, a final placement is usually determined by an initial placement phase for determining an initial state of placement and a subsequent sequential placement improvement phase.

At present, various layout optimization techniques are used in the layout improvement process. Among them, K &L's well-known partitioning algorithm (K &L's famous partitioning algorithm ( BWKernighan and S. Lin, "An Ef
ficient Heuristic Procedure for Partitioning Graph
s ", Bell Sys. Tech. J., Vol.49 pp.291-307, Feb. 197
0). This is a typical division method of the logic cell in the mini-cut arrangement, and the gain of the cell (a value indicating how many nets passing through the cut line decreases when the cell is moved) is successively accumulated. It is said that by doing this, a kind of look-ahead becomes possible, and generally good performance is obtained.

However, as can be seen from the example of division shown in FIG. 13, there are many problems to be taken into consideration, such as variations in the size of each cell and occurrence of imbalance in the number of cells in division. And the most serious problem is that if it falls into a locally optimal state depending on the initial solution, no further improvement can be expected.
Hereinafter, this problem will be described more specifically with reference to FIGS.

FIG. 2 shows an arrangement state determined from an initial state. A dotted line indicates a cut line set on a chip, a circle with a Roman character indicates a cell, and a solid line indicates a connection relation between them. Shall be shown. In this example, it is possible to obtain an optimal arrangement result as shown in FIG. 3 from a global perspective, and it should be possible to minimize the number of nets passing through the cut line to three.

[0008] However, once a local optimal arrangement state as shown in FIG. 2 is reached, the number of cuts tends to increase regardless of which cell is moved, and minimization does not proceed. Also, even when the K & L division algorithm is used, there is no decisive way to exchange cells J, I, L, K and cells O, M, P, N one after another without moving other cells at all. No further minimization can proceed.

For example, in the example of FIG. 2, cells F, H, U,
It is inevitable that any one of V, C, D, S, Q, etc. becomes a movement candidate first, and if this happens, even if the gain is accumulated and read ahead, further improvement is possible. Does not proceed and converges in this arrangement. That is, when there are a plurality of cells having the same gain, there is no selection criterion as to which cell should be moved first, so that the next arrangement state determined by these combinations cannot be guided in the optimal direction.

In addition, the number of cells having the same gain increases as the size of a large-scale LSI increases. Therefore, it is not possible to exhaustively examine all the layout improvement states determined by their permutations. there were.

On the other hand, the simplest method in the above-described arrangement improvement process is to exchange a position of a certain cell with a position of another cell to create a new arrangement state. There is a method to improve the arrangement by repeating the operation of returning to the original arrangement state if it gets worse (M.hanan, PKWolff Sr. ahd BJAgule, "Some
experimental results on placement techniques ", Pro
ceedings of the 13thDesign Automation Conference, 1
976, pp. 214-224.).

In this method, as the number of cells increases, the processing time required for improving the arrangement to obtain a satisfactory arrangement solution sharply increases. For this reason, there is a problem that it is necessary to achieve high-speed processing in order to effectively optimize within a practical processing time.

As a parallel arrangement improving method for solving this problem, there is a method of improving cells having no direct connection relationship with each other in parallel, or an LSI chip without such a limiting operation. A method of improving the parallel placement by dividing the region has already been proposed (ICCAD'86, A parallel s
imulated annealing algorithm for the placemet ofma
cro-cells, A Casotto and Alberto Aangiavanni-Vince
ntelli, UCB., JP-A-62-243071).

However, the former requires a lock mechanism for selecting mutually independent exchange cell pairs having no direct connection relationship in order to eliminate an improvement error when cell exchange processing is performed simultaneously and in parallel. An overhead for the operation of collecting and limiting the exchanged cell pair by the computer is generated every time a cell to be improved is selected. In addition, since there are usually a large number of exchange cell pairs, there remains a problem that many repetitive operations are required before the improvement converges, and it is difficult to perform global optimization at high speed.

On the other hand, in the latter method of simply dividing a region and parallelizing it, the placement improvement processing time in the divided region becomes non-uniform, and the placement improvement time of the entire chip takes the longest processing time. There is a problem in that it cannot be shortened due to the rules of the area (the degree of parallelism does not increase).

As described above, as the number of cells increases, the processing time required for improving the arrangement for obtaining a satisfactory arrangement solution sharply increases. For this reason, the processing time has to be shortened in order to effectively optimize within a realistic processing time.

For this reason, some parallel placement methods have already been proposed. However, in the method of dividing and parallelizing a region, the placement improvement processing time in the divided region becomes non-uniform, and the placement as a whole chip is performed. There is a problem that the parallelism is not increased because the improvement time is determined by the region where the processing time is the longest.

FIG. 13 is a schematic diagram showing an example of area division on a chip area for explaining this problem more specifically. Four areas divided by dotted lines are arranged and improved in parallel by separate computers. It corresponds to the unit area to be processed. Here, the large rectangle with half-tone is RAM / RO
Macro blocks such as M are shown, and small rectangles show other general cells.

If the chip is simply divided into four parts and processed as in this example, the number of cells to be effectively improved in each area is different. The processing time required for improving the arrangement in each area is significantly different. Since the placement improvement processing time of the entire chip is determined by the maximum value of the placement improvement processing time in each divided area as shown by the arrow in FIG. 13, the degree of parallelism does not increase with simple division.

As a general parallel processing method, a method of dynamically distributing and equalizing a load, a method of allocating processing to a processor in advance of processing that would take a long time, and the like can be considered. Certainly, the former is relatively effective when the number of processors used is relatively small and the target processing unit is small and large (granularity is small), and the load is stochastically uniform and effective. There was a problem that the imbalance remained.

In the latter case, it is not possible to absorb a load situation that changes every moment during execution or a variation in the performance of a computer to be used, and there is no guarantee that the loads become even. When the granularity is large, the load imbalance remains as in the former case, and the problem is not solved.

However, if the divided areas are adjusted as shown in FIG. 6, the layout improvement processing time in each area is uniformed as shown by the arrows, and the calculation time required for the layout improvement processing of the entire chip is reduced. Be transformed into In other words, if such a preparatory procedure for the division is taken, the available processor can be effectively used, and the speed-up of the layout processing can be realized.

By the way, the number of transistors mounted on the ULSI is increasing at a rate of several times every year due to the improvement of the integration degree due to the advance of the ULSI manufacturing technology, and within a few years. While it is expected that megagate class LSIs will be feasible, it is strongly required that they be produced in a short period of time. For this reason, the layout CAD must process a large amount of data at high speed.

Various methods have been proposed for automatic placement, but in most cases, a single CP is used.
Since processing has been performed sequentially using U, the calculation speed is limited, and it is difficult to reduce the calculation time. In order to increase the calculation speed, a method of increasing the speed of the CPU or a method of performing parallel processing by multiple CPUs to greatly reduce the calculation time can be considered. Of these, the method of increasing the speed of the CPU is naturally limited. On the other hand, an arrangement method for shortening the calculation time by parallel processing has been conventionally proposed.

Conventionally, in the parallel arrangement processing, after a parallel area is set, an area is arbitrarily allocated to each processor. When the number of parallel areas is larger than the number of processors, each processor processes a plurality of areas. As a result, there is a problem that the difference between the total processing times of the respective processors becomes large.

In this case, even if the processor which has completed processing of one area is immediately processed by another unprocessed area to improve the degree of parallelism, the processing of the last remaining area is extremely difficult. However, there is a problem that the processing load is applied to only one processor, and the other processors end the processing and the degree of parallelism decreases.

[0027]

As described above, in the automatic arrangement, the improved algorithm based on the conventional greedy division method already proposed is generally far more than the optimization method such as annealing. Although it is fast, it has a drawback that it falls into a local optimal solution and the improvement does not proceed sufficiently. This is due to the fact that once the cell has fallen into the local arrangement state as shown in FIG. 2, sufficient optimization cannot be realized only by evaluating the cell alone and repeating the movement.

In the conventional placement improvement method in automatic placement, when the chip area of the LSI is divided and parallelized, when there is no large difference between the number of available processors and the number of divided areas, the load is reduced. There is a problem that it is difficult to disperse and equalize the data and the degree of parallelism is reduced.

Further, in the conventional method for arranging cells in parallel in an LSI design, after setting a parallel area,
If the processing of the last remaining area takes a very long time because the area is allocated arbitrarily to each processor, the processing is performed only by one processor, even if the other processors have completed processing. In some cases, the parallel effect of the layout is reduced.

The present invention has been made to solve such a problem, and the first object of the present invention is to first improve the system by a greedy method to quickly approach an optimum state, An object of the present invention is to provide a method of parallel arrangement of logical cells, which can globally find an optimal arrangement state by dynamically grouping and moving cells.

It is another object of the present invention to provide a high-speed cell arrangement improving method. A third object of the present invention is to increase the degree of parallelism of layout processing by allocating each area to a processor in consideration of the evaluation value of a parallel area when performing parallel processing, thereby achieving a high-speed and effective placement result. And a method for arranging logic cells in parallel.

[0032]

According to a first aspect of the present invention, in a layout design of a semiconductor integrated circuit, when a cell arrangement position is automatically determined using a computer, an LSI chip area is divided. A step of configuring a plurality of areas; a step of selecting cells whose number of nets passing between the divided areas is reduced by moving or exchanging the cells to improve an arrangement position; and a step of passing between the divided areas Selecting a cell set in which the number of nets is reduced by moving or exchanging the cell set to improve the arrangement position, and optimizing the cell arrangement in the divided areas.

According to a second aspect of the present invention, in a method of automatically arranging a plurality of cells on a semiconductor substrate by using a computer, an LSI chip area is cut and divided into a plurality of areas. A step of subtracting cells whose positions such as macroblocks are fixed and calculating a substantial improvement target cell in the area when the cell arrangement improvement processing in the area is performed simultaneously and in parallel using a plurality of computers. Calculating the number of nets connected inside the region and the number of nets connected outside the region; calculating the gap between the target placement evaluation value within the region and the current placement evaluation value; and the performance of the computer used. And a step of calculating a load condition to determine a method of dividing the chip region, and to make the arrangement improvement processing time in each region uniform.

According to a third aspect of the present invention, there is provided an automatic layout system for a semiconductor integrated circuit, wherein a target area is divided into a plurality of areas, and a cell set is arranged in parallel in improving cell arrangement. Is evaluated, and a parallel processing area is allocated to a process based on the evaluation value.

[0035]

According to the first aspect of the present invention, in a method of automatically arranging a plurality of cells on a semiconductor substrate by using a computer, the means for improving the arrangement state includes a connection between the improving means by moving a single cell and a net. , An appropriate cell group is constructed, and the cell group is moved for each cell set. As a result, it is possible to realize an optimization that simultaneously satisfies the effect of advancing the improvement at a high speed and the effect of exiting the locally optimal state and finding a more optimal arrangement state globally.

According to a second aspect of the present invention, in a method of automatically arranging a plurality of cells on a semiconductor substrate by using a computer, an LSI chip area is divided into a plurality of areas, and each area is divided into a plurality of areas. When the cell placement improvement processing is performed simultaneously and in parallel using a plurality of computers, the placement improvement processing time in each region can be made uniform, and the placement improvement time of the entire chip takes the longest processing time. This solves the problem that it cannot be shortened due to the rules of the area (the degree of parallelism does not increase).

As a result, high-speed processing can be effectively realized by executing the arrangement improvement processing in the area simultaneously and in parallel by different processors. In addition, this method naturally requires an estimated time (overhead) for determining a divided area, but this estimated time is very short as compared with the processing time for actually repeating the layout improvement in the area. realizable. Therefore, it is much more efficient than a case where a plurality of processors are put into a waiting state once an uneven load is assigned, and a decrease in the degree of parallelism can be avoided.

Further, according to the third aspect of the present invention, when the layout processing is parallelized, each area is assigned to a processor based on the evaluation value of the parallel area. The processing time is made uniform and the parallel effect can be improved.

[0039]

An embodiment of the present invention will be described below.

FIG. 1 is a flowchart showing a schematic processing procedure of the first invention. A detailed processing procedure for realizing this is described at the end of the embodiment in the form of detailed processing steps step0 to step21. I have. Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 2 and 3 and detailed processing procedures step0 to step21 along the flow of the flowchart of FIG.

After START, first, the chip area of the LSI is divided into two by a cut line to create a divided area.
Then, cells in each divided area are provisionally determined, and an initial arrangement state is determined. This initial arrangement may employ, for example, a random cell arrangement (S1).

Next, the degree of improvement is initialized in the initial division completed in (S1) (step 0), and a congested divided area of cells is selected (step 1). Next, a cell having the highest effect of reducing the number of nets passing through the cut line is selected from the cells in the congested area (S2), the cell is moved (S3), and the improvement is accumulated (step).
2). Next, the arrangement state is compared with the previous arrangement state, and if there is a degree of improvement, the arrangement state is updated (step 3).

Next, according to the improved convergence determination conditions of step 4 to step 6, the arrangement improvement processing by the single cell movement as described above (from S2 to S3) is performed until convergence. As a result, the cell selection with the maximum gain and the movement processing of the cell are repeated. (S2 to S4).

In the above-described arrangement improvement process by moving a single cell, the arrangement state is improved from the cell having the highest improvement effect, and the optimization proceeds rapidly. As a result, it converges to a certain local arrangement optimal solution. This is an arrangement state as shown in FIG. 2, for example.

Next, in order to further improve the layout from such a locally optimum layout, steps 7 to 7 are described.
In step 14 (S5 to S7), a cluster of cells is dynamically formed, and movement is attempted in cluster units. If the cell filling rate in the destination area exceeds the allowable range due to the movement of the cluster, the same procedure s is performed.
Replace with a dynamically formed cluster according to steps 15 to 21.

As a method of forming a cluster, cells having a high effect of improving the arrangement state (cells having a high gain, usually a plurality of cells) are once packed in a queue, and these cells are set as kernel candidate candidates for each cluster (step 9). , Step1
6) Next, one candidate cell serving as a core of the cluster is selected from this queue (step 10 and step 17), and
The cells connected to the cell are connected in a chain,
Create a cluster (cell set) by adding it to the list of states sorted in descending order of gain (step
11, step 13, step 18, step 20).

As a result, a cluster having the maximum gain determined by the net connection relation can be dynamically extracted from a certain arrangement state. In creating the cluster, the size of the cluster is adjusted so that the balance of the cell filling rate in each of the divided areas is not broken by the movement / exchange of the cluster (steps 12 and 19).

According to the above-described processing procedure, for example, when the cell set composed of the cells J, I, L, and K is collectively moved from the arrangement state as shown in FIG. In addition, it is possible to evaluate the case where the cell set is replaced with a cell set composed of cells O, M, P, and N. Therefore, even if a local optimal solution as shown in FIG. 2 is found, it is possible to escape from it and further optimize it, and in this case, as a result, a global solution as shown in FIG. The improvement will proceed to the optimal arrangement state.

Next, it is determined whether or not the improvement by the generation of the cluster having the largest gain by the above processing procedure (S5) and the movement of each clustered cell set (S6) has been successful (S7). If the improvement is successful, return to (S2),
The process from the improvement process by a single cell movement to the improvement process in cluster units is repeated according to the procedure. If unsuccessful, stop the placement optimization process.

As described above, in this embodiment, the means for evaluating the movement of a dynamically clustered cell set from a certain arrangement state in a situation where the arrangement positions of other cells do not change and the improvement by single cell movement Use different evaluation methods to improve the layout. As a result, it is possible to realize an optimization that simultaneously satisfies the effect of advancing the improvement at a high speed and the effect of breaking out of a locally optimal state and finding a more optimal arrangement state globally.

It should be noted that the present invention is not limited to the above-described embodiment, but can be modified and implemented without departing from the spirit thereof.

Detailed processing procedure step 0: The cut number reduction cumulative value G of the registered arrangement state is set to 0. Step 1: A congested region R of a cell is selected. Step 2: A cell in which the number of cuts is reduced by movement from the region of R is moved to the opposite side of the cut line to create a temporary arrangement state, and the reduced value of the number of cuts is accumulated G. Step 3: If the cumulative value G is equal to or larger than the maximum value of G up to the present, the registered arrangement state is updated.

Step 4: Steps 1 to 3 are repeated until all cells have been moved or fall below the cumulative lower limit. step5: if the maximum value of the cumulative value G is positive, step0
What. Step 6: The maximum value of the accumulated value G is 0 and there is a moving cell,
If there is a cell having a positive gain among all cells in the congested area of the cell, go to step0.

Step 7: The cut number reduction cumulative value T of the registered arrangement state is set to 0. Step 8: Select a congested region R of cells. Step 9: The cell in which the number of cuts is reduced most by the movement from within the region R is inserted into the cell QUEQ. Step 10: One cell is taken out of the cell QUEQ and the gain sorted list L is initialized. If Q is NULL, END.

Step 11: Gain sorted list L
One cell C is taken out from the table and moved to the opposite side of the cut line to create a provisional arrangement state, and the reduced value of the number of cuts is accumulated T
I do. Step 12: If the total cell area limit value is exceeded, step 1
To 0. Step 13: If the accumulated value T is not positive, add a new cell in the same area connected to the cell C to L, and go to step 11. Step 14: If the difference between the cell filling rates is equal to or smaller than the allowable range, the registration of the arrangement state is updated, and the process proceeds to step 10.

Step 15: Cell Congested Area R
Select Step 16: The cell whose cut number is reduced most by the movement from the area of R is inserted into the cell QUEU. Step 17: One cell is taken out of the cell QUEU and the gain sorted list L is initialized. If U is NULL, go to step 10.

Step 18: Gain sorted list L
One cell is taken out from the cell and moved to the opposite side of the cut line to create a temporary arrangement state, and the decrease value of the number of cuts is accumulated T. Step 19: If the total cell area limit value is exceeded, step 1
Go to 7. Step 20: If the accumulated value T is not positive, add a new cell in the same area connected to the cell C to L and go to step 18. Step 21: Go to step 14.

Second Embodiment FIG. 5 is a schematic diagram showing the relationship between the processors respectively responsible for the divided areas on the chip. The four rectangles with P are divided on the chip. Each processor allocated to each area is shown.
Each processor has basic computing and storage devices,
As shown by the bold line, it is connected to the processor on the control side by a communication channel. The transfer of the arrangement data and the overall control are performed via these communication means, and the respective processors operate simultaneously and in parallel.

FIG. 6 is a schematic diagram showing an example of area division on a chip area for explaining an embodiment of the present invention. Four areas divided by dotted lines are simultaneously arranged in parallel by separate computers for improvement. It corresponds to a unit area for processing. In this example, if the chip is simply divided into four and processed as shown in FIG. 13, the number of cells to be effectively improved in each area is different.
The processing time required for improving the arrangement in each area is significantly different.

Since the layout improvement processing time of the entire chip is determined by the maximum value of the layout improvement processing time in each of the divided areas, the degree of parallelism does not increase by such a simple division. However, if the divided areas are adjusted as shown in FIG. 6 of the embodiment, the arrangement improvement processing time in each area is made uniform and uniform.
The processing time for improving the arrangement of the entire chip is shortened.

FIG. 4 is a flow chart of the present invention showing a processing procedure for realizing the area division as shown in FIG. 6. According to such a procedure, the speed of the layout processing can be increased by effectively utilizing the available processor. Can be realized. The second
The parallel arrangement processing method according to the present invention will be described with reference to the flow chart of FIG.

After the start, first, the LSI chip area is cut along a cut line and temporarily divided into a plurality of rectangular areas (S1).
1). Thereby, the chip is divided into two in the vertical direction and two in the horizontal direction, for example, as shown by a dotted line in FIG.
A total of four divided areas are configured.

Next, in each divided area completed in (S11), the number of cells to be substantially improved in the area is calculated by subtracting cells in which the positions of macroblocks and the like are fixed.
EC (S12). Next, the number of nets connected inside the area and the number of nets connected to the outside of the area in each divided area formed by the temporary division are calculated, and are set as IN, respectively (S13). Next, in each divided area formed by the temporary division, a deviation between a target arrangement evaluation value in the area and a current arrangement evaluation value is calculated, and is set as a DF (S14). Next, the performance of the computer to be used and the current operation (load) status are calculated and set as PW and LD (S15).

Next, from the values obtained in (S12) to (S15), a load estimation value E is calculated by, for example, the following formula, and correction of the area division is repeated so that the estimation values become equal. The area allocated to the processor is determined (S16). Note that a to d in the calculation formulas are weighting factors for each item. As a result, the divided area on the LSI chip is corrected, for example, as shown by a dotted line in FIG. 6, and four new divided areas are determined.

[0065]

(Equation 1) Once the area division is determined by (S16),
A different computer (processor) is assigned to each of these areas, and the arrangement improvement processing in each area is executed simultaneously and in parallel (S17). Here, since each processor repeats the placement improvement only in the partial area in which it is assigned, it is possible to improve the placement at a higher speed than the placement processing of the entire chip. Finally, the result of the placement improvement in each area by each processor is collected, and the placement result of the entire chip is synthesized. finish.

In the second invention, as described above, the layout improvement for each divided area is parallelized, and the layout optimization of the entire chip is performed at high speed. Note that the present invention is not limited to the above-described embodiment, and can be implemented with various modifications without departing from the spirit of the present invention.

Third Embodiment A specific embodiment of the third invention will be described below with reference to FIGS. In the present embodiment, when an initial arrangement is given in a layout target area of a gate array, a plurality of parallel areas are set and assigned to a processor, an arrangement improvement process is performed in parallel, and a cell arrangement position is determined. explain. Here, a case where the number of child processors is 5 and the number of parallel areas is 9 is considered.

FIG. 7 is a diagram showing a processing flow in this embodiment. First, as shown in FIG. 8, parallel areas 2 to 10 are set for a given layout target area 1.
Next, as shown in FIG. 9, an evaluation value at the present time is obtained for each of the parallel areas 2 to 10 based on the given arrangement state. Here, based on the current arrangement result, a value obtained by integrating the cells, the number of cuts, and the pin dispersion value (the number shown in parentheses) is obtained for each of the parallel regions 2 to 10.

As shown in FIG. 10, the parallel areas 6, 9, 3, 5, and 4 are assigned to the processors 20 to 2 in ascending order of the evaluation value.
4 and perform arrangement improvement processing in parallel. Each of the processors 20 to 24 determines the convergence in each area based on the evaluation value, and ends the improvement of the arrangement in the area when convergence is recognized. In this case, since the evaluation value used when allocating an area to the processors 20 to 24 is the same as the evaluation value used for determining the convergence of the area, it is considered that processing with a lower evaluation value before processing requires more time. .

When the processors 20 to 24 complete the improvement of the area arrangement, the areas to be processed next are assigned in the order of 7, 10, 8, and 2 having the lowest evaluation value from the unprocessed areas each time. The processing is performed until the arrangement improvement processing converges.
The above processing is repeated until the layout improvement of all the parallel areas 2 to 10 is completed and there is no unprocessed area.

FIG. 11 shows, as a conventional example, the relationship between the processing time of each processor and the allocated area when the areas are allocated in order from the lower left of the chip according to the area number.
In this case, since the evaluation value is not taken into account, the processor that has completed processing of one area is immediately made to process another unprocessed area, thereby improving the degree of parallelism.

However, the processing of other processors ends, and the processing load may be applied to only one processor, so that the degree of parallelism decreases. On the other hand, as shown in FIG. 10, in the present embodiment, since the processor that has completed the processing quickly is allocated from the one with the worse evaluation value, that is, from the area where the processing time is expected to take longer, the load is uniformly applied to each processor. To increase the degree of parallelism.

[0073]

As described above, according to the first aspect,
When automatically deciding the cell placement position using a computer in the layout design of a semiconductor integrated circuit, if the improvement can be achieved by moving or exchanging a single cell first, improve the arrangement of these cells first. To quickly reach the optimal arrangement. Also, after such an arrangement improvement method has converged, global arrangement improvement can be performed by moving or exchanging each group dynamically configured from the connection relation of the nets. As described above, if the level of improvement is dynamically changed according to the nature of the arrangement state, optimization can be performed at high speed while escaping from the local optimum solution.

According to the second aspect of the present invention, in the automatic placement processing for determining the placement location of a cell using a computer, L
Even if there is no large difference between the number of divided regions on the SI chip and the number of available processors, parallelization with little loss can be realized, and the processor is effectively used to speed up the layout improvement processing. It is possible to do.

Further, according to the third aspect of the present invention, when the layout processing is parallelized, each area is assigned to a processor based on the evaluation value of the parallel area. The processing time is made uniform and the parallel effect can be improved.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a processing procedure according to an embodiment of the first invention.

FIG. 2 is a schematic diagram for explaining a problem of the related art with respect to the first invention.

FIG. 3 is a schematic view for explaining one embodiment of the first invention.

FIG. 4 is a flowchart showing a processing procedure according to an embodiment of the second invention.

FIG. 5 is a schematic configuration diagram showing a relationship between processors in the second invention.

FIG. 6 is a view for explaining an embodiment of the invention in the second invention.

FIG. 7 is a flowchart showing an arrangement processing procedure according to an embodiment of the third invention.

FIG. 8 is a diagram showing a parallel area according to an embodiment of the third invention;

FIG. 9 is a diagram showing an evaluation value for each parallel region according to one embodiment of the third invention;

FIG. 10 is a diagram showing a relationship between a processing time for each processor and an allocated area according to an embodiment of the third invention.

FIG. 11 is a diagram showing a relationship between a processing time and an assigned area of each conventional processor according to the third invention.

FIG. 12 is a schematic diagram for explaining a problem of the related art with respect to the first and second inventions.

FIG. 13 is a diagram showing a schematic configuration of a chip of a conventional semiconductor integrated circuit for the first and second inventions.

[Explanation of symbols]

 A to X cell 1 layout target area 2 to 10 area set for parallel use 20 to 24 processor

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/82 G06F 17/50 H01L 21/822 H01L 27/04

Claims (7)

(57) [Claims] In a layout design of a semiconductor integrated circuit, when automatically determining a cell arrangement position by using a computer, a step of dividing a chip area of an LSI to form a plurality of areas, Selecting a cell in which the number of nets passing between the divided areas is reduced by moving or exchanging the cell and improving the arrangement position; and moving or exchanging the cell set by the number of nets passing between the divided areas. Selecting a cell set reduced by the above and improving the arrangement position, and optimizing the cell arrangement in the divided areas. 2. The method according to claim 1, wherein in the step of selecting a cell, a cell in which the number of nets passing between the divided areas is minimized by moving or exchanging the cell is selected to improve an arrangement position. Item 6. A method for processing parallel arrangement of logic cells according to Item 1. 3. The step of selecting a cell set is characterized by selecting a cell set in which the number of nets passing between the divided areas is the smallest by moving or exchanging the cell set and improving the arrangement position. 2. The parallel arrangement processing method for logic cells according to claim 1, wherein 4. When finding the cell set to be moved or exchanged, the cell set is determined by chain-operating the cells connected to the net from the cell selected in the cell selecting step. 3. The method according to claim 1, wherein
A parallel processing method for arranging logic cells according to the above description. 5. A step of dividing a chip area of an LSI to form a plurality of areas when automatically determining a cell arrangement position using a computer in a layout design of a semiconductor integrated circuit. Selecting a cell in which the number of nets passing between the divided areas is reduced by moving or exchanging the cell to improve the arrangement position; and, after this step, the number of nets passing between the divided areas is determined by the cell set. Selecting a cell set that is reduced by movement or replacement of the cell and improving the arrangement position, and optimizing the cell arrangement in the divided areas. 6. A method of automatically arranging a plurality of cells on a semiconductor substrate using a computer, wherein the chip area of the LSI is cut and divided into a plurality of areas, and the cell arrangement in each area is improved. When performing the processing simultaneously and in parallel using a plurality of computers, a step of calculating a substantial improvement target cell in the area by subtracting a fixed cell position such as a macroblock in the divided area. , calculates the displacement of calculating a number of nets connected to the network and the divided regions outside the placement evaluation value and the current placement evaluation value as a target of the divided region to <br/> connected inside the divided region Performing a step and a step of calculating the performance and load state of a computer to be used to determine a method of dividing a chip region, and uniforming the placement improvement processing time in each of the divided regions. Logic cells in parallel End processing method. 7. In an automatic layout system for a semiconductor integrated circuit, a target area is divided into a plurality of areas, and a cell set of each area is used for improving cell arrangement in parallel.
Calculating an evaluation value based on the state in which the logic cells are arranged, and allocating a parallel processing area to the processor based on the evaluation value .