JP3211948B2 - ATM cell demultiplexing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM (Asynchro
The present invention relates to a demultiplexing method using cells, and more particularly to an ATM cell demultiplexing circuit for reducing the frequency of cell discarding.

[0002]

2. Description of the Related Art In a conventional ATM transmission apparatus, for example, as described in Japanese Patent Laid-Open No. 4-79540, a buffer memory is provided for each output transmission line, and an overhead according to the format of the transmission line is added. And multiplex,
It is sent to the transmission line. FIG. 2 shows the configuration of this conventional ATM cell transmission device.
Empty cell detector 34, overhead head pattern generator 3
5, a timing signal generator 36, a multiplexer 37, and a transmitter 38.

In FIG. 2, input signals are stored in a buffer memory 33 in the order of input. However, since there is a possibility that an empty cell is included in the input, when an empty cell is detected by the empty cell detector 34, the writing is stopped. The overhead pattern creating unit 35 generates an overhead according to the format of the transmission path. The timing signal generator 36 determines the timing of the output of the overhead or the output of the ATM cell according to the transmission line format, and generates a read control signal to the buffer memory 33 when the output timing is the ATM cell.

[0004] The multiplexing section 37 includes a timing signal generating section 3.
6, the signal from the overhead pattern creating unit 35 is output to the AT
If it is the M cell output timing, a signal from the buffer memory 33 is selected and output. The transmitting unit 38 includes the multiplexing unit 3
7 is output to the output transmission path as a signal in the SONET format.

The empty cell detector 34 of this circuit prohibits writing to the cell buffer only when the cell header indicates an empty cell.
If this circuit is changed to output a write signal only when a cell having a value of (Virtual Path Identifier) is input, this circuit becomes an ATM cell demultiplexing circuit. In this circuit, when the input transmission speed is instantaneously higher than the output transmission line transmission speed, buffer overflow occurs in the buffer memory 33 and cell loss occurs.

[0006]

In a conventional ATM cell demultiplexing circuit, if the amount of buffer memory used for cell separation is small, buffer overflow occurs, the frequency of cell discarding increases, and cell loss increases. . Although the cell loss can be reduced by increasing the capacity of the buffer memory, increasing the capacity of the buffer memory for each output transmission line causes a rapid increase in hardware of the entire circuit, and also increases the cost. .

In view of the above problems, an object of the present invention is to provide an ATM cell demultiplexing circuit capable of minimizing the increase in hardware and reducing the frequency of ATM cell discarding in ATM communication. It is in.

[0008]

An ATM cell demultiplexing circuit according to the present invention includes means for separating cells according to the VPI value of an ATM cell in an input signal, and a cell input speed higher than a transmission speed of an output transmission line. Means for detecting an over-input state;
A means for storing cells in the shared buffer when the over-input state is detected; and a means for removing the stored cells from the shared buffer when the over-input state is restored.

The ATM cell demultiplexing circuit of the present invention is provided with a shared FIFO (first-in first-out memory), so that even when the average speed or arrival interval of the input ATM cell stream becomes high, the temporary cell is stored in the shared FIFO. Can be stored, and the cell loss can be kept small. Further, by adopting a configuration in which the FIFO is shared by all output transmission lines, an increase in the amount of hardware can be minimized.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of an ATM cell demultiplexing circuit according to the present invention. The circuit shown in FIG. 1 has a VPI among ATM cells from an input transmission line.
= A to the output transmission line 1 and VPI =
The ATM cell having the value of b is output to the output transmission line 2 and VPI = c
Is configured to be output to the output transmission line 3.

In the ATM cell demultiplexing circuit shown in FIG.
The physical layer device 1 includes a physical ray termination circuit 101 for terminating a physical layer of a transmission signal from an input transmission line and an ATM.
And a line FIFO 102 for taking out cells. The read control circuit 202 is connected to the line FIFO 102
, And a read signal to the line FIFO 102 and a shared FIFO 20 based on the signal.
1 is generated.

The shared FIFO 201 stores a data signal inputted therein at the same time as a write signal is inputted from the read control circuit 202. VPI filter 20
3 receives the cell presence indication signal from the shared FIFO 201, generates a read signal based on the signal, and
The ATM cell is read from O201. The VPI filter 203 includes a VPI input for the output transmission line 1 and an output transmission line 2
According to the values of the VPI input for output and the VPI input for output transmission line 3, if the ATM cell read from the shared FIFO 201 matches the header, write signals 1 and wr are respectively provided.
The te signal 2 and the write signal 3 are output.

The physical layer device 2 internally has a line FI
FO 301 and physical layer termination circuit 302,
When the write signal 1 from the VPI filter 203 is active, the data signal input at the same time is
The cell is stored in O301, and the physical layer termination circuit 302 converts the cell into the transmission format of the output transmission line 1 and outputs it to the output transmission line 1. Physical layer devices 3 and 4 are:
The output transmission line 2 has the same configuration as the physical layer device 2,
Output to 3.

Next, the operation of the circuit of the present invention will be described. Here, the value a is input to the VPI input for the output transmission line 1, the value b is input to the VPI input for the output transmission line 2 in FIG.
It is assumed that the value c is input to the PI input.

The physical layer termination circuit 101 receives a signal from an input transmission line, extracts an ATM cell from the received signal according to the physical layer transmission format,
Output to the IFO 102. The line FIFO 102 stores the input ATM cells in the input order. Line F
The IFO 102 activates the cell presence indication signal when there is a cell that has been written without being read, and does not activate when there is nothing.

The read control circuit 202 has a line FIFO
When the cell presence indicator signal from 102 is active, the FIFO control signal is activated, and when the cell presence indicator signal is not active, the FIFO control signal is not activated. The line FIFO 102 outputs the cell data stored therein to the data line if the FIFO control signal from the read control circuit 202 is active, and does not output it if it is not active. Also, the shared FIFO 201
If the FIFO control signal is active, the signal of the simultaneously input data line is stored internally.

Therefore, when the FIFO control signal from the read control circuit 202 becomes active, the line FI
The ATM cells stored in the FO 102 are shared by the shared FIFO 20
1 will be saved again. Similarly to the line FIFO 102, when there is a cell that has not been read and remains written, the shared FIFO 201 activates the cell presence display signal.

The VPI filter 203 has FULL signals 1, 2, 3 inputted from the physical layer devices 2, 3, 4.
Are not active, if the cell presence indication signal output from the shared FIFO 201 is active,
The cell is read from the shared FIFO 201 by activating the d signal. At the same time, the VPI filter 203 compares the VPI field of the read cell with the input values of the VPI for the output transmission line 1, the VPI for the output transmission line 2 and the VPI for the output transmission line 3, and matches the VPI for the output transmission line 1. When the write signal 1 is activated, the output transmission line 2 VP
When the value matches I, the write signal 2 is activated. When the value matches the VPI for the output transmission line 3, the write signal 3 is activated.

When at least one of the FULL signals 1, 2, and 3 from the physical layer devices 2, 3, and 4 is active, the VPI filter 203 shares the cell presence indication signal from the shared FIFO 201 even if the signal is active. FI
Cell reading from the FO 201 is not performed.

The line FIFO 3 of the physical layer device 2
01 is a write signal 1 from the VPI filter 203
VP from the VPI filter by storing the data of the data line input simultaneously when
Only cells with I = a will be saved. Also line F
The IFO 301 activates the FULL signal 1 when the data is stored up to the maximum storable cell.

The physical layer termination circuit 302 has a line FI
When an ATM cell is stored in the FO301,
The cell is read, converted according to the transmission format of the output transmission line 1, and output. By this operation, ATM cells of VPI = a are separated and output to the output transmission line 1. The physical layer devices 3 and 4 also output only ATM cells of VPI = b and c to the output transmission lines 2 and 3, respectively, by the same operation as the physical layer device 2.

According to the above operation, VPI in the input signal
If the input rate of the ATM cell having the a = a is lower than the transmission rate of the output transmission path, the cells are sent to the output transmission path 1 without line or line accumulation in the line FIFO 301. On the other hand, assuming that the ATM cell input speed of VPI = a in the input signal is higher than the transmission speed of the output transmission line 1, cells are gradually accumulated in the line FIFO 301. If this state continues, the line FIFO 301 will notify the VPI that the cell input speed is higher than the output transmission line speed when the cell storage amount reaches the predetermined capacity.
The FULL signal 1 shown in the filter 203 is activated.

The VPI filter 203, which has received the fact that the FULL signal 1 is active, stops reading cells from the shared FIFO 201.
The ATM cell a is stored in the shared FIFO 201. Then, if the ATM cell input speed of VPI = a becomes slower than the speed of the output transmission line 1 before the FIFO capacity of the shared FIFO 201 is reached and the capacity of the line FIFO 301 becomes available, the FULL signal 1 becomes inactive at that time. , VPI stored in shared FIFO 201 =
Since the ATM cell a is output to the line FIFO 301 via the VPI filter 203, no cell loss occurs.

[0024]

According to the present invention, since the total buffer capacity is increased by providing the shared FIFO, the frequency of cell discarding is reduced even when the transmission speed or arrival interval of the separated ATM cell stream is increased. Can be suppressed. Also,
This shared FIFO is shared by each output transmission line, and the increase in the amount of hardware can be suppressed lower than a method in which a large-capacity FIFO is provided for each output transmission line.

[0025]

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an ATM cell demultiplexing circuit according to the present invention.

FIG. 2 is a block diagram showing a conventional example.

[Explanation of symbols]

 Reference Signs List 101 Physical layer termination circuit 102 Line FIFO 201 Shared FIFO 202 Read control circuit 203 VPI filter 301 Line FIFO 302 Physical layer termination circuit 401 Line FIFO 402 Physical layer termination circuit 501 Line FIFO 502 Physical layer termination circuit 33 Buffer memory 34 Free cell detector 35 Overhead pattern generator 36 Timing signal generator 37 Multiplexer 38 Transmitter

Continuation of the front page (56) References JP-A-4-334144 (JP, A) JP-A-6-284453 (JP, A) JP-A-4-213255 (JP, A) JP-A-6-85840 (JP) JP-A 8-251198 (JP, A) JP-A 9-162884 (JP, A) JP-A 8-335944 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB (Name) H04L 12/56

Claims (4)

(57) [Claims] An ATM cell received from an input transmission line is shared.
Means for storing in a buffer having data, and storing in the shared buffer
The read ATM cell is read, and the read ATM cell is read.
The output transmission path is determined according to the VPI value of the cell.
Means for outputting a cell to the output transmission path,
Cell input speed to the power transmission line is equal to the cell output speed of the transmission line.
Means for detecting an over-input state faster than
Is detected before the over-input state is recovered.
Stop reading ATM cells from shared buffer
Means for demultiplexing ATM cells. Means for detecting an over-input state in which a cell input speed is higher than a cell output speed of said output transmission line, wherein said cell is stored in a line FIFO provided in a physical layer device on said output transmission line side. 2. The ATM cell demultiplexing circuit according to claim 1, further comprising means for detecting that the number has reached the maximum storable cell. 3. An ATM receiving signal from an input transmission line
An input-side physical layer device for extracting a cell, a shared FIFO for storing the ATM cell output from the input-side physical layer device, and an ATM cell stored in the shared FIFO. A VPI filter that separates the ATM cell for each output transmission line in accordance with the VPI value of the VPI filter, a line FIFO and a physical layer termination circuit therein, and the AT that is input simultaneously with a write signal from the VPI filter.
A plurality of output-side physical layer devices for storing M cells in the line FIFO, converting the ATM cells into a transmission format of an output transmission line in a physical layer termination circuit, and outputting the converted cells to the output transmission line; The line FIFO in the side physical layer device is
A FULL signal indicating that the number of cells stored in the line FIFO has reached the maximum storable cell is output to the VPI.
Means for outputting to the filter, the VPI filter
Is a line F in the plurality of output side physical layer devices.
When the FULL signal is input from any of the IFOs
The ATM cell stored in the shared FIFO.
Stops reading and the FULL signal is released.
Sometimes reading of subsequent ATM cells from the shared FIFO
AT having means for restarting delivery
M cell demultiplexing circuit. 4. The VPI filter according to claim 1, wherein the shared FIFO is
Comparing the VPI value of the cell read from O with the VPI value of each of the plurality of output transmission lines, and transmitting the cell to the line FIFO in the output side physical layer device of the coincident transmission line. The ATM cell demultiplexing circuit according to claim 3.