JP3211169B2 - Circuit that converts voltage to current - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

This invention relates to the design of tunable transconductance devices and monolithic continuous-time filters.

[0002]

2. Description of the Related Art Monolithic, continuous-time, high-frequency filters preferably conform to capacitors and transconductance rather than to operational amplifiers. In general, there are many strict requirements for transconductance building blocks. These blocks must have a large dynamic range. Furthermore, it must be configured with a simple circuit in order to reduce the parasitic capacitance characteristic during high frequency operation. In addition, it must be easily tunable for use with conventional applications, such as programmable filters. These blocks are preferably configured as perfect differentiators for excellent PSRR (Power Supply Rejection), CMRR (Common Mode Rejection) and second order distortion cancellation. Also, these blocks preferably operate at 5 volts.

Conventionally, it has been difficult to tune mutual conductance. Conventional circuits are not suitable for high frequencies and do not meet the desirable criteria described above. In theory, high frequency filters implemented with transconductance, the most desirable building block for high frequency filters, were not useful due to bandwidth and / or dynamic range constraints.

It is difficult to realize a differential input or multiple input transconductance element with a conventional element.

[0005]

SUMMARY OF THE INVENTION It is therefore an object of the present invention to extend the achievable frequency range of operation of a tunable transconductance with a large dynamic range. It is a further object of the present invention to facilitate the setting of the pole frequency and the polar quality factor of a fourth-order filter structure based on these transconductance elements.
It is a further object of the present invention to provide a transconductance circuit element with minimal parasitic capacitance and output conductance. Another object of the present invention is to produce a transconductance element whose basic design can accommodate either single or multiple inputs. Furthermore, the subject of the present invention is low output admittance (high output impedance)
Is to design a multi-input transconductance that maintains

[0006]

SUMMARY OF THE INVENTION The present invention comprises a symmetrical parallel connection circuit that receives the positive and negative ends of an input voltage. Being a transconductance element, the input is a voltage level and the output is a current. Each symmetric circuit consists of a cascaded input stage and a gain stage. That is, the positive end of the input voltage is supplied to the input stage of the positive end circuit, where it is transformed into a current by the gain stage of the same circuit half. The negative end of the input voltage is provided to an input stage of a negative input voltage circuit, which in turn amplifies the signal power and provides an output current to each gain stage. The gain stages of the positive and negative halves of the circuit each include a bias transistor (current source load) and are modulated by the averaging and comparing circuit inputs to the bases of these two bias transistors. This averaging and comparing circuit stabilizes the common mode voltage level.

By providing a current between the input and gain stages of each of the positive and negative circuit halves making up the present invention, a new flexibility is obtained in the transconductance element of the present invention.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The components required to implement a bipolar tunable transconductance element are described. In the following description, numerous specific details such as voltage polarity, semiconductor type, and the like are set forth in order to provide a more thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known circuits have not been described in order not to unnecessarily obscure the present invention.

A transconductance element is an element that converts an input voltage into an output current. An ideal transconductance has infinite input and output impedance. Bipolar tunable transconductance elements are typically based on a Gilbert multiplier core.

A conventional Gilbert multiplier compliant transconductance element is illustrated in FIG. Input voltage Vi5
1 is provided to input terminals 46 and 47. The input terminal 46 is introduced to a positive input stage consisting essentially of elements enclosed in a box 90. Terminal 47 is connected to a negative input stage consisting essentially of an element surrounded by box 92.

The positive-end input stage 90 includes transistors Q1 and Q
2 and a resistor 70. The input terminal 46 is connected to the base 11 of the transistor Q1. The emitter 10 of the transistor Q1 is connected to one end of the resistor 70. The other end of the resistor 70 is connected to the node 48. The base 14 of transistor Q2 is connected to DC voltage 84. The emitter 13 of transistor Q2 is connected at node 49 to the collector 12 of transistor Q1.

The negative end input stage 92 comprises transistors Q5 and Q6 and a resistor 71. Negative input terminal 47 is connected to base 23 of transistor Q5. The emitter 22 of the transistor Q5 is connected to the emitter resistor 71. The other terminal of the resistor 71 is connected to the node 48. The base 26 of the transistor Q6 also has a DC voltage of 84
It is connected to the. The emitter 25 of transistor Q6 is connected at node 58 to the collector 24 of transistor Q5. The collector 27 of the transistor Q6 is connected to the supply voltage Vc.
Connected to c50.

The positive input stage 90 is connected to a positive gain stage consisting essentially of the elements in box 91. Positive end input stage 92 is connected to a negative end gain stage consisting essentially of the elements in box 93.

The positive gain stage 91 comprises transistors Q3 and Q4. The base of transistor Q3 15 is connected to the connecting section between the collector 12 of the emitter 13 and the transistor Q1 of the transistor Q2 at node 49. The emitter 16 of the transistor Q3 is connected to the node 60. The emitter 21 of the transistor Q4 is connected to the supply voltage Vcc5.
0, the collector 19 of transistor Q4 is connected at node 44 to the collector 18 of transistor Q3.

[0015] The base of the transistor Q7 is connected to the connecting section of the collector 24 of the emitter 25 and the transistor Q5 of transistor Q6 at node 58. Transistor Q
7 emitter 28 is connected to node 60. The negative end gain stage 93, operations one input is connected to the node 44, the other input (a connecting section of the collector 30 of the collector 31 and the transistor Q7 of the transistor Q8) is connected to the node 45 An amplifier 43 is included. Operational amplifier 4
3 output 29 is the bases 20 and 3 of transistors Q4 and Q8.
2 are connected. Emitter 33 of transistor Q8
Are connected to the supply voltage Vcc50. The output of the transconductance device shown in FIG. 1 is a current I0 54 at the respective collectors of transistors Q3 and Q7. Current I2 80 is the current at node 60 and current I1 81 is the current at node 48.

The transconductance circuit of Figure 1 are indicated by the symbol 111 in FIG. Input V i 51 is connected to the transconductance element 111 at the input 46 and 47. The transconductance element 111 supplies an output current I0 54 to a buffer ( level shifter ) 112. Ba
A buffer ( level shifter) 112 supplies an output voltage V0. This buffer is shown in detail in FIG. The base of the transistor T1 is connected to the A input (positive input) of the buffer 112. The emitter of transistor T1 is connected to ground via resistor R6. Buffer 1
Twelve B (negative input) is connected to the base of the transistor T2. The emitter of the transistor T2 is a resistor R7
Connected to ground via Voltage V0 is the voltage between the emitters of transistors T1 and T2.

The transconductance of the circuit shown in FIG. 1 is expressed by the following equation .

[0018]

(Equation 1)

When this transconductance is used as a building block in a high frequency filter, the following restrictions are imposed. That is, consideration of the dynamic range of the input determines the minimum value of the product RE × I1. On the other hand, the transconductance capacitor C Ru is loaded
Then, the following time constant occurs.

[0020]

(Equation 2)

This time constant is inversely proportional to the desired pole frequency,
Therefore, the following equation is obtained.

[0022]

(Equation 3)

The realization of high frequency filters is severely hindered by the following difficulties. 1) The product RE × I1 has already been determined. 2) C is to hold the predictability of the design, it can not be made arbitrarily small C so should be greater at least one size than model formation are difficult to parasitic floating Yu capacitance at the output node. 3) Increasing I2 is not a solution for two reasons. a) The power consumption becomes excessive. b) High current transistors are not available.

Most bipolar processes yield only lateral PNP transistors whose current is severely limited. Therefore, the increase flow of current I2 is required increase in the size of transistors, an increase of floating Yu capacitance associated to it. Furthermore, since the output conductance of a transistor is proportional to its collector current, increasing the current I2 makes it increasingly difficult to obtain an optimum transconductance. This problem is particularly acute in a new type of high frequency shallow junction bipolar process characterized by low transistor output resistance. Known circuit techniques for increasing the output resistance do not meet the requirements for the circuit, i.e., having a large dynamic range, the circuit being simple and operating at 5 volts.

Such a contradiction is resolved by the supply of current through the current sources 82 and 83 shown in FIG.
FIG. 4 further includes a level shift output buffer and a bias circuit 94. Common mode output voltage level is PN
It is stabilized by controlling the P current sources Q4 and Q8.

The bipolar transconductance element of the present invention shown in FIG. 4 includes a pair of input stages 90 and 92 connected between a supply voltage Vcc 50 and a current source 81, and a similar connection between the supply voltage Vcc 50 and a current source 80. And a pair of gain stages 91 and 93 connected in parallel between them. Input stages 90 and 92 are cascaded with gain stages 91 and 93, respectively, corresponding to the positive and negative ends of differential input voltage Vi 51, respectively. These positive and negative halves are symmetric.

The input stages 90 and 92 include a DC voltage supply VDC 84
Biased by Similarly, gain stages 91 and 9
3 is biased by a bias circuit 94. The positive-end gain stage 91 and the negative-end gain stage 93 are connected to the output terminal 52, respectively.
And 53. An output current I0 54 extends across the output terminals 52 and 53. The output current I054 is proportional to the differential voltage input Vi51 between the input terminal 46 on the positive input stage 90 and the input terminal 47 on the negative input stage 92.

Both the positive-end input stage 90 and the negative-end input stage 92 comprise a transistor and a resistor connected in series. The input stage 90 has a bias transistor Q2, the collector 15 of which is connected to the supply voltage Vcc 50,
The base 14 is connected to a DC voltage source 84 and the emitter 13
Is connected to the collector 12 of the transistor Q1.
Transistor Q2 applies a DC bias voltage to transistor Q3.
And performs log pre-compensation to linearize the overall function of the multiplier. Transistor Q1, the active transistor, receives at its base 11 a positive differential input of Vi51. Emitter 10 of active transistor Q1
Are connected in series with the resistor 70. The other end of the resistor 70 is connected to a current source 81 to ground. The bias transistor Q2 of the positive input stage 90 is connected to a reference voltage 84. The collector 12 of the active transistor Q1
The emitter 13 of the bias transistor Q2 of the positive input stage 90 connected to the input stage 90 functions as the output node 57 of the input stage 90. It is at this node on the input stage 90 that the gain stage 91 is connected in series. The circuit of the input stage 92 is symmetrical in all aspects to the circuit described above.

The voltage Vi is applied to the bases of the transistors Q1 and Q5.
When applied between each other :

[0030]

(Equation 4)

As a result, the bases of the transistors Q3 and Q7
Voltage difference therebetween can be represented by the following formula △ V is generated.

[0032]

(Equation 5)

This voltage difference ΔV results in a current difference ΔI between the transistors Q3 and Q7 which can be expressed by the following equation.

[0034]

(Equation 6)

The current difference with a fixed current I2 / 2 △ I / 2 is
One terminal enters the circuit and the other terminal exits the circuit. Positive end input stage 90 is cascaded with positive end gain stage 91. The negative end input stage 92 is similarly cascaded to the negative end gain stage 93. The gain stages 91 and 93 are symmetric, as are the input stages 90 and 92.

The gain stage 91 includes a bias transistor Q connected in series between the voltage source Vcc 50 and the current source 80.
4 and an active transistor Q3. The emitter 16 of the active transistor Q3 is connected to a current source 80. The base 17 of the gain stage active transistor Q3 functions as the input terminal 55 for the gain stage 91. That is, the output terminal 57 of the input stage 90 is connected to the input terminal 55 (
It is connected to the base 17) of the active transistor Q3. Furthermore the voltage supply source Vcc to the base 17 of the active transistor Q3
A current source 82 connected to 50 is connected. Current source 82 supplies current to the connecting section 55 of the input stage 90 and gain stage 91. Bias transistor Q in gain stage 91
The base of 4 is connected to a bias circuit 94 ( which stabilizes the common mode voltage of the transconductance element ) . The emitter 21 of the bias transistor Q4 is connected to a voltage supply source Vcc50. The collector 18 of the bias transistor Q4 of the gain stage 91 is connected to the collector 18 of the active transistor Q3 of the same gain stage.
This collector-collector connection functions as the current output terminal 52 for the gain stage 91. The circuit of the gain stage 93 is symmetrical in all aspects to the circuit described above.

The operation of gain stage 91 depends on the voltage difference between nodes 57 and 58. When the output voltage 57 from the input stage 90 drops (and at the same time the voltage at node 58 rises), the current flowing into the collector 18 of the active transistor Q3 of that gain stage also drops. Bias transistor Q4 of gain stage 91 functions as a constant current source. Therefore, when the collector current of the active transistor Q3 is reduced, the surplus constant current is shunted to the output terminal 52 of the gain stage 91. Conversely, the base 17 of the active transistor Q3 of the gain stage 91
When the voltage at (the input terminal of the gain stage) is increased (and, if the voltage at the base 29 drops), the collector current of the active transistor Q3 rises, to pull out current from the output terminal 52 of the gain stage 91 . The function of the negative end gain stage 93 is the same as described above.

The bases of bias transistors Q 4 and Q 8 in gain stages 91 and 93 are connected to bias circuit 94. The output 59 of the bias circuit 94 is ( positive input 4
That accept a reference voltage 85 in 2) is the output from the comparator 86, the reference voltage 85 provides a quiescent bias voltage at the base of the bias transistor. Inverting input 41 of the comparator 86 is the average value of the voltage at the output terminal of the positive and Ftan gain stage (hence DC value only) that accept the. Output terminals 52 and 5
3 is connected to the bases 36 and 39 of the transistors Q9 and Q10 in the bias circuit 94. Transistor Q9
And the collectors 37 and 40 of Q10 are connected to a supply voltage source Vcc50. Emitter 35 of transistors Q9 and Q10
And 38 are connected to ground voltage via resistors 72 and 73.

The degree of freedom of the circuit is added by the collective current IDC from the current sources 82 and 83. Although the input dynamic range is determined by the product RE × I1, τ and ω0 in this case are obtained by the following equations.

[0040]

(Equation 7)

(Equation 8)

A model of the circuit shown in FIG. 4 is shown in FIG. Input voltage V i is connected to the transconductance element 113 at the input 46 and 47. The output Io 54 of the transconductance element 113 is a single gain buffer.
( Level shifter ) 114. Level shifter 114 provides output V0.

As shown in FIG. 6, two or more new transconductances can be easily incorporated into one circuit. The circuit of FIG. 6 adds additional transistors Q11 and Q12 and emitter resistors 76 and 77. A second input voltage 79 is applied to the positive input 62 and the negative input 63.
Is supplied. (The first input voltage to inputs 46 and 47 is also provided.) Positive terminal 62 is connected to base 65 of transistor Q11. The collector 66 of transistor Q11 is connected at node 57 to the collector 12 of transistor Q1. The emitter 64 of transistor Q11 is connected to node 78 via resistor 76.

The negative input 63 is connected to the base 68 of the transistor Q12. The collector 69 of transistor Q12 is connected at node 58 to the collector 24 of transistor Q5. The emitter 67 of transistor Q12 is connected to node 78 via resistor 77. Current I18
5 is supplied from node 78.

The gain of this double input is as follows.

[0045]

(Equation 9) here:

[0046]

(Equation 10)

[Equation 11]

If we choose IDC * = IDC + I1, Equation 6 becomes:

[0048]

(Equation 12)

This equation is exactly the same as that obtained when two transconductances (shown in FIG. 4) are connected in parallel. However, the significant savings in power consumption realized by the structure of FIG. 6 are evident, as is the number of transistors and the area they occupy (especially PNP transistors are large). Further, the output admittance (G
0 + C0) is independent of the number of inputs. In contrast, the output admittance of two single-input transconductances simply in parallel will be doubled.

A model of the multiple input transconductance element of FIG. 6 is shown in FIG. Transconductance element 1
15 that accept the double input. That is, the input voltage V1 51 at inputs 46 and 47 and the input voltage V1 at inputs 62 and 63
279. These voltages are connected to equivalent resistors RE1 and RE2, respectively. Dual input transconductance element 115 provides an output to buffer ( level shifter ) 114. Level shifter 114 provides output V0.

The advantage of this novel approach to achieving a fully differential state variable filter structure is shown in FIG.
0 is shown. The circuit of FIG. 10 uses the double differential input / single differential output transconductance shown in FIG. Vi 51 is connected to a first transconductance element 88 at inputs 46 and 47. The outputs at nodes 95 and 96 of transconductance element 88 are buffered ( level
(Shifter ) 118. The output of level shifter 118 is provided as an input to transconductance element 89. Node 95 is also connected to ground via capacitor C1, and node 96 is connected to ground via equivalent capacitor C1. Transconductance 89
Outputs at nodes 97 and 98 are buffers ( level shifters )
119 is connected. Output at node 120 and 12 7 of the level shifter 119 is connected to respective second inputs of the transconductance elements 88 and 89 in the feedback loop. Node 97 is also connected to ground via capacitor C2, and node 98 is connected to ground via equivalent capacitor C2. Voltage VLP is provided between nodes 120 and 121.

FIG. 10 illustrates an advance over the technique of FIGS. A traditional differential input single-ended output fourth-order transconductance-C configuration having single-ended Vi and VLP is shown in FIG. Input Vi is connected to the positive input of transconductance element 100. The output of transconductance element 100 at node 102 is a capacitor C1
To ground and through a level shifter 116 to a respective negative input of the transconductance element 100 in a feedback loop. Voltage VLP is provided at node 99.

FIG. 9 shows a conventional fully differential configuration. The input voltage Vi is connected to the transconductance element 100 at inputs 46 and 47. The output of element 100 is provided at nodes 103 and 104. Node 103 is connected to ground via capacitor C1, and node 104 is connected to ground via capacitor C1. Node 103
And 104 are also connected as inputs to the transconductance element 101 via the level shifter 122. The output of transconductance element 101 is provided at nodes 105 and 106 which are connected to ground via capacitor C2.
Further, nodes 105 and 106 are provided as inputs to the transconductance element 107 via the level shifter 123. Outputs at nodes 109 and 110 of transconductance element 107 are connected to level shifter 123 in a feedback loop.
Connected to the input. The output of the level shifter 123 is at nodes 124 and 125 at the transconductance element 1
08 is connected to the input. Nodes 124 and 125 also provide the output voltage VLP. Transconductance element 1
The output of 08 is connected to nodes 103 and 104 in a feedback loop.

The transfer function of the filter of FIG. 10 is as shown by the following equation.

[0055]

(Equation 13)

In the circuit of FIG. 10, the pole frequency and polarity can be expressed as a function of capacitor, resistance and current as follows:

[0057]

[Equation 14]

(Equation 15)

C1 = C2 = C, RE1 = RE2 = RE, ie, as a result of the optimal symmetry and the best possible component matching, if the capacitors and resistors are all identical, the pole frequency Q is It is represented by an equation.

[0059]

(Equation 16)

[Equation 17]

(Note that IDC and IDC2 can also be negative if desired.)

In conclusion, the supplied currents IDC1 and ID
By proper selection of C2, any pole frequency and polarity quality factor can be achieved without rationalization of the capacitors. This is another obvious advantage of the novel approach of the present invention over conventional quaternary structures. Here, it is assumed that the area occupied by the multiplier transistors is scaled in proportion to the respective currents, as well as the cancellation of parasitic effects due to the regular multiplier core, optimal linear positive and small base resistance. Please note.

As previously described, a bipolar tunable transconductance element and its use in a fully differential state-variable structure is disclosed.

[0063]

The present invention is an improvement over prior designs in that the bandwidth problem associated with a bipolar tunable transconductance element can be solved. The present invention allows more freedom to set the pole frequency and polar quality factor of the transconductance-C filter element by adding an additional current source to the transconductance building block. As a result of the new design, tunable transconductance elements can be more easily manufactured. The present invention also discloses a circuit for implementing the novel idea of a multi-input transconductance element.

[Brief description of the drawings]

FIG. 1 is an embodiment of a conventional transconductance element.

FIG. 2 is a model of the circuit of FIG. 1;

FIG. 3 is a circuit diagram of a buffer / level shifter.

FIG. 4 is a circuit diagram of an embodiment of the present invention.

FIG. 5 is a model of the circuit of FIG. 4;

FIG. 6 is another embodiment of the present invention for a multiple input transconductance device.

FIG. 7 is a model of the circuit of FIG. 6;

FIG. 8 is a circuit diagram of a state variable fourth-order configuration having a differential input and single-ended output mutual conductance.

FIG. 9 is a fully differential equivalent circuit diagram of FIG. 8 configured with a conventional differential input / differential output transconductance.

FIG. 10 is an embodiment of the present invention for a quaternary state variable configuration of differential input and differential output.

[Explanation of symbols]

 29: output 41: inverting input 42: positive input 43: operational amplifier 44, 45: nodes 82, 83: current source 84: reference voltage 90: positive terminal input stage 91: positive terminal gain stage 92: negative terminal input stage 93: Negative gain stage

Continuation of front page (56) References JP-A-55-52615 (JP, A) JP-A-62-160805 (JP, A) JP-A-63-158903 (JP, A) JP-A-2-27806 (JP) US Pat. No. 3,89,958 (US, A) US Pat. No. 3,899,959 (US, A) US Pat. No. 4,374,335 (US, A) US Pat. Patent 4823092 (US, A) US Patent 4881043 (US, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03F 1/00-1/56 H03F 3/00-3/45 H03F 3 / 50-3/52 H03H 11/00-11/54 PCI (DIALOG) WPI (DIALOG)

Claims (2)

(57) [Claims] 1. A circuit for converting a voltage to a current, said circuit being provided between a first current source (81) to ground and a supply voltage (Vcc).
And the first and second input stages (90, 9
2) wherein said first input stage (90) is to be transformed
An input coupled to one terminal for transmitting the voltage;
The second input stage (92) carries the voltage to be converted.
An input coupled to the other input terminal ; each of said first and second input stages (90; 92) has an
Series connection of the active transistor (Q1; Q5) and the resistor (70; 71)
Includes bias transistors (Q2; Q6) connected to
The vias of the first and second input stages (90; 92).
Transistors (Q2; Q6) are connected to their base and ground.
Biased by a first voltage source (84) between
Between the second current source (80) to earth and the supply voltage (Vcc).
And the first and second gain stages (91, 9
3) wherein said first and second gain stages (91, 93)
Each has a series connected bias transistor (Q
4, Q8) and active transistors (Q3, Q7)
Bias transistors (Q4, Q8) are
Is biased Te; said first gain stage (91), the said first gain stage (91)
A base of an active transistor (Q3) and the first input stage (90);
First connection point of the collector of the active transistor (Q1)
At (55) the second input stage (90) is coupled to the second input stage (90).
The gain stage (93) of the second gain stage (93)
The base of the transistor (Q7) and the function of the second input stage (92).
To the second connection point (56) of the collector of the driving transistor (Q5).
And a third current source (8) for supplying a current to the first connection point (55).
2) and a fourth power supply for supplying a current to the second connection point (56).
And a third current source (82) and a third current source (83).
4 is connected to the supply voltage (Vcc).
The comparator (86) has a voltage level from the second voltage source (85);
As a first input, and said first gain stage (91)
Voltage appearing at the collector of the active transistor (Q3) and
The collector of the active transistor (Q7) of the second gain stage (93)
The average voltage of the voltage appearing at the
Circuitry for converting cormorants are configured, a voltage, wherein the current. 2. A circuit for converting a voltage into a current, comprising a first and a second input stage (90, 92),
The power stage (90) has one end carrying said voltage to be converted.
A second input stage (92) having an input coupled to the
Coupled to the other terminal carrying said voltage to be converted
And it has an input; said first input stage (90), an active Trang connected in series
A pair of resistors each including a resistor (Q1, Q11) and a resistor (70, 76).
A pair of branches connected in parallel with each other;
Bias transistors coupled in series to a pair of branches
(Q2), and the second input stage (92) is connected in series.
Active transistors (Q5, Q12) and resistors (71, 77) connected to
Are connected in parallel with each other.
And a pair of branches connected in series to the pair of branches.
A bias transistor (Q6).
The bias transistor (Q2) of the first input stage and the bias transistor (Q2);
A series connection with one branch (Q1,70) of the first input stage,
And the bias transistor of the second input stage
(Q6) and one branch (Q5, 71) of the second input stage in series
The connections are respectively connected to the supply voltage (Vcc) and the first current source (8
1) and said first input stage
A bias transistor (Q2) and the other of the first input stage
A series connection with the branch (Q11, 76) of
The bias transistor (Q6) of the input stage and the second
The series connection with the other branch of the input stage (Q12, 77)
Respectively coupled between the supply voltage (Vcc) and the second current source (85)
The bias transistors of the first and second input stages.
Stars (Q2, Q6) are the first between the bases and ground.
Between the third current source (80) to ground and the supply voltage (Vcc).
And the first and second gain stages (91, 9
3) wherein said first and second gain stages (91, 93)
Each has a series connected bias transistor (Q
4, Q8) and active transistors (Q3, Q7)
Bias transistors (Q4, Q8) are
Is biased Te; said first gain stage (91), the said first gain stage (91)
A base of an active transistor (Q3) and the first input stage (90);
The active transistors (Q1,
At the first connection point (55) of the collector of Q11), the first input
Coupled to the power stage (90), the second gain stage (93)
The base of the active transistor (Q7) of the second gain stage (93);
The second input stage (92) in one and the other branch thereof;
The second connection point (5) of the collectors of the active transistors (Q5, Q12)
6) coupled to the second input stage (92) ; a fourth current source (8) for supplying current to the first connection point (55).
2) and a fifth power supply for supplying a current to the second connection point (56).
And a fourth current source (82) and a fourth current source (83).
5 is connected to the supply voltage (Vcc).
The comparator (86) has a voltage level from the second voltage source (85);
As a first input, and said first gain stage (91)
Voltage appearing at the collector of the active transistor (Q3) and
The collector of the active transistor (Q7) of the second gain stage (93)
The average voltage of the voltage that appears at the second input
Circuitry for converting cormorants are configured, a voltage, wherein the current.