JP3210489B2 - Silicon wafer and method for evaluating withstand voltage of oxide film - Google Patents

Silicon wafer and method for evaluating withstand voltage of oxide film

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Publication number
JP3210489B2
JP3210489B2 JP15796593A JP15796593A JP3210489B2 JP 3210489 B2 JP3210489 B2 JP 3210489B2 JP 15796593 A JP15796593 A JP 15796593A JP 15796593 A JP15796593 A JP 15796593A JP 3210489 B2 JP3210489 B2 JP 3210489B2
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JP
Japan
Prior art keywords
silicon wafer
oxide film
laser
density
withstand voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP15796593A
Other languages
Japanese (ja)
Other versions
JPH06349923A (en
Inventor
久実 元浦
訓之 植村
雅史 西村
光雄 河野
Original Assignee
コマツ電子金属株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Priority to JP15796593A priority Critical patent/JP3210489B2/en
Publication of JPH06349923A publication Critical patent/JPH06349923A/en
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Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】この発明はシリコンウェーハの酸
化膜耐圧に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oxide film withstand voltage of a silicon wafer.

【0002】[0002]

【従来の技術】シリコンウェーハの表層には各種のデバ
イスが組み込まれるが、各デバイスが電気的に良好に作
動するためには、その酸化膜耐圧の値が基準値を越えて
いる必要がある。しかるに従来よりデバイスの酸化膜耐
圧に影響を及ぼす因子については必ずしも十分に解明さ
れておらず、このため従来は実際に酸化膜耐圧測定用の
MOSキャパシターを作成して、実際に酸化膜耐圧を測
定していた。
2. Description of the Related Art Various devices are incorporated in a surface layer of a silicon wafer. In order for each device to operate electrically well, it is necessary that the withstand voltage of an oxide film exceeds a reference value. However, the factors that affect the oxide film breakdown voltage of devices have not always been sufficiently elucidated. Therefore, conventionally, a MOS capacitor for actually measuring the oxide film breakdown voltage was actually created, and the oxide film breakdown voltage was actually measured. Was.

【0003】[0003]

【発明が解決しようとする課題】しかるに上記従来の酸
化膜耐圧の評価方法は、実際に酸化膜耐圧測定用のMO
Sキャパシターを作成して酸化膜耐圧を測定するもので
あるから、長時間を要するという問題点がある。すなわ
ち素子作成から酸化膜耐圧測定までに要する時間を単純
に加算しても20時間程度を要し、実際には各種の準備
作業等があるために1週間程度を要していた。したがっ
て本発明は、簡易且つ迅速に酸化膜耐圧を評価すること
ができ、したがって評価に要するコストが著しく低廉な
シリコンウェーハの酸化膜耐圧の評価方法を提供し、併
せて酸化膜耐圧が十分に良好なシリコンウェーハを提供
することを目的とする。
However, the above-mentioned conventional method for evaluating the withstand voltage of an oxide film is actually a method for measuring the withstand voltage of an oxide film.
Since an S capacitor is prepared and the breakdown voltage of an oxide film is measured, there is a problem that it takes a long time. That is, it takes about 20 hours even if the time required from the device preparation to the measurement of the oxide film breakdown voltage is simply added, and in practice, it takes about one week due to various preparations and the like. Therefore, the present invention provides an evaluation method of an oxide film withstand voltage of a silicon wafer, which can easily and quickly evaluate an oxide film withstand voltage, and therefore the cost required for the evaluation is remarkably low. It is intended to provide a simple silicon wafer.

【0004】[0004]

【課題を解決するための手段】本発明者は上記目的を達
成するために研究を重ね、シリコンウェーハにレーザー
を照射したときの散乱光に着目し、この散乱光を生じさ
せるレーザー散乱体の密度が酸化膜耐圧に強い因果関係
を与えており、すなわちレーザー散乱体がシリコンウェ
ーハの表層部に多く存在すると、酸化膜耐圧が劣化する
ことを見出し、こうして本発明を完成するに至った。す
なわち本発明は、シリコンウェーハ表層のレーザー散乱
体密度に基づいて、前記シリコンウェーハの酸化膜耐圧
良品率又は不良品率を評価することを特徴とするシリコ
ンウェーハの酸化膜耐圧の評価方法であり、また、表層
のレーザー散乱体密度が5×105/cm3以下であるこ
とを特徴とするシリコンウェーハである。
Means for Solving the Problems The present inventor has repeated studies to achieve the above-mentioned object, paying attention to scattered light when a silicon wafer is irradiated with a laser, and the density of a laser scatterer that generates the scattered light. Have a strong causal relationship with the oxide film breakdown voltage, that is, it has been found that the oxide film breakdown voltage is degraded when a large number of laser scatterers are present in the surface layer of the silicon wafer, thus completing the present invention. That is, the present invention is a method for evaluating the oxide film breakdown voltage of a silicon wafer, comprising evaluating the oxide film breakdown voltage non-defective product rate or defective product rate of the silicon wafer based on the laser scatterer density of the silicon wafer surface layer, The silicon wafer is characterized in that the surface has a laser scatterer density of 5 × 10 5 / cm 3 or less.

【0005】[0005]

【実施例】以下に本発明の実施例を説明する。引上げ法
すなわちチョクラルスキー法によって単結晶シリコンイ
ンゴットを製造し、これにスライス・ラップ・面取り・
化学研磨の各工程を施してシリコンウェーハの試料とし
た。試料の諸元は、直径6インチ、結晶軸<100>、
P型、ボロンドープ、抵抗率10〜20Ωcm、酸素濃
度12〜15×1017atoms/cm3である。この
試料に各種の熱処理を施してレーザー散乱体の密度を変
化させ、しかる後ウェーハ表層部のレーザー散乱体の密
度を測定した。図1はレーザー散乱体の測定装置を示し
ている。シリコンウェーハ1の表面に向けてレーザー発
射装置2より波長1.3μmのレーザー光が垂直に照射
され、シリコンウェーハの表面にこのビームをフォーカ
スして、ウェーハ表面上の任意に定めた複数のポイント
を、ウェーハがスライドすることで走査する。ビームが
欠陥に当たるとわずかな位相のずれを生じるが、このず
れを検出することで欠陥を検出する。即ち、図1に示さ
れるように、この装置では、レーザー発射装置2から発
せられたレーザー光をプリズムによって位相が異なる2
本の偏光ビームに分離して、ウェーハの一方から入射さ
せる。そして、その内の一本のビームが欠陥を横切ると
位相シフトが生じ、もう一つのビームとの間に位相差が
生じることとなるので、この位相差をウェーハ透過後に
アナライザーで検出することにより欠陥の検出を行うの
である。
Embodiments of the present invention will be described below. A single crystal silicon ingot is manufactured by the pulling method, that is, the Czochralski method, and sliced, wrapped, chamfered,
Each step of chemical polishing was performed to obtain a silicon wafer sample. The specifications of the sample were 6 inches in diameter, crystal axis <100>,
P-type, boron-doped, resistivity 10 to 20 Ωcm, oxygen concentration 12 to 15 × 10 17 atoms / cm 3 . The sample was subjected to various heat treatments to change the density of the laser scatterers, and thereafter, the density of the laser scatterers on the wafer surface layer was measured. FIG. 1 shows a laser scatterer measuring device. A laser beam having a wavelength of 1.3 μm is vertically emitted from the laser emitting device 2 toward the surface of the silicon wafer 1, and this beam is focused on the surface of the silicon wafer to arbitrarily define a plurality of points on the wafer surface. , The wafer is scanned by sliding. When the beam hits a defect, a slight phase shift occurs. By detecting this shift, the defect is detected. That is, as shown in FIG.
In this device, the laser
The phase of the applied laser beam differs depending on the prism 2
Split into two polarized beams and incident from one side of the wafer.
Let And when one of them crosses the defect
A phase shift occurs, causing a phase difference with another beam
This phase difference after passing through the wafer.
Detecting defects by detecting with an analyzer
It is.

【0006】図2はシリコンウェーハ1の表面近傍(0
〜3μm)でのレーザー散乱体の密度と酸化膜耐圧が3
MV/cm以上、8MV/cm以下のBモード不良品率
との関係を示す。同図より明らかなように、レーザー散
乱体密度とBモード不良品率との間には著しい相関関係
があり、すなわちレーザー散乱体密度が増加するとBモ
ード不良品率が増加することが良く理解される。また図
3はレーザー散乱体の密度と酸化膜耐圧が8MV/cm
以上のCモード良品率との関係を示し、同図より明らか
なように、レーザー散乱体密度が増加するとCモード良
品率が減少することが理解される。
FIG. 2 shows the vicinity (0) of the surface of the silicon wafer 1.
(3 μm) and the oxide withstand voltage is 3
The relationship with the B mode defective product ratio of MV / cm or more and 8 MV / cm or less is shown. As is clear from the figure, there is a remarkable correlation between the laser scatterer density and the B-mode reject rate, that is, it is well understood that the B-mode reject rate increases as the laser scatterer density increases. You. FIG. 3 shows that the density of the laser scatterer and the withstand voltage of the oxide film are 8 MV / cm.
The relationship with the above C-mode non-defective rate is shown, and as is apparent from the figure, it is understood that the C-mode non-defective rate decreases as the laser scatterer density increases.

【0007】これらの図2及び図3自体は、図1のレー
ザー散乱体測定装置によってレーザー散乱体密度を測定
し、他方、実際に酸化膜耐圧測定用のMOSキャパシタ
ーを作成して酸化膜耐圧を測定した結果得られる図であ
るが、これらの図をひとたび得ておくことにより、シリ
コンウェーハの酸化膜耐圧を迅速に評価することができ
る。すなわち図1のレーザー散乱体測定装置によるレー
ザー散乱体密度の測定は、たとえば本装置で1ポイント
当たり測定できる領域は、128×450μmであるか
ら、ウェーハ面内の代表値とするためには少なくとも3
0ポイント以上は必要となってくるが、それでも要する
時間は1時間程度ですむ。レーザーの走査方向はウェー
ハの深さ方向と、水平方向の2通りがあるが、本実施例
では、表面近傍(深さ0〜3μm)の値をとるため走査
を水平方向とし、ウェーハ中の5個所の位置で、それぞ
れ6ポイント、計30ポイントのレーザー散乱体を測定
し、ウェーハ面内の代表値とした。このようにして、あ
とは例えば図3を用いることにより、そのシリコンウェ
ーハの酸化膜耐圧良品率を直ちに評価することができ、
結局従来の直接的な測定によって酸化膜耐圧を求めてい
たときに比較して、著しく迅速に酸化膜耐圧を評価する
ことができる。また酸化膜耐圧良品率の仕様として例え
ば95%以上が要求されるときには、図3よりレーザー
散乱体密度としては約5×105/cm3以下である必要
があることが解るから、個々のシリコンウェーハ表層の
レーザー散乱体密度を測定し、この測定値が5×105
/cm3以下であるか否かによって当該シリコンウェー
ハの採否を容易且つ迅速に決定することができる。
In FIGS. 2 and 3, the density of the laser scatterer is measured by the laser scatterer measuring apparatus of FIG. 1, and on the other hand, a MOS capacitor for actually measuring the oxide film withstand voltage is formed to reduce the oxide film withstand voltage. These figures are obtained as a result of measurement, but once these figures are obtained, the oxide film breakdown voltage of the silicon wafer can be quickly evaluated. That is, in the measurement of the laser scatterer density by the laser scatterer measuring apparatus of FIG. 1, for example, the area that can be measured per point by the present apparatus is 128 × 450 μm, so that at least 3
You need more than 0 points, but it still takes about an hour. There are two types of laser scanning directions: the depth direction of the wafer and the horizontal direction. In this embodiment, the scanning is performed in the horizontal direction to take a value near the surface (depth of 0 to 3 μm). At each position, laser scatterers were measured at 6 points, respectively, for a total of 30 points, and were set as representative values in the wafer plane. In this way, after that, for example, by using FIG. 3, the oxide film breakdown voltage non-defective rate of the silicon wafer can be immediately evaluated,
As a result, the oxide film breakdown voltage can be remarkably quickly evaluated as compared with the case where the oxide film breakdown voltage is obtained by the conventional direct measurement. Further, when the specification of the oxide film breakdown voltage non-defective rate is required to be, for example, 95% or more, it is understood from FIG. 3 that the laser scatterer density needs to be about 5 × 10 5 / cm 3 or less. The laser scatterer density of the wafer surface layer was measured, and the measured value was 5 × 10 5
/ Cm 3 or less, it is possible to easily and quickly determine whether or not to use the silicon wafer.

【0008】[0008]

【発明の効果】本発明方法は、シリコンウェーハ表層の
レーザー散乱体密度に基づいてシリコンウェーハの酸化
膜耐圧良品率又は不良品率を評価するものであるから、
個々のシリコンウェーハの酸化膜耐圧を容易且つ迅速に
評価することができる。また本発明は表層のレーザー散
乱体密度が5×105/cm3以下のシリコンウェーハで
あるから、その酸化膜耐圧良品率は約95%以上と著し
く良好なシリコンウェーハである。
The method of the present invention evaluates the oxide film breakdown voltage non-defective product rate or defective product rate of a silicon wafer based on the laser scatterer density of the surface layer of the silicon wafer.
The oxide film breakdown voltage of each silicon wafer can be easily and quickly evaluated. Further, the present invention is a silicon wafer having a surface layer having a laser scatterer density of 5 × 10 5 / cm 3 or less, and thus has a remarkably good silicon film withstand voltage ratio of about 95% or more.

【図面の簡単な説明】[Brief description of the drawings]

【図1】レーザー散乱体密度の測定手法を示す図FIG. 1 is a diagram showing a method for measuring a laser scatterer density.

【図2】レーザー散乱体密度とBモード不良品率との関
係を示す図
FIG. 2 is a diagram showing a relationship between laser scatterer density and B-mode defective product rate.

【図3】同じくCモード良品率との関係を示す図FIG. 3 is a diagram showing the relationship with the non-defective rate in the C mode.

【符号の説明】[Explanation of symbols]

1…シリコンウェーハ 2…レーザー発射装置 1. Silicon wafer 2. Laser emitting device

───────────────────────────────────────────────────── フロントページの続き (72)発明者 河野 光雄 神奈川県平塚市四之宮2612番地 コマツ 電子金属株式会社内 (56)参考文献 特開 平6−242036(JP,A) 特開 平6−112292(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 21/66 G01N 21/00 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Mitsuo Kono 2612 Yonomiya, Hiratsuka-shi, Kanagawa Prefecture Komatsu Electronic Metals Co., Ltd. (56) References JP-A-6-242036 (JP, A) JP-A-6-112292 ( JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 21/66 G01N 21/00

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 ビームが欠陥に当たると生じるわずかな
位相のずれを検出することで欠陥を検出することによ
り、シリコンウェーハ表層のレーザー散乱体密度を測定
し、これに基づいて、前記シリコンウェーハの酸化膜耐
圧良品率又は不良品率を評価することを特徴とするシリ
コンウェーハの酸化膜耐圧の評価方法。
1. The small amount of light that occurs when a beam hits a defect.
By detecting defects by detecting the phase shift
And measures the laser scatterer density on the surface of the silicon wafer
And evaluating the oxide film breakdown voltage non-defective product rate or defective product rate of the silicon wafer based on the evaluation result.
【請求項2】 請求項1記載の方法により表層のレーザ
ー散乱体密度が5×10/cm3以下であるか否かに
よってシリコンウェーハの採否を決定する方法
Wherein whether crab surface of the laser scattering body density by the method of claim 1, wherein is 5 × 10 5 / cm 3 or less
Therefore, a method of determining whether to adopt a silicon wafer .
【請求項3】 ビームが欠陥に当たると生じるわずかな
位相のずれを検出することで欠陥を検出することによ
り、シリコンウェーハ表層のレーザー散乱体密度を測定
し、当該散乱体密度が5×10 /cm 3 以下であると
されたシリコンウェーハ。
3. The small amount of light produced when the beam hits a defect.
By detecting defects by detecting the phase shift
And measures the laser scatterer density on the surface of the silicon wafer
When the scatterer density is 5 × 10 5 / cm 3 or less
Silicon wafer.
JP15796593A 1993-06-02 1993-06-02 Silicon wafer and method for evaluating withstand voltage of oxide film Expired - Lifetime JP3210489B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15796593A JP3210489B2 (en) 1993-06-02 1993-06-02 Silicon wafer and method for evaluating withstand voltage of oxide film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15796593A JP3210489B2 (en) 1993-06-02 1993-06-02 Silicon wafer and method for evaluating withstand voltage of oxide film

Publications (2)

Publication Number Publication Date
JPH06349923A JPH06349923A (en) 1994-12-22
JP3210489B2 true JP3210489B2 (en) 2001-09-17

Family

ID=15661320

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP3210489B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3274246B2 (en) * 1993-08-23 2002-04-15 コマツ電子金属株式会社 Manufacturing method of epitaxial wafer

Also Published As

Publication number Publication date
JPH06349923A (en) 1994-12-22

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