JP3208160B2 - Memory management method in computer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage management system for a computer.

[0002]

2. Description of the Related Art Conventionally, a virtual storage system has been generally used as a storage management system in a computer. The virtual storage system is a system in which a lacking portion is allocated to an auxiliary storage device such as a magnetic disk as a secondary storage device and used, assuming that all logical spaces are available.

For example, the logical address space that can be handled by a 32-bit CPU is 4 Gbytes, but the capacity of a main memory device usually mounted is considerably smaller than that, and is at most several Mbytes.

FIG. 4 is a block diagram showing a general hardware configuration of a conventional computer.

In FIG. 4, reference numeral 2 denotes a CPU (central processing unit) for controlling the entire system, and 4 denotes a ROM (read only memory) storing a program for the control.
And a main memory comprising a RAM (random access memory) which functions as a working memory for storing data, 6 is an auxiliary memory such as a floppy disk or a hard disk, 8 is a secondary memory interface,
Is an address conversion unit (MMU), 12 is a physical address bus, 14 is a data bus, and 16 is a cache memory (buffer memory).

In a computer having such a configuration,
A general segment paging method used in the virtual storage method will be described with reference to the conceptual diagram of FIG.

In FIG. 5, reference numeral 50 denotes a status (4 bits) transmitted from the CPU 2 to the address conversion unit (MMU) 10 when an address is designated;
2 is a logical address (32 bits) transmitted to the address translation unit (MMU) 10; 52a is a segment;
52b is a page and 52c is an offset.

Reference numerals 54, 56 and 58 denote address translation units (MM
U) Referenced by 10, 54 is a task register, 5
6 is a segment table, and 58 is a page mapping table.

The address translation unit (MMU) 10 refers to the task register 54 based on the status 50 and specifies the head of the segment table 56 to be accessed.
Then, an address to be accessed is determined by the segment 52a of the logical address 52. That is, the status 50 specifies the attribute of the task, and the segment 52a specifies the task itself.

[0010] Based on the value of the segment table 56,
The start address of the page mapping table 58 to be accessed next is specified. This shows the first page of the task. It is assumed that the task is divided into pages of 8 Kbytes and managed. The page 52b in the logical address 52 specifies which page of the task is to be accessed. Then, the actual physical address 60 is determined based on the lower 16 bits of the page mapping table 58 and the offset 52c of the logical address 52, and sent out from the address conversion unit (MMU) 10 to the physical address bus 12.

Here, if the physical address 60 does not exist in the main storage device 4, the CPU 2 executes an exception handling routine, and stores the auxiliary storage in advance by an OS (operating system: basic program). The data of the corresponding page is read from the swap area on the device 6 to the main storage device 4 via the secondary memory interface 8 and the data bus 14, and further read from the cache memory 1.
6 to execute the processing.

The above is the operation of the segment paging system in the virtual storage system. The auxiliary storage device 6 is used as a virtual storage space, and the storage capacity of the main storage device 4 is apparently expanded.

The cache memory 16 stores the CPU 2
To perform high-speed operation.

[0014]

However, the frequent use of the auxiliary storage device 6 as a virtual storage space for the main storage device 4 is due to the slow operation speed of the auxiliary storage device 6, resulting in a significant reduction in processing capacity. Will be invited.

The present invention has been made in view of such circumstances, and aims to increase the apparent storage capacity of a main storage device while increasing the processing capacity. Aim.

[0016]

SUMMARY OF THE INVENTION A storage management method in a computer according to the present invention has a high write / read speed.
Main storage device with small storage capacity and write / read speed
The auxiliary storage device, which is slow and has a large storage capacity, and the CPU
Set the logical address to be accessed in the virtual memory space,
The real storage space of the main storage device and the storage space of the auxiliary storage device
Between the main storage device and the
The address of the data stored in the auxiliary storage device is
An address translation unit for translating into a physical address;
The data corresponding to the logical address sent by the PU is
When it does not exist in the main storage device,
The data corresponding to the logical address is read in page units.
Read out the data and compress the read data to the main memory.
Device, and stores the C
Reads and decompresses what the PU requests, and
Memory and then read from the cache memory.
The output data is transferred to the CPU .

[0017]

When data is transferred from the auxiliary storage device to the main storage device, the data is compressed by the data compression / decompression device, so that the amount of data that can be transferred at one time is increased, and the storage capacity of the main storage device is accordingly reduced. In addition to the apparent enlargement, the frequency of access to the main storage device storing the data transferred from the auxiliary storage device increases, so that the processing capacity can be improved.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a storage management method in a computer according to the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing a hardware configuration of a computer to which a storage management system according to an embodiment of the present invention is applied.

In FIG. 1, reference numeral 2 denotes a CPU (central processing unit), 4 denotes a main storage device comprising a ROM and a RAM, 6
Is an auxiliary storage device such as a hard disk, 8 is a secondary memory interface, 10 is an address conversion unit (MMU),
Reference numeral 12 denotes a physical address bus, reference numeral 14 denotes a data bus, and reference numeral 16 denotes a cache memory. These components are the same as those in the conventional example described with reference to FIG. In this embodiment, the following configuration is provided in addition to the above configuration.

That is, there is provided a data compression / decompression device 20 connected to the physical address bus 12 and the data bus 14 via the input / output interface 18.
The data compression / decompression device 20 includes an input-side cache memory 20a, a compression / decompression integrated circuit 20b, and an output-side cache memory 20c.

FIG. 2 shows a real storage space 30 which is a memory image of the main storage device 4. The real storage space 30 is roughly divided into an OS area 30A, a cache memory area 30B (64 Kbytes), and a compressed data holding unit 30C. In the OS area 30A, in addition to the exception handling routine 32, an address conversion unit (M
The task register 54, the segment table 56 (16K bytes), and the page mapping table 58 (256K bytes) which are referred to by the MU (10) are included. 34 is a compressed data table.

FIG. 3 shows a virtual storage space 40 which is a memory image of the auxiliary storage device 6. The virtual storage space 40 has a system area 42, a user task area 44, a compressed data storage area 46, a secondary memory swap area 48, and the like.

Next, the operation of the computer of this embodiment regarding the storage management method will be described.

When data stored in the auxiliary storage device 6 is read into the main storage device 4, the data is first mapped to the secondary memory swap area 48 of the virtual storage space 40 by an OS (operating system) system call. Registration).

When the CPU 2 makes a system call for mapping, the data stored in the auxiliary storage device 6 is mapped to the secondary memory swap area 48 in page units, and the mapped page data is stored in the secondary memory. The data is transferred to the data compression / decompression device 20 via the interface 8 and the data bus 14. The compression / decompression integrated circuit 20b of the data compression / decompression device 20 is set to the compression mode via the input / output interface 18.

The page-by-page data mapped and transferred is first stored in the input side cache memory 20a in the data compression / decompression device 20, and is compressed by the compression / decompression integrated circuit 20b in the compression mode. After that, the data is stored in the output side cache memory 20c. Further, the compressed data is transferred to the data bus 14.
Is transferred to the compressed data holding unit 30C in the real storage space 30 of the main storage device 4 and stored therein.

A data length is written at the head of the compressed data, and a page other than the page related to the main storage device 4 is written in the page mapping table 58 as a page. In the lower bits, the compressed data table 34
The offset at has been written. This is CPU2
When an access is made from the CPU, an exception process is generated, and during the exception process, the compressed data of the compressed data holding unit 30C is transferred to the compression / decompression integrated circuit 20b in the decompression mode in page units.

When the CPU 2 accesses the compressed page, the OS activates the exception handling routine 32 to set the compression / decompression integrated circuit 20b to the decompression mode via the input / output interface 18 as described above. The compressed data is transferred from the compressed data holding unit 30C to the input cache memory 20a of the data compression / decompression device 20. The compressed data stored in the input side cache memory 20a is transmitted to the compression / decompression integrated circuit 20 in the decompression mode.
After the data is expanded by b, the data is stored in the output side cache memory 20c.

Further, the decompressed data is transferred to the cache memory 16 of the CPU 2 via the data bus 14. Then, the data loaded in the cache memory 16 is processed by access from the CPU 2.

As described above, since the auxiliary storage device 6 is used as the virtual storage space 40, the storage capacity of the main storage device 4 is apparently expanded.

In addition, the auxiliary storage device 6 to the main storage device 4
Since the transfer of data in page units is performed in a compressed state, the unit amount per page unit can be increased as compared with the conventional example, and the data length in page units can be increased. In other words, the real storage space 30 of the main storage device 4 is substantially expanded.

Therefore, the frequency of data transfer from the auxiliary storage device 6 to the main storage device 4 can be reduced, the frequency of access to the auxiliary storage device 6 having a low operation speed is reduced, and the main storage device 4 having a high operation speed is reduced. Since the frequency of access to the URL increases, the processing capability can be increased.

[0034]

As described above, according to the present invention, it is possible to increase the processing capacity while increasing the apparent storage capacity of the main storage device.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a hardware configuration of a computer to which a storage management method according to an embodiment of the present invention is applied.

FIG. 2 is a memory image of a real storage space of a main storage device according to the embodiment.

FIG. 3 is a memory image of a virtual storage space for an auxiliary storage device according to the embodiment.

FIG. 4 is a block diagram showing a general hardware configuration of a conventional computer.

FIG. 5 is a conceptual diagram of a general segment paging scheme used in a conventional virtual storage scheme.

[Explanation of symbols]

 2 CPU 4 Main storage device 6 Auxiliary storage device 10 Address conversion unit (MMU) 12 Physical address bus 14 Data bus 16 Cache memory 20 Data compression / decompression device 20a Input side cache memory 20b Compression / decompression integrated circuit 20c Output side cache memory Reference Signs List 30 real storage space 30C compressed data holding unit 40 virtual storage space

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-1-111244 (JP, A) JP-A-2-12352 (JP, A) JP-A-59-14185 (JP, A) JP-A-58-58 220288 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G06F 12/08 G06F 12/10

Claims (1)

(57) [Claims] 1. A writing / reading speed is fast and a storage capacity is high.
Small main storage device and slow writing / reading speed
Auxiliary storage device with large capacity and theory of CPU access
A physical address in a virtual storage space, and the main storage device
The real storage space of the storage device and the storage space of the auxiliary storage device are integrated.
The main storage device and the auxiliary storage device for managing
The address of the data stored in the logical address
And an address translator for translating the data.
Data corresponding to the logical address is stored in the main storage device.
When the logical address is not present in the auxiliary storage device,
Read the data corresponding to the
Compresses the read data and stores it in the main memory
And the CPU requests out of the data in the main storage device.
Read, decompress, write to cache memory
Data read from the cache memory.
A storage management method in a computer , wherein the data is transferred to the CPU .