JP3206275B2 - Logic circuit with error detection function and fault tolerant system using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a self-check circuit and a method for constructing the self-check circuit, and more particularly to a self-check comparison circuit suitable for a highly reliable system configuration.

[0002]

2. Description of the Related Art Advanced control is required to improve energy (fuel) efficiency, operability, ride comfort, safety, and speed of transportation such as aircraft, trains, and automobiles. Accordingly, computerization of these control devices is progressing. For the safe operation of these transportation means, there is a strong demand for the reliability and fail-safeness of the control device (that no dangerous output is generated due to the occurrence of a failure).

In order to guarantee the reliability and fail-safeness of the control device, it is necessary to detect the occurrence of a failure in the control device.
That is, self-checking properties are important. In order to realize the self-checking property, an M-out-of-N code or a two-wire logic (1-out-of-2 code, that is, M-out-of-code) is used.
A method using a so-called redundant code in which the hamming distance between codes is two or more is widely used. According to the above method, it is possible to completely detect a single fault. However, this is not always the case when multiple faults occur, and when a self-check circuit is implemented in an LSI, the generated fault propagates to the entire chip, and a phenomenon equivalent to the occurrence of multiple faults. May be indicated. Here, when a failure occurs, the probability that an erroneous output coincides with the code point of the determined output code space O is based on the assumption that the error is random.

[0004]

(Equation 1)

Where No: number of code points in the output code space O Nu: number of code points Therefore, how to increase Nu with respect to No is a problem in improving the detection rate.

There are the following two methods for realizing a self-checking circuit using the above redundant codes.

(1) A method of configuring the entire circuit with redundant codes (2) A method of duplicating a functional block unit and comparing outputs of the functional block units with a self-checking comparing circuit configured with redundant codes (1) The method of (1) requires a new design for achieving self-checking, and it is difficult to optimize the operation speed of the circuit.

On the other hand, according to the method (2), only the comparison circuit needs to be newly designed with redundant logic, so that the existing processor and memory can be used for the functional block unit, so that the development cost is greatly increased. In addition, the speed can be easily increased because the latest semiconductor technology can be utilized. The self-checking performance of this method largely depends on the self-checking performance of the comparator.

Therefore, in order to realize a self-checking comparator, the logic itself used in the comparison circuit is M-ou.
It has been proposed to use redundant codes such as t-of-N codes or two-wire logic. For example, in the literature (Yoshihiro Toma, “Fault-Tolerant System Theory”, IEICE)
(1990)) shown in Fig. 2.5 (p. 31).
ction Circuit for Checker Output)
By connecting to a tree structure as shown in (p.32),
A self-checking comparator can be realized.

In the case of the comparator, the probability of occurrence of a fault in the circuit to be compared is small, so that a mismatch between signals to be compared rarely occurs. Therefore, if a path to be activated is rarely activated when a mismatch is detected, and a failure occurs in a mode in which the output of this path is always fixed to mean “match”, However, there is a possibility that a failure may occur. Therefore, in the case of the comparison circuit, in addition to the above-described redundant code, a dynamic logic in which the signal level changes in an alternating manner such as a frequency logic or an alternating test method is used instead of the binary level logic of 0 and 1. Is used as a signal indicating that the signal is normal (hereinafter, referred to as a signature signal). One example is Figure 2.15 of the above documents, RCCO shown in 2 .16 (p.42)
A permuter (per
muter). In this way, an AC output can be obtained in a normal state, and the threshold value of the semiconductor element fluctuates and a fixed fault at the 0,1 level (stack-at 0,1).
In the event of a failure due to fluctuations in the DC characteristics of the device (e.g., failure), AC signals cannot be obtained, and errors are periodically injected to check the operation of the error detection function. King performance is significantly improved.

[0011]

The above prior art has a problem that it is susceptible to contact between wiring nets in a semiconductor device. When crosstalk occurs between wiring nets due to failure of a semiconductor element due to crosstalk between wiring nets, migration of wiring material, insulation failure of an insulating layer, or the like, a signature signal of another wiring net (hereinafter referred to as a signal of another wiring net) This is called a forged signature). Normally, in a fail-safe circuit, a signature signal indicates that the circuit is normal, so that a forged signature due to cross-contact recognizes that the circuit is normal even though the circuit is abnormal, which may impair the fail-safe property of the circuit. .

For this reason, in the prior art, the occurrence of cross-contact has been prevented by adding a special design constraint to the wiring interval and the like. However, according to this method, transistors and wirings must be formed on a semiconductor substrate based on restrictions completely different from those of general-purpose semiconductors, so that the benefits of existing technologies and design automation tools cannot be enjoyed at all, and many methods cannot be used. In many cases, there was a lot of human manual work.

An object of the present invention is to provide a logic circuit with an error detection function that does not require special restrictions and can guarantee fail-safeness, and a fault-tolerant system using the same.

[0014]

According to the present invention, a functional block for outputting a plurality of signals has at least a duplex configuration,
Comparing means for comparing the outputs of these functional blocks,
In a logic circuit with an error detection function for detecting an error based on a comparison result, a synthesizing means for superimposing a unique waveform previously assigned to each output signal on an output signal of the one functional block is provided, It is characterized in that an error is detected by comparing the output from the means with the output from the other functional block.

That is, for example, when a semiconductor element is assumed, a unique signal waveform is assigned as a signature to each wiring net corresponding to each of the above output signals, and only when the signal waveform matches the signal waveform unique to the wiring net, It should be considered a signature.

In order to distinguish a legitimate signature from a forged signature, it is desirable that signatures unique to each wiring net have no correlation with each other. Here, the orthogonal function is widely known as a function having no correlation.

[0017]

(Equation 2)

If so, the functions fi (x) and fj (x) are said to be orthogonal to each other. Known orthogonal functions include trigonometric functions having different periods, Walsh-Hadamal functions, and M-sequences. Wavelet analysis, which analyzes signal waveforms in the time-frequency domain instead of conventional Fourier analysis, has recently attracted attention, and the underlying Wavelet is also an orthogonal function. Although the trigonometric function and Wavelet are analog functions, they may be binarized in order to apply them to digital circuits.

[0019]

According to the present invention, for example, when a semiconductor element is assumed, a unique signal waveform is assigned to each wiring net as a signature, and a signature is valid only when the signal waveform matches a signal waveform unique to the wiring net. Is considered.
As a result, even if a crosstalk occurs between wiring nets due to crosstalk, migration of wiring material, insulation failure of an insulating layer, and the like, and a signature signal is induced from another wiring net, a false signature is inherent in the wiring net. Since it does not match the signal waveform, it can be distinguished from a legitimate signature. Therefore, a special wiring restriction or the like, which is indispensable for the complete detection of a fault in the prior art, for preventing cross-contact is not required, and fail-safe performance can be guaranteed.

[0020]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

FIG. 1 shows an embodiment of a comparator according to the present invention. Errors for testing are injected into the signals a0 to an (10 to 1n) from the functional block A by the permuters 80 to 8n according to the orthogonal waveform (test pattern) generated by the orthogonal waveform generating circuit 100. The signals after injection are a0 'to an' (10 'to 1n'). Note that the permuters 80 to 8n are provided with exclusive ORs (Exclu
sive OR), which has a function to inject errors artificially for testing. Subsequently, the signals 10 'to 1n' after the error injection are compared with the signals b0 to bn from the functional block B by comparing circuits 30 to 3n.
bn (20 to 2n), and the comparison results 40 to 4n are collected in the integrated circuit 5, where the comparison results 40 to 4n
Only when n indicates a normal signature, a signature signal indicating normal is output to the signature output 6.

Here, the signals a0 'to an' after error injection are performed.
If any one of (10 'to 1n') is represented by ai ',

[0023]

Ai ′ = ai ＾ pi (Equation 3) where i: signal number (i: 0... N) pi: orthogonal waveform (test pattern) generated by orthogonal waveform generating circuit 100 ＾: exclusive It is an operator of Exclusive OR. Further, when any one of the comparison results c0 to cn (40 to 4n) is represented by ci,

[0024]

## EQU4 ## ci = ai '＾ bi = ai ＾ pi ＾ bi (Equation 4) Here, when the functional blocks A and B are normal, ai ＾ bi = 0 since ai = bi. Therefore,

[0025]

Equation 5: ci = pi (Equation 5)

Here, since arbitrary p i (i: 1... N) are mutually orthogonal, ci and c j (i ≠ j) are also orthogonal. a
Assuming that i and pi are statistically independent or orthogonal, ai and ai 'are also orthogonal to each other, and bi and ai' are also orthogonal to each other. Therefore, among these waveform groups, correlations that are not orthogonal but have a correlation between ai and bi and between pi and ci
Between. Therefore, in order to prevent the generation of a forged signature due to the above-mentioned touch, ai, bi and pi,
If the circuit layout is considered so as to be physically separated between ci, it is possible to prevent the influence of forgery signatures caused by cross-contact. An example of this circuit layout will be described later (FIG. 15).

According to the present embodiment described above, a complete self-checking comparator can be provided without requiring special wiring restrictions or the like.

In FIG. 2, the function block A11
0, the function block B111 is always a valid signal a0 to an
(10 to 1n) and b0 to bn (20 to 2n) are not necessarily output, and signals a0 to an (10 to 1n) and signals b0 to bn (20 to
2n) is often output together with a strobe signal indicating that it is valid. In such a case, the signals a0 to an by the strobe signals 130 and 131 as shown in FIG.
When (10-1n) and b0-bn (20-2n) are valid, they may be held by the latches 120 and 121. The type of signal used as a strobe signal in a circuit using a microprocessor differs depending on the microprocessor, and the address signal and the control signal are AS (Address Strob).
e), data signal such as BS (Bus Start)
(TransferAcknowledge), DTACK (Data Transfer Ac
knowledge) can be used as the strobe signal.

FIG. 3 shows the present invention in the literature (Yoshihiro Toma, "Fault Tolerant System Theory", IEICE (1)
990)) is an embodiment applied to a comparator based on an RCCO tree. Signals a0-an (10-1)
n) includes a permutator 80 to 8n and a quadrature waveform generation circuit 1
The error for the test is injected according to the orthogonal waveform (test pattern) generated at 00, and the signal 1 after the error injection is
0 'to 1n' and input to the RCCO tree 3.
In the case of the RCCO tree, the signature output 6 is also a two-wire logic.

As in the embodiment of FIG. 1, the input and output of the RCCO are orthogonal inside the RCCO tree 3, so that it is possible to prevent the influence of forgery signatures caused by cross-contact.

In the following description of the embodiment, description will be made based on the comparison circuit shown in FIG. 1. However, unless otherwise specified, the comparison circuit based on the RCCO tree can be similarly implemented.

FIG. 4 shows signals b0 to bn from the function block B.
(20-2n) is also an embodiment in which errors are injected by the permuters 90-9n using the orthogonal waveforms generated by the orthogonal waveform generation circuit 100. According to the present embodiment, when bi takes the same value for a long time, it is possible to prevent the stack fault of the input of the comparison circuit from becoming latent. For example, if bi is an address signal and the program uses only an address in a specific area, the value of the upper bits of the address is constant for a long time.

FIG. 5 shows an embodiment in which the functional blocks A and B have orthogonal waveform generating circuits 100 and 101 separately and independently. According to the present embodiment, the orthogonal waveform generation circuits 100 and 10
1 is duplicated, the orthogonal waveform generation circuits 100, 1
01 faults can be detected and reported. Further, according to this embodiment, the independence of the two systems can be utilized in the layout described later with reference to FIG.

FIG. 6 shows an embodiment in which a pulse-on waveform is used in a time slot unique to each wiring net as an orthogonal waveform. According to the present embodiment, the output patterns p0 to pn of the orthogonal waveform generation circuit 100 and the functional blocks A110 and B1
11 are normal and the comparison results c0 to cn (40
4n) are as shown in FIG.

FIG. 7 shows an embodiment of the orthogonal waveform generating circuit 100 for generating a pattern as shown in FIG. At the power-on reset of the system, the RESET signal becomes active, the flip-flop 1001 is preset (1 is set as an initial value), and the flip-flop 1001 is reset.
2 to 100 m is reset (0 is set as the initial value)
Is done. That is, the flip-flop arrays 1001 to 10
0m is set to a value of 1, 0, 0, 0, 0,... 0.
After the power-on reset, the patterns of 1, 0, 0, 0, 0,... 0 are sequentially shifted according to the CLK (clock) signal to generate the pattern of FIG. Flip-flop 1
If 001 to 100 m are made redundant and the output of the redundant flip-flop is determined for each stage, a soft error of the flip-flop due to noise or radiation, a temporary error called a single event upset, etc. Transient fault) can be prevented, and reliability can be further improved. It is needless to say that this orthogonal waveform generation circuit 100 can also be used for the RCCO tree 3 in FIG.

FIG. 8 shows an integrated circuit 5 suitable for the pattern of FIG.
This is an embodiment of the invention. According to the pattern of FIG. 6, since a simple OR (logical sum) as shown in FIG. 8 has a different waveform, occurrence of a failure can be known. At this time, even if a collision occurs between the wiring nets, there is no other wiring net using the valid signatures of p2 and c2, so that the valid signature appears erroneously in the signature output 6. No forged signature is output. Therefore, even in the case where a forged signature due to a touch occurs, fail-safe performance can be guaranteed.

FIG. 11 shows an embodiment in which an excess pulse detecting function is added to the pulse missing detecting function of the integrated circuit of FIG. Here, the excess pulse is a signal c0 to cn (40 to 4n).
Is a phenomenon in which one of the signals is turned on at the same time.
As shown in FIG. 9, any one of c0 to cn (40 to 4n)
If two signals are turned on, OR (logical sum) 50, E
Both the OR (exclusive OR) 51 generates a signature output as shown in FIG. Here, as shown in FIG.
When the pulses are turned on at the same time at 2 and cn, FIG.
As shown in (1), the pulse of the signature output 61 is lost and the waveform becomes different from the valid signature, so that the occurrence of a failure can be known.

FIG. 13 shows an embodiment of the assembling circuit 5 further considering the arrival sequence of pulses. If the signature pulse of the comparison result normally arrives in the order of c0, c1, c2,... Cn, the level of the signature output 6 is inverted every time a signature pulse of cn arrives, as shown in FIG. However, if any of the signature pulses c0, c1, c2,... Cn is missing, the signature output 6 will not be inverted or the period will be significantly longer. According to the present embodiment, failure detection greatly facilitates the cycle of the signature output 6 due to a failure.

FIG. 15 shows an embodiment of the layout of the present invention. Signals a0-an (10
To 1n) are latched by the latch 120 in response to the strobe signal 130, the exclusive OR of the orthogonal waveform of the orthogonal waveform generation circuit 100 and the permuters 80 to 8n is obtained, and a0 'to a
n '(10' to 1n '). Similarly, signals b0 to bn (20 to 2n) from the function block B111 are latched by the latch 121 by the strobe signal 131.
The orthogonal waveform of the orthogonal waveform generating circuit 101 and the permuter 90
９ 9n to obtain an exclusive OR, and b0 'to bn' (20 '
~ 2n '). The signal a generated as described above
0 'to an' (10 'to 1n'), b0 'to bn' (2
0 'to 2n') are compared by the comparison circuits 30 to 3n to become comparison results c0 to cn (40 to 4n), which are output to the signature output 6 by the integrated circuit 5. Up to this point, the embodiment is as described above.

Here, the comparison circuits 30 to 3n and the assembly circuit 5
To area 0 (200), function block A110, latch 1
20, orthogonal waveform generating circuit 100, permuters 80 to 8
n is the area 1 (201), the function block B111, the latch 121, the orthogonal waveform generation circuit 101, the permuters 90 to
9n is divided into two regions, a region 2 (202). When these circuits are formed as individual chips, the area 0 (20
0), area 1 (201), and area 2 (202). Further, when these circuits are accommodated in the same chip, the area 0 (200) and the area 1
By setting a distance between (201) and the area 2 (202), or by using separate power grounds, it is possible to prevent the propagation of a fault. According to the layout of the present embodiment described above,
Correlated signals, ie, between ai, bi and pi,
Since the ci can be separated geometrically, physically, or electrically, it is possible to prevent the influence of the generation of a forged signature due to cross-contact.

In designing a high-performance LSI, a general layout (floor plan) is based on a heuristic method such as human experience and intuition, and a method of automatically wiring details based on a fixed algorithm is generally used. Is efficient. Accordingly, many of the existing automatic wiring tools have a function of inputting a rough layout (floor plan) by a human and automatically wiring detailed wiring. Therefore, the method according to the present embodiment has good consistency (compatibility) with the functions of the existing automatic wiring tools, and the functions of these automatic wiring tools can be utilized to the maximum.

According to the present embodiment described above, a functional block by ordinary logic design is simply logically or optically copied, and the area 0 (200) composed of the comparison circuits 30 to 3n and the assembly circuit 5 is copied. ) Enables easy self-checking, not only improving reliability, but also significantly reducing development cost man-hours.

FIG. 16 shows an embodiment of a self-checking computer using the present invention. Each of the functional blocks A110 and B111 has an MPU (Micro-Processing U).
nit), WDT (Watch Dig Timer), INTC (interrupt controller), and other computer components are connected to the internal buses 212 and 213. Each functional block is connected to external buses 206 and 207 via interfaces 204 and 205. The comparator according to the present invention compares the signal of the internal buses 212 and 213 with a signal in which a signature is superimposed by the permuters 80 to 8n and 90 to 9n in accordance with the pattern generated by the orthogonal waveform generating circuits 100 and 101, thereby making a functional block A11.
0, B111 normal / abnormal is determined. Internal bus 21
2 and 213, the comparator (region 0)
(200)) outputs the signature signal to signature output 6. Further, as shown in FIG. 16, the functional block A110 is (area 1 (201)), the functional block B111 is (area 2 (202)), and the area 0 (200) of the comparator is between areas according to the layout shown in FIG. If they are arranged on one chip after being separated from each other or the power ground is separated, a one-chip self-checking microcomputer can be realized. For simplicity,
The latches 120 and 121 are omitted.

In addition to the internal buses 212 and 213, the external bus 2
If the comparators 06 and 207 are checked by the comparator (area 0 (200)), the operation of the entire LSI including the operation of the interfaces 204 and 205 can be further monitored.

According to this embodiment, the MP having the normal design
U (Micro-Processing Unit), WDT (Watch Dig Time
r), a functional block of a microcomputer constituted by components of the microcomputer such as an INTC (interrupt controller) is simply logically or optically copied (at a mask pattern level) and duplicated, and a comparison circuit 40 is provided. .About.4n, a region 0 composed of an integrated circuit 5
By combining with (200), a self-checking microcomputer can be easily realized,
A highly reliable self-checking circuit can be realized with less development man-hour and cost.

FIG. 17 shows an embodiment of a fault-tolerant computer system using a self-checking computer. Self-checking computer 20
3, 203 'to the external bus 206 (207), 206'
The signal output to (207 ') is selected by the output selection circuit 210 and becomes the final output 211. Output selection circuit 2
10 is controlled by a switching control signal 209 generated by the switching control circuit 208 based on the signature outputs 6, 6 '. That is, based on the signature outputs 6, 6 'from the self-checking computers 203, 203', the outputs of the self-checking computer regarded as normal are selected.

FIG. 18 is a diagram for explaining the configuration of the switching control circuit 208. Signature monitoring circuit 21
2, 213 monitor the signature outputs 6, 6 ', and if the signature outputs 6, 6' are normal, the monitoring results 214, 2
15 outputs a signal indicating "normal", and when the signature outputs 6, 6 'are abnormal, outputs signals indicating "abnormal" to the monitoring results 214, 215. In decision logic 216,
Only when the signature output 6 is abnormal and the signature output 6 'is normal, the switching control signal 209 indicates "external bus 20".
6 '(207') is selected. Otherwise, "external bus 206 (207) is selected".
Outputs a meaning signal. In the drawing, for simplicity, a signal indicating “normal” of the monitoring results 214 and 215 is a normal binary logic H level, a signal indicating an “abnormal” is L level, and the “external bus” of the switching control signal 209 is illustrated. 206 '(2
07 ') is shown at H level, and a signal meaning' select external bus 206 (207) 'is shown at L level. However, these signals are not limited to binary logic, and if a redundant logic such as a two-wire logic, a frequency logic, and a unique signature for each net provided by the present invention are used, the switching control circuit 208 can be made highly reliable. Thus, the reliability of the entire system can be further improved.

Subsequently, the signature monitoring circuits 212 and 2
The thirteenth embodiment will be described. In the case where the signature output 6 has a periodic waveform as shown in FIG. 9, the signature monitoring circuits 212 and 213 can be realized by monitoring the arrival of the pulse at a constant interval by a counter. If the signature output 6 is a more complex waveform, the correlation is made with a waveform serving as a reference (template). If the correlation is 1.0, it is determined to be normal, and if the correlation is less than 1.0, If it is determined that is abnormal, the signature monitoring circuits 212 and 213 can be realized.

According to this embodiment described above, a hot-standby fault-tolerant system in which the self-checking computer 203 is the main system and the self-checking computer 203 'is the subordinate (standby) system can be constructed. In addition, a more reliable system than before can be provided by the error detection system with few detection omissions provided by the present invention.

The self-checking computer provided by the present invention can be applied to fault-tolerant systems having various configurations other than the above-described system configuration. For example, the present invention can be applied to Japanese Patent Application No. 63-266055 (hereinafter referred to as an already applied patent) which has already been filed by the inventors. Subsystem 1 of FIG.
-1 to 1-N are replaced with the self-checking computer 203 provided by the present invention, and the output
The present invention can be applied by replacing .about.3-N with the external bus 208 (207) of the present invention and replacing the mutual diagnosis results 4-1 and 4-N of the patent application with the signature output 6 of the present invention.

FIG. 19 shows an embodiment of a self-checking comparator according to the present invention. Here, the comparison circuits 40 to 4n,
Assembling circuit 5 in area 0 (200), latch 120, quadrature waveform generating circuit 100, and permuters 80-8n in area 1 (2).
01), the latch 121, the orthogonal waveform generation circuit 101, and the permuters 90 to 9n are divided into two regions, a region 2 (202), and a region 0 (200) and a region 1 (20
1), the area 2 (202) is spaced apart from each other, and the power supply ground is separated to prevent the propagation of a fault. These circuits are housed in the same chip to form a comparator 217. The comparator 217 is connected to the external function blocks A110 and B111 and compares the outputs. According to the present embodiment, similarly to the embodiment shown in FIG.
That is, since ai, bi and pi, ci can be separated geometrically, physically, or electrically, it is possible to prevent the influence of generation of a forged signature due to cross-contact, and to perform self-checking comparison. Vessel can be realized.

[0052]

According to the present invention, it is possible to provide a new method capable of guaranteeing fail-safe performance even when a forgery signature due to a touch occurs. Therefore, the present invention does not require special restrictions in realizing a fail-safe logic circuit, and can benefit from existing semiconductor technologies, design automation tools, etc., and greatly reduces both development cost and time. Can be expected.

[Brief description of the drawings]

FIG. 1 shows a basic embodiment of the present invention.

FIG. 2 is an embodiment corresponding to a functional block;

FIG. 3 shows an embodiment using an RCCO tree.

FIG. 4 is an embodiment in which an orthogonal waveform is added to the output from the functional block B;

FIG. 5 is an embodiment in which the orthogonal waveform generation circuit is duplicated.

FIG. 6 is an example of an orthogonal function waveform.

FIG. 7 is an embodiment of an orthogonal waveform generation circuit.

FIG. 8 shows an embodiment of an integrated circuit.

FIG. 9 is an example of an orthogonal function waveform and signature output.

FIG. 10 shows an example of an orthogonal function waveform and a signature output at the time of a failure.

FIG. 11 shows an embodiment of an integrated circuit.

FIG. 12 shows an example of an orthogonal function waveform and a signature output at the time of a failure.

FIG. 13 shows an embodiment of an integrated circuit.

FIG. 14 shows an example of an orthogonal function waveform and signature output.

FIG. 15 is a circuit layout according to the present invention.

FIG. 16 is a configuration diagram of a self-checking computer according to the present invention.

FIG. 17 is a configuration diagram of a fault-tolerant computer system using a self-checking computer.

FIG. 18 is a configuration diagram of the inside of a switching control circuit.

FIG. 19 is a self-checking comparator.

[Explanation of symbols]

10 to 1n: signals a0 to an from the functional block A, 20
.About.2n ... signals b0 to bn from functional block B, 3 ... RC
CO, 30-3n... Comparison circuit, 40-4n... Comparison result c
0 to cn, 5: integrated circuit, 6: output signal, 80 to 8n, 9
0-9n-permuter, 100, 101: orthogonal waveform generating circuit, 110: functional block A, 111: functional block B, 120, 121 ... latch, 203, 203 '... self-checking computer.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Issumi Tashiro 7-1-1, Omikacho, Hitachi City, Ibaraki Prefecture Within Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Keisuke Toji 7-1 Omikamachi, Hitachi City, Ibaraki Prefecture No. 1 Hitachi, Ltd., Hitachi Research Laboratory (72) Inventor Hiroshi Sato 7-1-1, Omikacho, Hitachi City, Ibaraki Prefecture Hitachi, Ltd., Hitachi Research Laboratory (72) Inventor Makoto Nomi 1070 Ichige, Katsuta City, Ibaraki Prefecture Address: Mito Plant, Hitachi, Ltd. (72) Inventor: Shinya Otsuji 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Within Hitachi Research Laboratory, Hitachi, Ltd. (56) References JP-A-9-288150 (JP, A) JP 8-171581 (JP, A) JP 5-35514 (JP, A) JP 2-138636 (JP, A) Toma Yoshihiro, " Over belt-tolerant system theory ", Institute of Electronics, Information and Communication Engineers, 1990 June 10, p. 41-42 (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 11/16-11/20 G06F 11/22-11/26

Claims (13)

(57) [Claims] 1. A logic circuit with an error detection function for comparing an output of at least a duplicated functional block and detecting an error, wherein one or both of the outputs of the duplicated functional block are provided for each of the blocks. the preassigned provided combining means for superimposing a unique waveform, the be one that detects an error based on an output from the combining means, the unique waveform which is assigned in advance to each block is Bed
A logic circuit with an error detection function, wherein the waveforms are orthogonal to each other for each lock and each bit . 2. The apparatus according to claim 1, wherein said synthesizing means includes a waveform generating means for generating a unique waveform pre-assigned for each of said functional blocks, and said generated unique waveform and an output from said functional block. A logic circuit with an error detection function, comprising: a logic operation means for calculating an exclusive OR of 3. A logic circuit with an error detection function, wherein a functional block for outputting a plurality of signals has at least a duplex configuration, and a comparing means for comparing outputs of these functional blocks, and detecting an error based on a comparison result. A synthesizing unit that superimposes a unique waveform previously assigned to each output signal on the output signal of the one functional block, and compares an output from the synthesizing unit with an output from the other functional block. A logic circuit with an error detection function that detects errors by performing 4. The apparatus according to claim 3, wherein said synthesizing means includes a waveform generating means for generating a unique waveform assigned to each of said output signals in advance, and said generated unique waveform and said one of said functional blocks. A logic circuit with an error detection function, comprising a logic operation means for calculating an exclusive OR with each output signal. 5. The logic circuit with an error detection function according to claim 3, wherein the unique waveforms previously assigned to each output signal are mutually uncorrelated waveforms. 6. A logic circuit with an error detection function according to claim 3, wherein the unique waveforms previously assigned to the respective output signals are mutually orthogonal waveforms. 7. A logic circuit with an error detection function, wherein a function block for outputting a plurality of signals has at least a duplex configuration, a comparison means for comparing outputs of these function blocks, and an error detection function based on a comparison result. A first synthesizing means for superimposing a unique waveform previously assigned to each output signal on the output signal of the one functional block, and an output signal of the other functional block for each output signal in advance. Error detecting means for detecting an error by comparing an output from the first synthesizing means with an output from the second synthesizing means. Logic circuit with function. 8. A method for comparing output signals between functional blocks outputting a plurality of duplicated signals and detecting an error, wherein each output of one of the duplicated functional blocks is output. A unique waveform previously assigned to each output signal is superimposed on the signal, and the other output signal of the duplicated functional block and each output signal on which the unique waveform is superimposed is generated. An error detection method comprising comparing and detecting an error. 9. An exclusive OR operation of each output signal of one of the duplicated function blocks and a unique waveform previously assigned to each output signal according to claim 8, An error detection method comprising superimposing the eigenwaveform. 10. A method for comparing output signals between functional blocks that output a plurality of duplicated signals and detecting an error, wherein each output of one of the duplicated functional blocks is output. A unique waveform previously assigned to each output signal is superimposed on the signal, and the other output signal of the duplicated functional block and each output signal on which the unique waveform is superimposed is generated. An error detection method comprising: comparing and, if the comparison results in a waveform other than the pre-assigned unique waveform, determining that the waveform is erroneous. 11. A method for comparing output signals between functional blocks that output a plurality of duplicated signals and detecting an error, wherein each output of one of the duplicated functional blocks is output. A unique waveform previously assigned to each output signal is superimposed on the signal, and the other output signal of the duplicated functional block and each output signal on which the unique waveform is superimposed is generated. Comparing, if the comparison does not result in the pre-assigned unique waveform,
An error detection method characterized by determining an error. 12. A first circuit, comprising at least a CPU, an interrupt controller, and a timer, for generating a plurality of output signals, a second circuit having the same function as the first circuit, and the first circuit. And a logic circuit with an error detection function having a comparison circuit for comparing each output signal from the second circuit, wherein the plurality of output signals are assigned to each of the plurality of output signals in advance in the first and second circuits. Provided with first and second combining circuits for superimposing the obtained unique waveforms, and wherein the first circuit, the second circuit, and the comparing circuit are respectively arranged on different chips. Logic circuit. 13. A synthesizing means for superposing a function block for outputting a plurality of signals at least in a duplex configuration and superimposing a unique waveform previously assigned to each output signal on an output signal of one of the function blocks. A first computer and a second computer that detect an error by comparing an output from the synthesizing unit with an output from the other functional block;
A switching control circuit for selecting one of the outputs of the first and second computers and outputting the selected output to the outside, wherein the switching control circuit detects an error output from the first and second computers. A fault tolerant system, wherein one of the computer outputs is selected based on a signal.