JP3203172B2 - MPEG video decoder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an MPEG (Moving)
Picture Expert Group) relates to a video decoder.

[0002]

2. Description of the Related Art The information handled by multimedia is enormous and diverse, and it is necessary to process such information at high speed in order to put multimedia into practical use. In order to process information at high speed, data compression / decompression technology is indispensable. As such data compression / decompression technology, the “MPEG” method is exemplified. This MPEG system is based on the ISO (International Organization).
for Standardization) / IEC ( International Elec)
trotechnical Commission)
It is being standardized by O / IEC JTC1 / SC29 / WG11).

[0003] MPEG is composed of three parts. Part 1 “MPEG System Part” (ISO / IEC
IS 11172 Part1: Systems) defines a multiplex structure (multiplex structure) of video data and audio data and a synchronization method. Part 2 "MPE
In the "G video part" (ISO / IEC IS 11172 Part2: Video), a high-efficiency encoding method of video data and a format of the video data are specified. Part 3, "MPEG
Audio Part ”(ISO / IEC IS 11172 Part3: Audio)
Defines a high-efficiency encoding method of audio data and a format of audio data.

[0004] The video data handled by the MPEG video part relates to a moving image, and the moving image is composed of several tens (eg, 30) frames (still images, frames) per second. As shown in FIG. 8, video data includes a sequence (Sequence) and a GOP (Group).
Of Pictures), Pictures (Picture), Slices (Sl
ice), macroblock (Macroblock), block (Bl
ock) in the order of six layers. The number of slices constituting one picture is not constant, and the number of macroblocks constituting one slice is not constant.
In FIG. 8, the macro block layer and the block layer are omitted.

[0005] At present, MPEG-1 and MPEG-1 are mainly used due to differences in encoding rates.
-2. In MPEG-1, a frame corresponds to a picture. In MPEG-2, a frame or a field can correspond to a picture. Two fields constitute one frame. The structure in which a frame corresponds to a picture is called a frame structure, and the structure in which a field corresponds to a picture is called a field structure.

[0006] MPEG uses a compression technique called inter-frame prediction. Inter-frame prediction compresses data between frames based on temporal correlation. In the inter-frame prediction, bidirectional prediction is performed. The bidirectional prediction is to use both forward prediction for predicting a current reproduced image from a past reproduced image (or picture) and backward prediction for predicting a current reproduced image from a future reproduced image. .

[0007] This bidirectional prediction is based on an I-picture (Intra-Pi
), a P picture (Predictive-Picture), and a B picture (Bidirectionally predictive-Picture).

An I picture is generated independently of a past or future reproduced image. In order to perform random access, at least one I picture is required in a GOP. All macroblock types in an I picture are
This is an intra-frame prediction screen (IntraFrame).

A P picture is generated by forward prediction (prediction from a past I picture or P picture). P
The macroblock type in the picture includes both an intra prediction picture and a forward prediction picture ( Forward Inter Frame).

A B picture is generated by bidirectional prediction. In bidirectional prediction, a B picture is generated by any one of the following three predictions. Forward prediction; prediction from past I or P pictures,
Backward prediction; prediction from future I or P pictures; bidirectional prediction; prediction from past and future I or P pictures. The macroblock types in the B picture include four types: an intra-frame prediction screen, a forward prediction screen, a backward prediction screen (Backward Inter Frame), and an interpolative prediction screen (Interpolative Inter Frame).

Then, these I, P and B pictures are respectively encoded. That is, an I picture is generated even if there is no past or future picture. In contrast, a P picture is not generated without a past picture, and a B picture is not generated without a past or future picture.
However, even for P pictures and B pictures, macro blocks
When the type is an interpolative prediction screen, the macroblock is generated without any past or future picture.

In the inter-frame prediction, first, an I picture is periodically generated. Next, a frame several frames ahead of the I picture is generated as a P picture. This P
The picture is generated by one-way (forward) prediction from the past to the present. Subsequently, a frame located before the I picture and after the P picture is generated as a B picture. When generating this B picture, an optimal prediction method is selected from three of forward prediction, backward prediction and bidirectional prediction. In a continuous moving image, the current image and the images before and after it are generally very similar, and only a part of the image is different. Therefore, it is assumed that the previous frame (for example, I picture) and the next frame (for example, P picture) are the same, and if there is a change between both frames, only the difference (B picture data) is extracted. Compress. Thus, data between frames can be compressed based on temporal correlation.

The data sequence (bit stream) of video data encoded in conformity with the MPEG video part is called an MPEG video stream (hereinafter, abbreviated as video stream).

By the way, MPEG-1 mainly uses video C
D (Compact Disc) and CD-ROM (CD-Read Only Mem)
ory). MPEG-
2 is a video CD, CD-ROM, DVD (Digital Vi
deo Disk), VTR (VideoTape Recorder ) and other storage media, as well as communication media such as LAN (Local Area Network), terrestrial broadcasting, satellite broadcasting and CAT
It supports all transmission media including broadcast media such as V (Community Antenna Television).

The core of the technology used in the MPEG video part is motion-compensated prediction (MC).
ated prediction) and discrete cosine transform (DCT; Disc)
reteCosine Transform). An encoding technique using both MC and DCT is called a hybrid encoding technique. In the MPEG video part, when encoding, DCT
The image (video signal) is decomposed into frequency components and processed using FDCT (also known as Forward DCT). Then, at the time of decoding, the inverse transform of DCT (inverse discrete cosine transform; ID
Using CT (Inverse DCT), the frequency component is returned to an image (video signal) again.

FIG. 9 shows a conventional MPEG video decoder 1.
1 shows a block circuit No. 01. MPEG video decoder 1
01 is the bit buffer 102, the frame buffer 10
3. Picture header detection circuit 104, slice header detection circuit 105, variable length decoder 106, inverse quantization circuit 1
07, IDCT (Inverse Discrete Cosine Transform
) Circuit 108, MC (Motion Compensated prediction)
) Circuit 109, ROM (Read Only Memory) 110,
111, a control core circuit 112, and a Huffman error detection circuit 113. Each of the circuits 104 to 113
Are mounted on a one-chip LSI.

The control core circuit 112 includes each of the circuits 102 to 11
1 and 113 are controlled. The video stream transferred from the transmission medium 120 is input to the bit buffer 102. The transmission media 120 includes storage media (video CD, CD-ROM, DVD, VTR, etc.), communication media (LAN, etc.), broadcast media (terrestrial broadcast, satellite broadcast, CATV, etc.).

The bit buffer 102 has a FIFO (First-
In-First-Out (RAM) Random Access Memory (RAM)
, And sequentially accumulates video streams transferred from the transmission medium 120.

The reason why the bit buffer 102 is provided is that the data amounts of the I, P, and B pictures are different. The data amount of the I picture is about 30 kbytes,
The data amount of the P picture is about 10 to 15 kbytes, and the data amount of the B picture is 0 to about 6 kbytes. On the other hand, the bit rate of the video stream transferred from the transmission medium 120 is constant. As described later, each of the circuits 106 to 109 performs processing for each picture, and the processing time varies depending on the data amount of each picture. Therefore, when the video stream transferred from the transmission medium 120 is directly transferred to each of the circuits 106 to 109, a picture that cannot be processed by each of the circuits 106 to 109 appears. In order to prevent this, by providing a bit buffer 102 as a buffer memory for a video stream transferred from the transmission medium 120, I,
That is, the difference in data amount between the P and B pictures is absorbed.

The picture header detection circuit 104 detects a picture header at the head of each picture of the video stream stored in the bit buffer 102, and determines the picture type (I,
P, B) are detected.

The slice header detection circuit 105 detects a slice header at the head of each slice of the video stream stored in the bit buffer 102. The control core circuit 112 reads a video stream for one picture every one frame period from the bit buffer 102 based on the detection result of the picture header detection circuit 104.

The variable length decoder 106 stores the picture read from the bit buffer 102 into the ROM 11
Variable length decoding is performed based on the Huffman code stored in the Huffman table stored in 0.

The inverse quantization circuit 107 is a variable length decoder 1
06 is subjected to inverse quantization based on the quantization threshold stored in the quantization table stored in the ROM 111, and DCT (Discrete Cosine Transform) is performed on the decoding result.
) Find the coefficient.

The IDCT circuit 108 includes the inverse quantization circuit 10
7 performs the IDCT on the DCT coefficient obtained. The MC circuit 109 performs M processing on the processing result of the IDCT circuit 108.
Perform C (Motion Compensated prediction).

The processing result of the MC circuit 109 is transferred to each area 103a to 103c of the frame buffer 103. In addition, each area 103a to
The data read from 103c is transferred to the MC circuit 109.

The frame buffer 103 is composed of a RAM, and its inside is divided into three areas (a forward reference area 103a, a backward reference area 103b, and a B picture storage area 103c). The forward reference area 103a stores a future I picture or P picture used when the MC circuit 109 performs backward prediction. The backward reference area 103b stores a past I picture or P picture used when the MC circuit 109 performs forward prediction. B pictures are stored in the B picture storage area 103c.

The I picture or P picture stored in the forward reference area 103a and the backward reference area 103b is
Each region 103 is used as base data for performing forward prediction or backward prediction until it is no longer necessary.
a, 103b. Since the B picture stored in the B picture storage area 103c is not treated as the base data, it becomes unnecessary when output to the display 121. In addition, each area | region 103a-103
c is called a plane.

The picture data (video signal) stored in any one of the areas 103a to 103c
Is output to the display 121 provided outside the MPEG video decoder 101 via the MC circuit 109.

For example, when the order of each picture of the original image is configured as shown in FIG. 10A, the order of each picture is rearranged in the MPEG video encoder as shown in FIG. 10B. As shown in FIG. 10C, in the transmission medium 120, each picture is transferred in the order rearranged by the MPEG video encoder. Then, as shown in FIGS.
In the G video decoder 101, the order of the pictures is rearranged so that the order of the pictures in the reproduced image on the display 121 is the same as that of the original image.

The frame buffer 103 stores the MPEG
It is provided to rearrange the order of each picture in the video decoder 101. That is, each circuit 1
When the B picture B3 is processed at 06 to 109 and the processing result is transferred to the B picture storage area 103c, the I picture I2 already stored in the backward reference area 103b is output to the display 121.

Each of the circuits 106 to 109 processes the B picture B4, and stores the processing result in the B picture storage area 10.
During the transfer to 3c, the B picture B3 already stored in the B picture storage area 103c is output to the display 121. As a result, each of the circuits 106 to 109
Is processing the B picture B4, the B picture B3 already stored in the B picture storage area 103c is processed.
, The data of the newly processed B picture B4 is overwritten.

When the P-picture P8 is processed by each of the circuits 106 to 109 and the processing result is transferred to the backward reference area 103b, the B-picture already stored in the B-picture storage area 103c is displayed on the display 121. B4
Is output.

The frame buffer 103 and the bit buffer 102 are provided separately in one RAM in order to reduce the number of components and reduce the component cost of the MPEG video decoder 101.

The Huffman error detection circuit 113 detects an error for each slice by monitoring the decoding process in the variable length decoder 106. That is, the Huffman error detection circuit 113 includes an error in the slice when the data corresponding to the slice is not stored in the Huffman table or when the data corresponding to the slice is inconsistent with the past decoding result. Is determined.

When the Huffman error detection circuit 16 determines that an error is included in the slice, the control core circuit 112 performs the following error processing. Here, a case where an error is included in the slice S1 shown in FIG. 8 will be described as an example. It is assumed that the slice S1 is composed of n macroblocks MB1 to MBn.

(1) The decoding process of the variable length decoder 106 for the slice S1 determined to contain the error is stopped, and the decoding process result of the slice S1 is invalidated.

(2) On the basis of the detection result of the slice header detection circuit 105, the slice buffer S
The slice S2 next to 1 is read. Then, the variable-length decoder 106 performs variable-length decoding of the slice S2.

(3) The MC circuit 109 and the frame buffer 103 are controlled so that the slice S1 stored in the frame buffer 103 is output to the display 121 immediately before the picture containing the slice S1. Are replaced by the corresponding macro blocks MB1 'to MBn'. This operation will be described by taking as an example a case where the order of each picture is configured as shown in FIGS.

(3)-[1] The picture including slice S1 is B
In the case of the picture B3; the picture output to the display 121 immediately before the B picture B3 is the I picture I2. When the B picture B3 is being transferred to the B picture storage area 103c, the I picture I2 has already been stored in the backward reference area 103b.

As shown in FIG. 11, macroblocks MB1 'to MBn' of I picture I2 corresponding to slice S1 of B picture B3 are read from backward reference area 103b. Then, the macroblock MB1 'of the I picture I2
.. MBn 'in the B picture storage area 103c, thereby changing the slice S1 of the B picture B3 to the I picture I2.
Macro blocks MB1 'to MBn'.

(3)-[2] The picture including slice S1 is B
In the case of the picture B4; the picture output to the display 121 immediately before the B picture B4 is the B picture B3. When transferring the B picture B3 to the B picture storage area 103c, the B picture B3 is already stored in the B picture storage area 103c.

As shown in FIG. 12, in the B picture storage area 103c, the macro blocks MB1 'to MB of the B picture B3 corresponding to the slice S1 of the B picture B4.
n 'is not overwritten with the data of B picture B4,
The macro blocks MB1 'to MBn' of the B picture B3 are left as they are. As a result, slice S of B picture B4
1 is the macroblock MB1 'to MB of the B picture B3
n '.

(3)-[3] If the picture including slice S1 is P
In the case of the picture P5; the picture output to the display 121 immediately before the P picture P5 is the B picture B4. The P picture P5 is stored in the forward reference area 103a, and the B picture B4 is stored in the B picture storage area 103c.

As shown in FIG. 13, macroblocks MB1 'to MBn' of B picture B4 corresponding to slice S1 of P picture B5 are read from B picture storage area 103c. Then, the macroblock M of the B picture B4
By writing B1 'to MBn' in the forward reference area 103a, the slice S1 of the P picture P5 is
Macro blocks MB1 'to MBn'.

FIG. 14 shows the internal configuration of the MC circuit 109. The MC circuit 109 includes a backward prediction memory 131, a forward prediction memory 132, an averaging circuit 133, and an addition circuit 13.
4. It is composed of switches SW1 to SW6.

The switch SW6 has two contacts a and b. The contact a is connected to the output of the IDCT circuit 108, the contact b is grounded, and one of the contacts a and b is connected to the input of the adding circuit 134. Is done.

The switch SW1 has four contacts a to d. The contact a is connected to the output of the backward prediction memory 131, the contact b is connected to the output of the averaging circuit 133, and the contact c
Is connected to the output of the forward prediction memory 132, the contact d is grounded, and one of the contacts a to d is connected to the addition circuit 1
34 inputs.

The switch SW2 has two contacts a and b. The contact a is connected to the input of the backward prediction memory 131, and the contact b is connected to the input of the forward prediction memory 132. One of them is connected to the switch SW3.

The switch SW3 has three contacts a to c, and the contact a is a forward reference area 1 of the frame buffer 103.
The switch b is connected to the output of the switch SW5, the contact b is connected to the output of the rear reference area 103b of the frame buffer 103, and the switch S is connected to the output of the switch SW5.
W5 is connected to the contact b, and the contact c is connected to the frame buffer 1
03 and connected to the contact c of the switch SW5.

The switch SW5 has three contacts a to c, and one of the contacts a to c is connected to the display 121.
Connected to. The switch SW4 has three contacts a to c, and the contact a is connected to the input of the front reference area 103a,
The contact b is connected to the input of the rear reference area 103b, the contact c is connected to the input of the B picture storage area 103c, and one of the contacts a to d is connected to the output of the adding circuit 134.

Each of the backward prediction memory 131 and the forward prediction memory 132 stores data for one macroblock. The averaging circuit 133 averages the data read from the backward prediction memory 131 and the forward prediction memory 132.

The MC circuit 109 configured as described above performs the following operation. When the Huffman error detection circuit 113 does not detect an error (normal operation); the switch SW6 is connected to the contact a.

[1] When an I-picture is output from the IDCT circuit 108: The switch SW1 is connected to the contact d, and the switch SW4 is connected to the contact a or the contact b.
The switch SW5 is connected to contacts a to c different from the contacts to which the switch SW4 is connected. For example, when the switch SW4 is connected to the contact a, the switch SW5
Is connected to the contact b or the contact c. Switch SW2, S
W3 may be connected to any contact. As a result, the output of the adder circuit 134 becomes the same as the output of the IDCT circuit 108. The output of the addition circuit 134 is supplied to the forward reference area 103a or the backward reference area 103 via the switch SW4.
b.

-[2] When a P-picture is output from the IDCT circuit 108: The switch SW1 is connected to the contacts c and d corresponding to the macroblock type. -[2]-<1> When the macroblock type is the intra-frame prediction screen; same as-[1] above.

-[2]-<2> When the macroblock type is the forward prediction screen; data of one macroblock read from the rear reference area 103b by connecting the switches SW2 and SW3 to the contact b, respectively. Is stored in the forward prediction memory 132. Then, switch SW1 is connected to contact c.
And the switch SW4 is connected to the contact a or the contact b. The switch SW5 is connected to contacts a to c different from the contacts to which the switch SW4 is connected. as a result,
The adder circuit 134 stores the macroblock data read from the forward prediction memory 132 and the IDCT circuit 108
And the output of. The output of the adding circuit 134 is transferred to the forward reference area 103a or the backward reference area 103b via the switch SW4.

-[3] When a B picture is output from the IDCT circuit 108; the switch SW1 is connected to the contacts a to d corresponding to the macro block type, and the switch SW
4 and SW5 are respectively connected to the contact c. As a result, the output of the adding circuit 134 is transferred to the B picture storage area 103c via the switch SW4.

-[3]-<1> When the macroblock type is the intra-frame prediction screen; connect the switch SW1 to the contact point d. The switches SW2 and SW3 may be connected to any contact. As a result, the output of the adder circuit 134 becomes the same as the output of the IDCT circuit 108.

-[3]-<2> When the macroblock type is the forward prediction screen; data of one macroblock read from the rear reference area 103b by connecting the switches SW2 and SW3 to the contact b, respectively. Is stored in the forward prediction memory 132. Then, switch SW1 is connected to contact c.
Connect to As a result, the adding circuit 134 adds the macroblock data read from the forward prediction memory 132 and the output of the IDCT circuit 108.

-[3]-<3> When the macroblock type is the backward prediction screen; data of one macroblock read from the forward reference area 103a by connecting the switches SW2 and SW3 to the contact a, respectively. Is stored in the backward prediction memory 131. Then, switch SW1 is connected to contact a
Connect to As a result, the addition circuit 134 adds the macroblock data read from the backward prediction memory 131 and the output of the IDCT circuit 108.

-[3]-<4> When the macroblock type is an interpolation prediction screen; first, the switches SW2 and SW3 are respectively connected to the contact b, and one macroblock read from the rear reference area 103b The data for the minute is stored in the forward prediction memory 132. Next, the switches SW2 and S
W3 are respectively connected to the contacts a, and the front reference area 103a
Are stored in the backward prediction memory 131. The averaging circuit 133 is
Reverse prediction memory 131 and forward prediction memory 132
Averaging the data read from. Then, the switch SW1 is connected to the contact b. As a result, the addition circuit 13
4 adds the output of the averaging circuit 133 and the output of the IDCT circuit 108.

When the Huffman error detection circuit 113 detects an error (error processing operation): the switch SW6 is connected to the contact b, and the switch SW2 is connected to the contact a.
The switch SW4 is set to the contacts a to c corresponding to the areas 103a to 103c in which the picture containing the error is stored.
Connect to The switch SW3 is connected to the contacts a to c corresponding to the areas 103a to 103c in which the picture to be output to the display 121 immediately before the picture containing the error is stored. Then, each area 103a-
One macroblock of data read from any one of the memories 103c is stored in the backward prediction memory 131 via the switches SW2 and SW3. Subsequently, the switch SW1 is connected to the contact a. As a result, the addition circuit 1
The output of 34 becomes the same as the macroblock data read from the backward prediction memory 131. The addition circuit 1
The output of the switch 34 is transmitted through the switch SW4 to the areas 103a to 103c in which the picture containing the error is stored.
Transferred to

The above error processing operation is performed by the slice (the slice S1) determined to contain an error.
The process is repeated for each macro block until the corresponding macro block (the macro blocks MB1 'to MBn') of the picture output to the display 121 immediately before the picture containing the slice is replaced.

In the above error processing operation, it is determined that an error is included in the slice S1 shown in FIG.
(D) An example in which the order of each picture is configured as shown in (e) will be described.

-[1] The picture including the slice S1 is B
In the case of picture B3 (see FIG. 11); switch SW4
In the B picture storage area 1 where the B picture B3 is stored.
03c is connected to the contact c. Switch SW3
To the backward reference area 103b in which the I picture I2 is stored.
To the contact b corresponding to. Then, the rear reference area 1
The data of the macro block MB1 'read from the memory 03b is stored in the backward prediction memory 131 via the switches SW2 and SW3. Subsequently, the backward prediction memory 131
Only the data of the macro block MB1 ′ read from the B picture storage area 103 via the addition circuit 134
c. This error processing operation is repeated for each of the macroblocks MB2 'to MBn', and the slice S1 of the B picture B3 is replaced with the macroblocks MB1 'to MBn' of the I picture I2. -[2] The picture including slice S1 is B picture B4
(See FIG. 12); the switch SW4 is connected to the contact point c corresponding to the B picture storage area 103c in which the B picture B4 is stored. Set switch SW3 to B picture B
3 is connected to the contact point c corresponding to the B picture storage area 103c where 3 is stored. Then, the B picture storage area 103
The data of the macro block MB1 ′ read from c.
Reverse prediction memory 1 via switches SW2 and SW3
31. Subsequently, only the data of the macroblock MB1 ′ read from the backward prediction memory 131 is transferred to the B picture storage area 103c via the addition circuit 134. That is, for the macroblock MB1 ', B
The data of the picture B4 is not overwritten, and the macro block MB1 'remains as it is. This error processing operation is repeated for each of the macroblocks MB2 'to MBn', and the slice S1 of the B picture B4 is replaced with the macroblocks MB1 'to MBn' of the B picture B3.

[3] If the picture including slice S1 is P
In the case of picture P5 (see FIG. 13); switch SW4
To the forward reference area 103a in which the P picture B5 is stored.
Is connected to the contact a corresponding to. The switch SW3 is connected to the contact point c corresponding to the B picture storage area 103c where the B picture B4 is stored. Then, the data of the macro block MB1 ′ read from the B picture storage area 103c is stored in the backward prediction memory 131 via the switches SW2 and SW3. Subsequently, the backward prediction memory 1
Only the data of the macro block MB1 'read from the block 31 is transferred to the forward reference area 103a via the adding circuit 134. This error processing operation is performed in each macro block M
B2 'to MBn' are repeated, and the P picture P
5 slices S1 to macroblock M of B picture B4
B1 'to MBn'.

As described above, in the conventional MPEG video decoder 101, the Huffman error detection circuit 113 detects an error for each slice. And slice S1
If an error is included, the above-described error processing ((1) to (3)) is performed.

[0067]

In recent years, there has been a demand for an MPEG video decoder to enhance the accuracy of error detection and error processing to enhance error resistance.

The present invention has been made to satisfy the above-mentioned requirements, and an object of the present invention is to provide an MPEG video decoder capable of enhancing error resistance.

[0069]

According to a first aspect of the present invention, there is provided an MPEG video decoder, comprising: an error detecting means for detecting an error contained in an MPEG video stream; Error processing means for concealing an error by replacing the corresponding data of the picture output to the display immediately before the included B picture, wherein the error detection means restores a motion vector for each macroblock. The point is that the error detection is performed for each macro block by monitoring the motion vector when performing the above. M of claim 2
The PEG video decoder detects an error included in the MPEG video stream for each slice or each macroblock. According to a detection result of the error detection unit, the PEG video decoder determines whether the slice or the macroblock including the error includes the error. Error processing means for concealing an error by replacing a corresponding slice or macroblock of a picture output to the display immediately before the present B picture, wherein the error detection means includes a motion vector for each macroblock. When performing restoration, the gist is to detect an error for each macroblock by monitoring a motion vector. The MPEG video decoder according to claim 3, wherein the error detecting means for detecting an error included in the MPEG video stream for each slice or each macroblock, and the error detecting means detects that an error is included in a certain slice. In this case, the slice containing the error is replaced with the B containing the slice.
The error detection means replaces the corresponding slice of the picture output to the display immediately before the picture by a macro block (MBm) in a slice (S1).
If an error is detected in the slice (S1), all the macroblocks (MBm to MBn) after the macroblock (MBm) in the slice (S1) include the slice (S1). Error processing means for concealing errors by replacing macroblocks (MBm 'to MBn') corresponding to pictures output to the display immediately before the B picture, wherein the error detection means comprises: When restoring a motion vector, the gist is to detect an error for each macroblock by monitoring the motion vector. An MPEG video decoder according to claim 4, wherein a slice header detection circuit detects a slice header attached to the head of each slice of the MPEG video stream, and a variable length based on a Huffman code stored in a Huffman table for the MPEG video stream. A variable-length decoder that performs decoding, an inverse quantization circuit that performs inverse quantization on a decoding result of the variable-length decoder based on a quantization threshold stored in a quantization table to obtain a discrete cosine transform coefficient, A discrete cosine inverse transform circuit that performs an inverse discrete cosine transform on the discrete cosine transform coefficient obtained by the transform circuit, a motion compensated prediction circuit that performs a motion compensated prediction on the processing result of the discrete cosine inverse transform circuit, Each picture of the processing result of the prediction circuit with compensation is temporarily stored, and the order of each picture is motion compensated. A frame buffer for rearranging and outputting via an attached prediction circuit, a motion vector restoration circuit for restoring a motion vector for each macroblock, and error detection for detecting an error included in the MPEG video stream for each slice or each macroblock Means for concealing an error in accordance with the detection result of the error detection means. The error detection means monitors the motion vector when restoring the motion vector for each macroblock, thereby monitoring the error for each macroblock. When the error detection unit detects that an error is included in a certain slice, the error processing unit stops the decoding process of the variable length decoder for the slice (S1) that includes the error. Invalidates the decoding result and uses the detection result of the slice header detection circuit. Causes the variable length decoder to perform variable length decoding of the next slice (S2), and displays the slice (S1) containing the error stored in the frame buffer immediately before the B picture containing the slice. Replaced by the corresponding slice of the picture output to
When the error detection means detects that an error is included in a certain macroblock (MBm) in a certain slice (S1), the error detection means and subsequent macroblocks (MBm) in the slice (S1) in which the error is included are included. The processing of the variable length decoder, the inverse quantization circuit, and the inverse discrete cosine transform circuit for all the macroblocks (MBm to MBn) is stopped to invalidate the processing result, and based on the detection result of the slice header detection circuit, The processing of the slice (S2) is performed by the variable length decoder, the inverse quantization circuit, and the inverse discrete cosine transform circuit, and all the macroblocks (MBm to MBn) stored in the frame buffer include the slice (S1). Corresponding to a macroblock (MBm ′ to MBm ′) of a picture output to the display immediately before the B picture
MBn '). The MPEG video decoder according to claim 5 is the MPEG video decoder according to any one of claims 1 to 4, wherein the error detecting means detects the motion vector when restoring the motion vector for each macroblock. The gist of the present invention is to detect whether an error is included in a macroblock including the motion vector by detecting whether or not the macroblock includes the motion vector. The MPEG video decoder according to claim 6 is any one of claims 1 to 4.
In the MPEG video decoder according to the item, when performing variable length decoding based on a Huffman code instead of the error detection means, a first error detection circuit that performs error detection for each slice by monitoring a decoding process When,
When performing inverse quantization based on a quantization threshold, a second error detection circuit that performs error detection for each macroblock by monitoring the inverse quantization process, and performs a motion vector restoration for each macroblock. In addition, the gist of the present invention is to provide an error detection means including a third error detection circuit for detecting an error for each macroblock by monitoring a motion vector. The MPEG video decoder according to claim 7, wherein the MPEG video decoder according to any one of claims 1 to 4, performs a decoding process when performing a variable length decoding based on a Huffman code instead of the error detection means. the performing error detection for each slice by monitoring 1
An error detection circuit, when performing restoration of the motion vector for each macroblock, further comprising an error detection means and a second error detection circuit which performs error detection for each macro block by monitoring the motion vector Is the gist. The MPEG video decoder according to the eighth aspect is characterized in that:
5. In the MPEG video decoder according to any one of the above items 4, when performing inverse quantization based on a quantization threshold in place of the error detecting means, monitoring an inverse quantization process to provide an error for each macroblock. a first error detection circuit for detecting, when performing restoration of the motion vector for each macroblock, error detection and a second error detection circuit which performs error detection for each macro block by monitoring the motion vector MPEG video decoder with means. An MPEG video decoder according to claim 9, wherein the MPEG video decoder according to any one of claims 1 to 4, wherein the error detection means is replaced with a variable length decoding based on a Huffman code stored in a Huffman table. If the data corresponding to the slice is not stored in the Huffman table or if the data corresponding to the slice is inconsistent with the decoding result in the past, it is determined that the slice contains an error. A first error detection circuit for performing error detection for each slice and a macro for determining whether a DC coefficient among discrete cosine transform coefficients is within a predetermined value when performing inverse quantization based on a quantization threshold value. A second error detection is performed for each block, and if not included, it is determined that an error is included in the macroblock. When performing a motion vector restoration for each circuit and a macroblock, it is detected whether or not the motion vector indicates an inside of the picture, and if the motion vector indicates outside the picture, an error is included in the macroblock including the motion vector. The gist is that an error detecting means including a third error detecting circuit for judging that the error has occurred is provided. An MPEG video decoder according to claim 10, wherein the MPEG video decoder according to any one of claims 1 to 4, wherein the error detection means is replaced with a variable length decoding based on a Huffman code stored in a Huffman table. If the data corresponding to the slice is not stored in the Huffman table or if the data corresponding to the slice is inconsistent with the decoding result in the past, it is determined that the slice contains an error. A first error detection circuit that performs error detection for each slice, and detects whether a motion vector indicates an inside of a picture when restoring a motion vector for each macroblock,
If it indicates outside the picture, it is determined that the macroblock including the motion vector contains an error .
The gist of the present invention is to provide an error detecting means including the second error detecting circuit. An MPEG video decoder according to claim 11, wherein the MPEG video decoder according to any one of claims 1 to 4.
In the G video decoder, when performing inverse quantization based on a quantization threshold in place of the error detection means, whether or not a DC coefficient among discrete cosine transform coefficients is within a predetermined value is detected for each macroblock. If not, the first error detection circuit that determines that an error is included in the macroblock, and when the motion vector is restored for each macroblock, the motion vector indicates the position in the picture. And a second error detection circuit for detecting whether an error is included in the macroblock including the motion vector if the error is outside the picture. Make a summary.

[0070]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows M of the present embodiment.
2 shows a block circuit of the PEG video decoder 1.

The MPEG video decoder 1 includes a bit buffer 2, a frame buffer 3, a picture header detection circuit 4, a slice header detection circuit 5, a variable length decoder 6, an inverse quantization circuit 7, an IDCT (Inverse Discrete Cosine Tr).
ansform) circuit 8, MC (Motion Compensated predict)
ion) circuit 9, ROM (Read Only Memory) 10, 1
1, control core circuit 12, Huffman error detection circuit 13,
It comprises a DC (Direct Current) error detection circuit 41 and a motion area error detection circuit 42. Each circuit 4
13, 13, and 42 are mounted on a one-chip LSI.

The control core circuit 12 includes the circuits 2 to 11, 1
3, 41 and 42 are controlled. The video stream transferred from the transmission medium 20 is input to the bit buffer 2. The transmission medium 20 includes storage media (video CD, CD-ROM, DVD, VTR, etc.),
This includes communication media (such as LAN) and broadcast media (such as terrestrial broadcasting, satellite broadcasting, and CATV).

The bit buffer 2 has a FIFO (First-In-F
transmission media 2 which is constituted by a ring buffer composed of a random access memory (RAM) having an irst-out (RAM) structure.
Video streams transferred from 0 are sequentially stored.

The reason why the bit buffer 2 is provided is as follows.
This is because the data amounts of the I, P, and B pictures are different. The data amount of the I picture is about 30 kbytes, the data amount of the P picture is about 10 to 15 kbytes, and the data amount of the B picture is 0 to about 6 kbytes. On the other hand,
The bit rate of the video stream transferred from the transmission medium 20 is constant. As described later, each circuit 6
9 perform processing for each picture, and the processing time varies depending on the data amount of each picture. Therefore, when the video stream transferred from the transmission medium 20 is directly transferred to each of the circuits 6 to 9, a picture that cannot be processed by each of the circuits 6 to 9 appears. In order to prevent this, by providing the bit buffer 2 as a buffer memory for the video stream transferred from the transmission medium 20, the difference in the data amount of each of the I, P, and B pictures is absorbed. .

The picture header detection circuit 4 detects a picture header at the head of each picture of the video stream stored in the bit buffer 2, and determines the picture type (I, P, B) specified in each picture header. ) Is detected.

The slice header detection circuit 5 detects a slice header attached to the head of each slice of the video stream stored in the bit buffer 2. Control core circuit 12
Is based on the detection result of the picture header detection circuit 4,
A video stream for one picture is read from the bit buffer 2 every frame period.

The variable length decoder 6 performs variable length decoding on the picture read from the bit buffer 2 based on the Huffman code stored in the Huffman table stored in the ROM 10.

The inverse quantization circuit 7 performs inverse quantization on the decoding result of the variable length decoder 6 based on the quantization threshold stored in the quantization table stored in the ROM 11, and performs DCT (Discrete Cosine Transform). ) Find the coefficient.

The IDCT circuit 8 performs IDCT on the DCT coefficient obtained by the inverse quantization circuit 7. The MC circuit 9
MC (Motion Compe
nsatedprediction).

The processing result of the MC circuit 9 is transferred to each area 3a to 3c of the frame buffer 3. The data read from each of the areas 3 a to 3 c of the frame buffer 3 is transferred to the MC circuit 9.

The frame buffer 3 is composed of a RAM, and its inside is divided into three areas (a forward reference area 3a, a backward reference area 3b, and a B picture storage area 3c). The forward reference area 3a stores a future I picture or P picture used when the MC circuit 9 performs backward prediction. The backward reference area 3b stores a past I picture or P picture used when the MC circuit 9 performs forward prediction. B picture storage area 3
B picture is stored in c.

The forward reference area 3a and the rear reference area 3b
Are used as base data for performing forward prediction or backward prediction, and must be kept stored in each of the areas 3a and 3b until they are no longer needed. Since the B picture stored in the B picture storage area 3c is not treated as the base data, it becomes unnecessary when output to the display 21.
Each of the areas 3a to 3c is called a plane.

The picture data (video signal) stored in any one of the areas 3a to 3c is the MC data.
The data is output to a display 21 provided outside the MPEG video decoder 1 via the circuit 9.

For example, when the order of each picture of the original image is configured as shown in FIG. 10A, the order of each picture is rearranged in the MPEG video encoder as shown in FIG. 10B. As shown in FIG. 10C, the pictures are transferred on the transmission medium 20 in the order rearranged by the MPEG video encoder. Then, as shown in FIGS.
In the G video decoder 1, the order of the pictures is rearranged so that the order of the pictures in the reproduced image on the display 21 is the same as that of the original image.

The frame buffer 3 is provided for rearranging the order of each picture in the MPEG video decoder 1. That is, in each of the circuits 6 to 9, B
When processing the picture B3 and transferring the processing result to the B picture storage area 3c, the display 21 outputs the I picture I2 already stored in the backward reference area 3b.

When the circuits 6 to 9 process the B picture B4 and transfer the processing result to the B picture storage area 3c, the display 21 displays the B picture already stored in the B picture storage area 3c. The picture B3 is output. As a result, when each of the circuits 6 to 9 processes the B picture B4, the newly processed B picture B3 is added to the B picture B3 already stored in the B picture storage area 3c.
The data of picture B4 is overwritten.

When the P-picture P8 is processed by each of the circuits 6 to 9 and the processing result is transferred to the backward reference area 3b, the B-picture already stored in the B-picture storage area 3c is displayed on the display 21. B4 is output.

The frame buffer 3 and the bit buffer 2 are provided in a single RAM so as to be divided into regions in order to reduce the number of components and reduce the component cost of the MPEG video decoder 1.

The Huffman error detection circuit 13 detects an error for each slice by monitoring the decoding process in the variable length decoder 6. That is, the Huffman error detection circuit 13 includes an error in the slice when the data corresponding to the slice is not stored in the Huffman table or when the data corresponding to the slice is inconsistent with the past decoding result. Is determined.

When the Huffman error detection circuit 16 determines that an error is included in the slice, the control core circuit 12 performs the following error processing A. Here, a case where an error is included in the slice S1 shown in FIG. 8 will be described as an example. It is assumed that the slice S1 is composed of n macroblocks MB1 to MBn.

A- (1) The decoding process of the variable length decoder 6 for the slice S1 determined to contain the error is stopped, and the decoding process result of the slice S1 is invalidated.

A- (2) The slice S2 next to the slice S1 is read from the bit buffer 2 based on the detection result of the slice header detection circuit 5. Then, it causes the variable length decoder 6 to perform variable length decoding of the slice S2.

A- (3) The MC circuit 9 and the frame buffer 3 are controlled to output the slice S1 stored in the frame buffer 3 to the display 21 immediately before the picture containing the slice S1. Macroblocks MB1 'to MBn' of the current picture. This operation will be described by taking as an example a case where the order of each picture is configured as shown in FIGS.

A- (3)-[1] When the picture including slice S1 is B picture B3; the picture output to display 21 immediately before B picture B3 is I picture I2
It is. When the B picture B3 is transferred to the B picture storage area 3c, the I picture I2 is already
b.

As shown in FIG. 11, macroblocks MB1 'to MBn' of I picture I2 corresponding to slice S1 of B picture B3 are read from rear reference area 3b.
Then, the macroblocks MB1 'to M1 of the I picture I2
By writing Bn 'in the B picture storage area 3c,
The slice S1 of the picture B3 is replaced with the macroblocks MB1 'to MBn' of the I picture I2.

A- (3)-[2] When the picture including slice S1 is B picture B4; the picture output to display 21 immediately before B picture B4 is B picture B3
It is. When transferring the B picture B3 to the B picture storage area 3c, the B picture B3 is already stored in the B picture storage area 3c.

As shown in FIG. 12, in the B picture storage area 3c, the macro blocks MB1 'to MBn' of the B picture B3 corresponding to the slice S1 of the B picture B4.
, The data of the B picture B4 is not overwritten, and the macroblocks MB1 'to MBn' of the B picture B3 are left as they are. As a result, the slice S1 of the B picture B4 is replaced with the macro blocks MB1 'to MBn' of the B picture B3.

A- (3)-[3] When the picture including slice S1 is P picture P5; the picture output to display 21 immediately before P picture P5 is B picture B4
It is. The P picture P5 is stored in the forward reference area 3a, and the B picture B4 is stored in the B picture storage area 3c.

As shown in FIG. 13, macroblocks MB1 'to MBn' of B picture B4 corresponding to slice S1 of P picture B5 are read from B picture storage area 3c. Then, the macroblock MB of the B picture B4
By writing 1 'to MBn' in the forward reference area 3a,
The slice S1 of the P picture P5 is replaced with the macroblocks MB1 'to MBn' of the B picture B4.

The DC error detection circuit 41 detects an error for each macro block by monitoring the inverse quantization processing in the inverse quantization circuit 7. That is, the DC error detection circuit 41 detects, for each macroblock, whether or not a DC (Direct Current) coefficient among the DCT coefficients obtained by the inverse quantization circuit 7 falls within a predetermined value. , It is determined that the macroblock contains an error. Note that the DC coefficient is the DCT coefficient (0,
0) component.

The motion area error detection circuit 42 detects an error for each macro block by monitoring the motion vector restored by the motion vector restoration circuit 43 in the MC circuit 9. For example, as shown in FIG. 2, the motion vector restoration circuit 43 restores the motion vectors 52 to 56 for the macroblocks MB11 to MB15 constituting the slice S3 included in the picture 51, respectively. The motion area error detection circuit 42 detects whether each of the motion vectors 52 to 56 indicates the inside of the picture 51, and
If the value is other than 1, it is determined that an error is included in the macroblock including the motion vector. Here, the motion vectors 52 to 55 show the inside of the picture 51, but the motion vector 56 shows the outside of the picture 51. Accordingly, the motion area error detection circuit 42
It is determined that an error is included in the macroblock MB15 including the motion vector 56.

The causes of errors detected by the DC error detection circuit 41 or the motion area error detection circuit 42 include the following. A case where the video stream transferred from the transmission medium 20 is not originally encoded according to the MPEG video part standard.

A case where an error occurs in an arbitrary bit of a video stream transferred from the transmission medium 20 due to some accident occurring in the transmission medium 20. For example,
When a video CD or DVD is used as the transmission medium 20, an error may occur in an arbitrary bit of a video stream read from the disk due to a scratch on the disk. In communication media and broadcast media, errors may occur in arbitrary bits of a transmitted video stream due to noise.

When the DC error detection circuit 41 or the motion area error detection circuit 42 determines that the macroblock contains an error, the control core circuit 12
The following error processing B is performed. Here, a case where an error is included in the macroblock MBm in the slice S1 shown in FIG. 8 will be described as an example.

B- (1) The processing of each of the circuits 6 to 8 for all the macro blocks MBm to MBn after the macro block MBm in the slice S1 determined to contain an error is stopped, and MBm to MBn
Invalidates the processing result of.

B- (2) The slice S2 next to the slice S1 is read from the bit buffer 2 based on the detection result of the slice header detection circuit 5. Then, each of the circuits 6 to 8 performs the processing of the slice S2.

B- (3) The MC circuit 9 and the frame buffer 3 are controlled so that each of the macro blocks MBm to MBn stored in the frame buffer 3 is
The macroblocks corresponding to the macroblocks MBm 'to MBn' which are output to the display 21 immediately before the picture including Bm to MBn are replaced. This operation will be described by taking as an example a case where the order of each picture is configured as shown in FIGS.

B- (3)-[1] Macro blocks MBm to MB
n is a B picture B3; as shown in FIG. 3, macroblocks MBm to MB of the B picture B3
n of the I-picture I2 corresponding to the macroblock MBm ′
... MBn ′ are read from the backward reference area 3b. And
By writing the macroblocks MBm 'to MBn' of the I picture I2 into the B picture storage area 3c, the macroblocks MBm to MBn of the B picture B3 are stored in the I picture I2.
Of macro blocks MBm 'to MBn'.

B- (3)-[2] Macro blocks MBm to MB
When the picture including n is a B picture B4; as shown in FIG. 4, in the B picture storage area 3c, for the macro blocks MBm 'to MBn' of the B picture B3 corresponding to the macro blocks MBm to MBn of the B picture B4. Without overwriting the data of B picture B4,
3 macroblocks MBm 'to MBn' are left as they are. As a result, the macroblock MBm of the B picture B4
MBn is the macroblock MBm 'of the B picture B3.
MBn '.

B- (3)-[3] Macro blocks MBm to MB
n is a P picture P5; as shown in FIG. 5, macro blocks MBm to MB of a P picture B5
n macroblock MBm ′ of B picture B4 corresponding to n
.About.MBn 'is read from the B picture storage area 3c. Then, the macro blocks MBm ′ to MB of the B picture B4
By writing n ′ into the forward reference area 3a, the macroblocks MBm to MBn of the P picture P5 are
Of macro blocks MBm 'to MBn'.

FIG. 6 shows the internal configuration of the MC circuit 9. M
The C circuit 9 includes a backward prediction memory 31, a forward prediction memory 32, an averaging circuit 33, an adding circuit 34, and switches SW1 to SW1.
SW6 and a motion vector restoration circuit 43.

The switch SW6 has two contacts a and b. The contact a is connected to the output of the IDCT circuit 8 and the contact b
Is grounded, and one of the contacts a and b is connected to the input of the adding circuit 34.

The switch SW1 has four contacts a to d. The contact a is connected to the output of the backward prediction memory 31,
The contact b is connected to the output of the averaging circuit 33, the contact c is connected to the output of the forward prediction memory 32, the contact d is grounded, and one of the contacts a to d is connected to the input of the adding circuit 34. You.

The switch SW2 has two contacts a and b. The contact a is connected to the input of the backward prediction memory 31,
The contact b is connected to the input of the forward prediction memory 32, and one of the contacts a and b is connected to the switch SW3.

The switch SW3 has three contacts a to c. The contact a is connected to the output of the front reference area 3a of the frame buffer 3 and to the contact a of the switch SW5, and the contact b is connected to the rear of the frame buffer 3. Reference area 3b
Of the switch SW5, and the contact c is connected to the output of the B picture storage area 3c of the frame buffer 3 and to the contact c of the switch SW5.

The switch SW5 has three contacts a to c, and any one of the contacts a to c is connected to the display 21. The switch SW4 has three contacts a to c, the contact a is connected to the input of the front reference area 3a, the contact b is connected to the input of the rear reference area 3b, and the contact c is connected to the input of the B picture storage area 3c. Then, one of the contacts a to c is connected to the output of the adding circuit 34.

Each of the backward prediction memory 31 and the forward prediction memory 32 stores data for one macroblock. The averaging circuit 33 averages data read from the backward prediction memory 31 and the forward prediction memory 32.

The motion vector restoration circuit 43 determines whether each area 3a
The data for one macro block read from any one of the macro blocks 3 to 3c is input via the switch SW3, and the motion vector of the macro block is restored.

The MC circuit 9 configured as described above performs the following operation. When none of the error detection circuits 13, 41, 42 detects an error (normal operation); the switch SW6 is connected to the contact a.

-[1] When an I picture is output from the IDCT circuit 8: The switch SW1 is connected to the contact d, and the switch SW4 is connected to the contact a or the contact b. The switch SW5 is connected to contacts a to c different from the contacts to which the switch SW4 is connected. For example, switch SW4
Is connected to the contact a, the switch SW5 is connected to the contact b or the contact c. The switches SW2 and SW3 may be connected to any contact. As a result, the output of the adding circuit 34 becomes the same as the output of the IDCT circuit 8. The output of the adding circuit 34 is transferred to the front reference area 3a or the rear reference area 3b via the switch SW4.

-[2] When a P picture is output from the IDCT circuit 8; Connect the switch SW1 to the contacts c and d corresponding to the macroblock type. -[2]-<1> When the macroblock type is the intra-frame prediction screen; same as-[1] above.

-[2]-<2> When the macroblock type is the forward prediction screen; the switches SW2 and SW3 are respectively connected to the contact b, and 1 is read from the rear reference area 3b.
Data of macroblocks are stored in the forward prediction memory 3
2 is stored. Then, switch SW1 is connected to contact c, and switch SW4 is connected to contact a or contact b.
The switch SW5 is connected to contacts a to c different from the contacts to which the switch SW4 is connected. As a result, the addition circuit 34 adds the macroblock data read from the forward prediction memory 32 and the output of the IDCT circuit 8. The output of the adding circuit 34 is transferred to the front reference area 3a or the rear reference area 3b via the switch SW4.

[3] When a B picture is output from the IDCT circuit 8; the switch SW1 is connected to the contacts a to d corresponding to the macroblock type, and the switches SW4 and SW4 are connected.
SW5 is connected to each of the contacts c. As a result, the output of the adding circuit 34 is transferred to the B picture storage area 3c via the switch SW4.

-[3]-<1> When the macroblock type is the intra-frame prediction screen; connect the switch SW1 to the contact point d. The switches SW2 and SW3 may be connected to any contact. As a result, the output of the adding circuit 34 becomes the same as the output of the IDCT circuit 8.

-[3]-<2> When the macroblock type is a forward prediction screen; switches SW2 and SW3 are respectively connected to the contact b, and 1 is read from the rear reference area 3b
Data of macroblocks are stored in the forward prediction memory 3
2 is stored. Then, the switch SW1 is connected to the contact c. As a result, the addition circuit 34 outputs the forward prediction memory 3
2 and the macroblock data read from IDC
The output of the T circuit 8 is added.

-[3]-<3> When the macroblock type is the backward prediction screen; 1 is read from the forward reference area 3a by connecting the switches SW2 and SW3 to the contact a, respectively.
Data of macroblocks are stored in the backward prediction memory 3
1 is stored. Then, the switch SW1 is connected to the contact a. As a result, the addition circuit 34 outputs the backward prediction memory 3
1 and the macroblock data read from IDC
The output of the T circuit 8 is added.

-[3]-<4> When the macroblock type is an interpolation prediction screen; first, the switches SW2 and SW3 are respectively connected to the contact b, and one macroblock read from the rear reference area 3b The data for the minute is stored in the forward prediction memory 32. Next, the switches SW2 and SW3 are connected to the contacts a, respectively, and the data for one macroblock read from the forward reference area 3a is stored in the backward prediction memory 31. The averaging circuit 33 averages data read from the backward prediction memory 31 and the forward prediction memory 32. Then, the switch SW1 is connected to the contact b. As a result, the adding circuit 34 adds the output of the averaging circuit 33 and the output of the IDCT circuit 8.

When any one of the error detection circuits 13, 41 and 42 detects an error (error processing operation); the switch SW6 is connected to the contact b, and the switch SW
2 is connected to the contact a. The switch SW4 is connected to the contacts a to c corresponding to the areas 3a to 3c in which the picture containing the error is stored. The switch SW3 is connected to the contacts a to c corresponding to the areas 3a to 3c in which the picture to be output to the display 21 immediately before the picture containing the error is stored. And each area 3a ~
The data for one macroblock read out from any one of 3c is stored in the backward prediction memory 31 via the switches SW2 and SW3. Then, switch SW
1 is connected to the contact a. As a result, the output of the adder circuit 34 becomes the same as the data of the macro block read from the backward prediction memory 31. The output of the adding circuit 34 is
Via the switch SW4, the data is transferred to the areas 3a to 3c in which the picture containing the error is stored.

-[1] When the Huffman error detection circuit 13 detects an error; the above-described error processing operation is performed on the slice determined to contain an error (the slice S
1) corresponds to the corresponding macroblock (the macroblocks MB1 ′ to MB1) of the picture output to the display 21 immediately before the picture containing the slice.
Repeatedly for each macroblock until replaced by n ').

In the above error processing operation, it is determined that an error is included in the slice S1 shown in FIG.
(D) An example in which the order of each picture is configured as shown in (e) will be described.

-[1]-<1> When the picture including slice S1 is B picture B3 (see FIG. 11); switch SW
4 is connected to the contact point c corresponding to the B picture storage area 3c in which the B picture B3 is stored. Switch SW3
It connects to the contact point b corresponding to the backward reference area 3b where the I picture I2 is stored. Then, the data of the macro block MB1 'read from the backward reference area 3b is stored in the backward prediction memory 31 via the switches SW2 and SW3. Subsequently, only the data of the macro block MB1 'read from the backward prediction memory 31 is transferred to the B picture storage area 3c via the addition circuit. This error processing operation is repeated for each of the macro blocks MB2 'to MBn', and the slice S1 of the B picture B3 is
Replaced by macroblocks MB1 'to MBn' of picture I2.

-[1]-<2> When the picture including slice S1 is B picture B4 (see FIG. 12); switch SW
4 is connected to the contact point c corresponding to the B picture storage area 3c in which the B picture B4 is stored. Switch SW3
It is connected to the contact point c corresponding to the B picture storage area 3c where the B picture B3 is stored. Then, the data of the macroblock MB1 ′ read from the B picture storage area 3c is stored in the backward prediction memory 31 via the switches SW2 and SW3. Subsequently, only the data of the macro block MB1 'read from the backward prediction memory 31 is transferred to the B picture storage area 3c via the addition circuit. That is, the data of the B picture B4 is not overwritten on the macroblock MB1 ', and the macroblock MB1' is not overwritten.
1 'will remain as it is. This error processing operation is repeated for each of the macroblocks MB2 'to MBn', and the slice S1 of the B picture B4 is replaced with the macroblocks MB1 'to MBn' of the B picture B3.

-[1]-<3> When the picture including slice S1 is P picture P5 (see FIG. 13); switch SW
4 is connected to the contact point a corresponding to the forward reference area 3a in which the P picture B5 is stored. The switch SW3 is connected to the contact c corresponding to the B picture storage area 3c where the B picture B4 is stored. Then, the B picture storage area 3c
The data of the macro block MB1 'read out from the backward prediction memory 31 via the switches SW2 and SW3.
To be stored. Subsequently, only the data of the macro block MB1 ′ read from the backward prediction memory 31 is transferred to the forward reference area 3a via the adder circuit. This error processing operation is repeated for each of the macro blocks MB2 'to MBn', and the slice S1 of the P picture P5 is
Replaced by macroblocks MB1 'to MBn' in picture B4.

[2] When the DC error detection circuit 41 or the motion area error detection circuit 42 detects an error; the above-described error processing operation is performed in the slice (the slice S1) determined to contain an error. Macroblocks (the macroblocks MBm to MBn) after the macroblock (the macroblock MBm) are the macros corresponding to the macros to be output to the display 21 immediately before the picture containing the macroblock. The process is repeated for each macro block until the block is replaced by the block (the macro blocks MBm 'to MBn').

In the above error processing operation, it is determined that an error is included in the macro block MBm in the slice S1 shown in FIG. 8, and the order of each picture is configured as shown in FIGS. 10 (d) and 10 (e). The following is an example of a case in which this is done.

-[2]-<1> When the picture including the macro block MBm is the B picture B3 (see FIG. 3); the switch SW4 is set to the contact c corresponding to the B picture storage area 3c where the B picture B3 is stored. Connect to Switch SW
3 is connected to the contact point b corresponding to the backward reference area 3b where the I picture I2 is stored. And the rear reference area 3b
The data of the macro block MBm ′ read out from the backward prediction memory 31 via the switches SW2 and SW3.
To be stored. Subsequently, only the data of the macroblock MBm ′ read from the backward prediction memory 31 is transferred to the B picture storage area 3c via the addition circuit. This error processing operation is performed by referring to each of the macro blocks MBm + 1 'to M
The processing is repeated for Bn ', and the macroblocks MBm to MBn of the B picture B3 are replaced with the macroblocks MBm' to MBn 'of the I picture I2.

-[2]-<2> When the picture including the macro block MBm is the B picture B4 (see FIG. 4); the switch SW4 is set to the contact c corresponding to the B picture storage area 3c where the B picture B4 is stored. Connect to Switch SW
3 is connected to the contact point c corresponding to the B picture storage area 3c where the B picture B3 is stored. Then, the data of the macro block MBm ′ read from the B picture storage area 3c is stored in the backward prediction memory 31 via the switches SW2 and SW3. Subsequently, the backward prediction memory 3
Only the data of the macro block MBm 'read from 1 is transferred to the B picture storage area 3c via the addition circuit 34. That is, for the macroblock MBm ', B
The data of the picture B4 is not overwritten, and the macroblock MBm 'remains as it is. This error processing operation is repeated for each of the macroblocks MBm + 1 'to MBn' to obtain the macroblock MB of the B picture B4.
m to MBn are the macroblocks MBm 'of the B picture B3
~ MBn '.

-[2]-<3> When the picture including the macro block MBm is the P picture P5 (see FIG. 5); the switch SW4 is set to the contact point a corresponding to the forward reference area 3a where the P picture B5 is stored. Connecting. Switch SW3
It is connected to the contact point c corresponding to the B picture storage area 3c where the B picture B4 is stored. Then, the data of the macro block MBm ′ read from the B picture storage area 3c is stored in the backward prediction memory 31 via the switches SW2 and SW3. Subsequently, only the data of the macro block MBm ′ read from the backward prediction memory 31 is transferred to the forward reference area 3a via the adder circuit. This error processing operation is performed by referring to each of the macro blocks MBm + 1 'to M
This process is repeated for Bn 'to replace the macroblocks MBm to MBn of the P picture P5 with the macroblocks MBm' to MBn 'of the B picture B4.

As described above, according to the present embodiment, the following operations and effects can be obtained. (1) The Huffman error detection circuit 13 performs error detection for each slice. When an error is included in a certain slice S1, the error processing A is performed.

(2) According to the above (1), the slice S1 containing the error stored in the frame buffer 3 is placed on the display 21 immediately before the picture containing the slice S1.
Macroblock MB of picture output to
1 'to MBn'. In each picture successively output to the display 21, a certain picture is very similar to a picture before and after it, and only a part of the picture is different.
That is, the slice S1 and the macroblocks MB1 'to MB1
There is a high possibility that n 'has the same data content. Therefore,
The slice S1 including the error is replaced with the macroblock MB1 '
In most cases, the error can be hidden by replacing with MBn '.

(3) The DC error detection circuit 41 and the motion area error detection circuit 42 perform error detection for each macro block. When an error is included in a certain macro block MBm in a certain slice S1, the error processing B is performed.

(4) According to the above (3), all macro blocks MBm to M after the macro block MBm in the slice S1 containing an error stored in the frame buffer 3
Bn is set to 1 of the picture containing the macroblock MBm.
It can be replaced by the corresponding macroblock MBm 'to MBn' of the picture output to the display 21 immediately before. It is highly possible that the macro blocks MBm to MBn and the macro blocks MBm 'to MBn' have the same data content. Therefore, all the macroblocks M after the macroblock MBm in the slice S1 including the error
If Bm to MBn are replaced by macroblocks MBm 'to MBn', errors can be hidden in most cases.

(5) In the conventional example shown in FIG.
Only the operation and effect of (2) can be obtained. On the other hand, in the present embodiment, the operations and effects of the above (3) and (4) can be obtained in addition to the above (1) and (2). Therefore, according to the present embodiment, it is possible to increase the accuracy of error detection as compared with the conventional example, and it is possible to enhance error tolerance.

(6) In the error processing B, the error processing is performed not only on the macroblock MBm containing the error but also on all the macroblocks MBm to MBn after the macroblock MBm in the slice S1 for the following reason. .

If any bit of the video stream transferred from the transmission medium 20 has an error due to some accident occurring in the transmission medium 20, the error state is hardly released in the middle of the slice.

For example, as shown in FIG. 7, (a): "0
The code of the video stream “00100101101001...” Is (b): “000110101101”.
001... Will be described as an example. Here, the Huffman code of the Huffman table is “11”: A, “10”:
B, "01": C, "001": D, "0001":
E, other codes: NG. Then, the correct video stream (a) is represented by “EDCBB” in Huffman code.
In contrast, the incorrect video stream (b) is represented as "EBBACD ...". That is, even if a certain bit of the video stream is incorrect, the video stream matches one of the Huffman codes.

In such a case, the Huffman error detection circuit 13 cannot detect an error, and the variable length decoder 6 continues to output random decoding results. The decoding result of the variable length decoder 6 also includes information on DC coefficients and motion vectors. for that reason,
If the decoding result of the variable length decoder 6 is incorrect, DC
Error detection circuit 41 and motion area error detection circuit 42
Cannot detect the error.

That is, each of the error detection circuits 41 and 42
Even if no error is detected for the macro block MBm + 1 next to the macro block MBm containing the error, the macro block MBm + 1 may include the error. Therefore, by performing error processing not only on the macroblock MBm containing the error but also on all the subsequent macroblocks MBm + 1 to MBn in the slice S1, it is possible to reliably detect an error.

The embodiments described above may be modified as follows, and the same operation and effect can be obtained in such a case. [1] Any one of the error detection circuits 13, 41, 42 is omitted. In addition, the Huffman error detection circuit 13 is omitted, and only one of the error detection circuits 41 and 42 is provided. In these cases, although the accuracy of error detection and error tolerance are reduced as compared to the above embodiment, they can be enhanced as compared with the conventional example.

[2] The error processing operation (-[1],
-[2]), switch SW2 is connected to contact b. Then, the data of one macroblock read from any one of the areas 3a to 3c is transferred to the switch S
The data is stored in the forward prediction memory 32 via W2 and SW3. Subsequently, the switch SW1 is connected to the contact c. As a result, the output of the adder circuit 34 becomes the same as the macroblock data read from the forward prediction memory 32.

[3] The above embodiment is replaced with software processing using a CPU. That is, each circuit (4
, 9, 12, 13, 41, 42) by C
Replace with software-like signal processing using PU.

While the embodiments have been described above, technical ideas other than the claims that can be grasped from the embodiments will be described below together with their effects. (A) The MPEG video decoder according to claim 4, wherein each circuit except a frame buffer is formed on one chip.

In this way, the entire MPEG video decoder can be downsized. (B) The MPEG video decoder according to claim 4, further comprising a bit buffer for temporarily storing the MPEG video stream and then transferring the MPEG video stream to a variable length decoder.
EG video decoder.

In this way, it is possible to absorb the difference in the data amount of each picture transferred from the transmission medium. (C) In the MPEG video decoder described in (b) above, the bit buffer and the frame buffer are
MPEG video decoder composed of AM.

In this way, the number of components constituting the MPEG video decoder is reduced, so that the cost can be reduced. By the way, in this specification, a member according to the configuration of the invention is defined as follows.

(A) The error detecting means comprises at least one of the error detecting circuits 13, 41 and 42. (B) The error processing means includes the MC circuit 9 and the control core circuit 12.

[0157]

As described above in detail, according to the present invention, an MPEG video decoder capable of enhancing error resilience is provided.
It can provide over da.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram of one embodiment.

FIG. 2 is an explanatory diagram for explaining the operation of the embodiment.

FIG. 3 is an explanatory diagram for explaining the operation of the embodiment.

FIG. 4 is an explanatory diagram for explaining the operation of the embodiment;

FIG. 5 is an explanatory diagram for explaining the operation of the embodiment.

FIG. 6 is a main part block circuit diagram of one embodiment.

FIG. 7 is an explanatory diagram for explaining the operation of the embodiment;

FIG. 8 is an explanatory diagram for explaining the operation of one embodiment and a conventional example.

FIG. 9 is a block circuit diagram of a conventional example.

FIG. 10 is an explanatory diagram for explaining the operation of one embodiment and a conventional example.

FIG. 11 is an explanatory diagram for explaining the operation of one embodiment and a conventional example.

FIG. 12 is an explanatory diagram for explaining the operation of one embodiment and a conventional example.

FIG. 13 is an explanatory diagram for explaining the operation of one embodiment and a conventional example.

FIG. 14 is a main part block circuit diagram of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 3 ... Frame buffer 5 ... Slice header detection circuit 6 ... Variable length decoder 7 ... Inverse quantization circuit 8 ... IDCT circuit 9 ... MC circuit 12 ... Control core circuit 13 ... Huffman error detection circuit 41 ... DC error detection circuit 42 ... Motion area Error detection circuit 43: Motion vector restoration circuit

Continuation of the front page (56) References JP-A-6-268992 (JP, A) JP-A-6-105285 (JP, A) JP-A-5-252055 (JP, A) JP-A-4-233388 (JP) , A) JP-A-7-38888 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N ^7/ 24-7/68

Claims (11)

(57) [Claims] 1. An error detecting means for detecting an error contained in an MPEG video stream, and data containing the error is sent to a display immediately before the B picture containing the error according to a detection result of the error detecting means. Error processing means for concealing an error by replacing the data with corresponding data of an output picture, wherein the error detection means monitors a motion vector when performing a motion vector restoration for each macro block. MPEG video decoder that performs error detection for each block. 2. An error detecting means for detecting an error contained in an MPEG video stream for each slice or each macroblock, and a slice or a macroblock containing an error is detected according to a detection result of the error detecting means. Error processing means for concealing an error by replacing a corresponding slice or macroblock of a picture output to the display immediately before the present B picture, the error detection means comprising: An MPEG video decoder that monitors a motion vector and performs error detection for each macroblock when performing restoration. 3. An error detecting means for detecting an error included in an MPEG video stream for each slice or each macroblock, and when the error detecting means detects that an error is included in a certain slice, The slice containing the error is replaced with the corresponding slice of the picture output to the display immediately before the B picture containing the slice, and the error detecting means replaces a macro in a slice (S1) When it is detected that an error is included in the block (MBm), all the macroblocks (MBm to M) after the macroblock (MBm) in the slice (S1) are detected.
Error processing means for concealing an error by replacing Bn) with a corresponding macroblock (MBm 'to MBn') of a picture to be output to a display immediately before a B picture including the slice (S1) An MPEG video decoder, wherein the error detection means monitors a motion vector and performs error detection for each macroblock when restoring a motion vector for each macroblock. 4. A slice header detection circuit for detecting a slice header attached to the beginning of each slice of the MPEG video stream, and a variable for performing variable length decoding on the MPEG video stream based on a Huffman code stored in a Huffman table. A long decoder, an inverse quantization circuit for performing inverse quantization on the decoding result of the variable length decoder based on the quantization threshold stored in the quantization table to obtain a discrete cosine transform coefficient, and an inverse quantization circuit A discrete cosine inverse transform circuit that performs inverse discrete cosine transform on the discrete cosine transform coefficient, a motion compensated prediction circuit that performs motion compensated prediction on the processing result of the discrete cosine inverse transform circuit, and a motion compensated prediction circuit Are temporarily stored, and the order of each picture is determined via the prediction circuit with motion compensation. A frame buffer for replacing and outputting, a motion vector restoration circuit for restoring a motion vector for each macroblock, an error detection means for detecting an error contained in the MPEG video stream for each slice or each macroblock, and an error detection means Error processing means for concealing an error according to the detection result of the error detection means. The error detection means performs error detection for each macro block by monitoring the motion vector when restoring a motion vector for each macro block. When the error detection unit detects that an error is included in a certain slice, the error detection unit stops the decoding process of the variable length decoder for the slice (S1) including the error and invalidates the decoding process result. The next slice based on the detection result of the slice header detection circuit. S2)
Of the slice containing the error stored in the frame buffer (S
1) is replaced with a corresponding slice of a picture to be output to a display immediately before a B picture including the slice, and the error detecting means determines that a certain macroblock (MBm) in a certain slice (S1) If it is detected that the macro block contains an error, the variable length decoder and the inverse quantization circuit for all macro blocks (MBm to MBn) after the macro block (MBm) in the slice (S1) containing the error , The processing of the discrete cosine inverse transform circuit is stopped to invalidate the processing result, and the processing of the next slice (S2) is performed based on the detection result of the slice header detection circuit, using a variable length decoder, an inverse quantization circuit, a discrete cosine circuit. The slice (S1) includes all the macroblocks (MBm to MBn) stored in the frame buffer, which are performed by the inverse conversion circuit. The corresponding macroblock (MBm′〜) of the picture output to the display immediately before the rare B picture
MPEG video decoder to replace MBn '). 5. The M according to claim 1, wherein
In the PEG video decoder, when restoring a motion vector for each macroblock, the error detection means detects whether or not the motion vector indicates an inside of a picture. An MPEG video decoder that determines that an error is included in the included macroblock. 6. The M according to claim 1, wherein:
In the PEG video decoder, when performing the variable length decoding based on the Huffman code instead of the error detecting means,
A first error detection circuit that detects an error for each slice by monitoring a decoding process; and, when performing inverse quantization based on a quantization threshold, monitors an error in each macroblock by monitoring the inverse quantization process. An error detection circuit comprising: a second error detection circuit for performing detection; and a third error detection circuit for performing error detection for each macroblock by monitoring a motion vector when restoring a motion vector for each macroblock. MPEG video decoder with means. 7. The M according to claim 1, wherein:
In the PEG video decoder, when performing the variable length decoding based on the Huffman code instead of the error detecting means,
A first error detection circuit that performs error detection for each slice by monitoring a decoding process, and performs an error detection for each macroblock by monitoring a motion vector when a motion vector is restored for each macroblock. An MPEG video decoder provided with an error detection means including a second error detection circuit. 8. The M according to claim 1, wherein:
In the PEG video decoder, a first error detection circuit that performs error detection for each macroblock by monitoring the inverse quantization process when performing inverse quantization based on a quantization threshold in place of the error detection means. An MPEG video decoder comprising: an error detection unit comprising: a second error detection circuit that monitors a motion vector when a motion vector is restored for each macroblock and detects an error for each macroblock. 9. The M according to claim 1, wherein:
In the PEG video decoder, when performing variable-length decoding based on the Huffman code stored in the Huffman table instead of the error detection means, when data corresponding to a slice is not stored in the Huffman table,
When data corresponding to a slice is inconsistent with a past decoding result, a first error detection circuit that performs error detection for each slice by determining that an error is included in the slice; When performing inverse quantization based on each of the discrete cosine transform coefficients, it is detected whether or not the DC coefficient is within a predetermined value for each macroblock, and if not, an error is included in the macroblock. A second error detection circuit that determines that the motion vector is present, and, when restoring a motion vector for each macroblock, detects whether the motion vector indicates an inside of a picture. MPEG video data provided with error detection means comprising a third error detection circuit for determining that an error is included in a macroblock including Over da. 10. The MPEG video decoder according to claim 1, wherein, when performing a variable length decoding based on a Huffman code stored in a Huffman table, instead of said error detecting means. , If the data corresponding to the slice is not stored in the Huffman table,
If the data corresponding to the slice is inconsistent with the past decoding result, it is determined that an error is included in the slice, and a first error detection circuit that performs error detection for each slice is provided. When restoring a motion vector for each macroblock, it is detected whether or not the motion vector indicates the inside of the picture. If the motion vector indicates outside the picture, an error is included in the macroblock including the motion vector. An MPEG video decoder comprising an error detection means including a second error detection circuit for determining that there is an error. 11. The MPEG video decoder according to claim 1, wherein, when performing inverse quantization based on a quantization threshold instead of said error detecting means, a discrete cosine transform coefficient is used. A first error detection circuit for detecting whether or not the DC coefficient is within a predetermined value for each macroblock, and if not, determining that an error is included in the macroblock; When the motion vector is restored, it is detected whether the motion vector indicates the inside of the picture. If the motion vector indicates the outside of the picture, it is determined that an error is included in the macroblock including the motion vector. An MPEG video decoder provided with an error detection means including a second error detection circuit.