JP3200847B2 - Hybrid encoder - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an encoder for detecting a rotation angle by a digital signal.

[Prior Art] It is well known that there are an increment type and an absolute type as encoders for detecting a rotation angle of a rotating shaft with an n-bit digital signal.

That is, the increment type encoder includes a disk directly connected to the rotating shaft and having concentric slits formed at equal intervals, and a light emitting element and a light receiving element installed on both sides of the disk.

When the rotation shaft rotates, the disk also rotates, and the light receiving element outputs a number of pulses proportional to the rotation angle.

Therefore, it is possible to detect the rotation angle of the rotating shaft by counting the pulses with a counter.

However, in this type of encoder, since the absolute value of the rotation angle of the rotating shaft is held in the counter, information is lost when the power of the counter is turned off.

On the other hand, in the case of an absolute type encoder, a disk is provided directly connected to the rotating shaft and has a pattern of slits corresponding to each bit on concentric circles of the number corresponding to the number of bits. It has a light emitting element and a light receiving element installed.

When the rotation shaft rotates, the disk also rotates, and a logic signal corresponding to each bit is output from the light receiving element, so that the rotation angle of the rotation shaft can be directly known.

However, in the encoder of this type, if the detection accuracy is increased, the pattern formed on the disk becomes complicated, so that not only the size of the disk is increased, but also the cost is increased. If the rotation speed is further increased, the output signal of the lower bit has a relatively higher frequency, and thus erroneous detection occurs due to the influence of the frequency characteristics of the signal processing circuit.

In order to solve these problems, the upper m bits of the n-bit detection signal are detected by an absolute value,
A hybrid encoder that detects the lower (nm) bits by an increment value has been proposed (Japanese Patent Laid-Open No. 1-30).
No. 5316).

[Problems to be Solved by the Invention] However, in the hybrid encoder, the lower bits are the count value of the counter, but the count value when the power of the counter is turned on is generally undefined,
Appears as a detection error.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and provides an initial value in accordance with an absolute value of a rotation angle and a value of a timing signal that can be immediately detected when the power is turned on. It is an object of the present invention to provide a hybrid encoder capable of reducing the error to a quarter of the related art.

[Means for Solving the Problem] A configuration of a hybrid encoder for solving the above problem is shown in FIG.

That is, the upper m bits (1 <m) of the n-bit digital signal value output as the detected value of the rotation angle of the rotation axis
A disk 100 having a concentric pattern for outputting the rotation angle of <n) as an absolute value and outputting a number of pulses proportional to the rotation angle of the rotation shaft.
Reading means 101 for reading a pattern formed on the disk 100; signal processing means 102 for outputting the absolute value of the rotation angle read by the reading means 101 in a binary code; and reading by the reading means 101. And a counting means 103 for counting the number of pulses obtained, the number corresponding to the digit (m + 1) th bit below the least significant digit of the m-bit absolute value expressed in Gray code format Signal generating means 104 for generating a timing signal based on a pattern further formed on the disc 100 so as to generate a signal to be generated, and m bits expressed in a binary code format which is the output of the timing signal and the processing means 102 Least significant digit of the absolute value (LSBa
An initial value calculating means 105 for calculating an initial value of the counting means 103 from bs) and an initial value setting signal generating means 106 for generating an initial value setting signal a predetermined time after power-on are provided.

[Operation] According to the hybrid encoder having such a configuration, the timing signal and four types of initial values obtained from the least significant digit (LBSabs) of the m-bit absolute value expressed in the binary code format are set in the increment counter. be able to.

Embodiment An optical hybrid encoder which is an embodiment of the present invention will be described below with reference to the drawings.

This hybrid encoder has a rotation angle of 2 ¹⁵
= 32768 divisions and outputs a 15-bit digital signal. The upper 8 bits are detected as an absolute signal, and the lower 8 bits are detected as an increment signal.

Then, the absolute value and the increment value are combined using the least significant digit of the duplicated absolute value and the most significant digit of the increment value to obtain a 15-bit output.

2 and 3 are a side sectional view and an enlarged view of a Y part of the hybrid encoder according to this embodiment, which are housed in a housing 1 composed of a main body 11 and a cover 12. FIG.

A shaft 3 having a coupling 2 protrudes from the cover 12 at the outer end of the housing 1, and the shaft 3 is supported by a bearing 13 attached to the cover 12, and is coupled to the object whose rotation angle is to be measured. Connected via

A disk 4 is attached to the tip of the shaft 3 in the housing 1 and rotates together with the rotating shaft.

The disk 4 has an absolute pattern for outputting an absolute value of the rotation angle as described later,
An increment pattern for outputting a pulse corresponding to the rotation of the rotating shaft, and 1 of the least significant digit of an m-bit absolute value expressed in a gray code format for synthesizing an absolute signal and an increment signal
A timing signal generation pattern for generating a timing signal corresponding to the next lower digit (the (m + 1) th bit) is formed.

A plurality of light emitting element groups 5 and light receiving element groups 6 corresponding to the absolute pattern, the increment pattern, the timing signal generation pattern, and the light quantity correction track are provided on both sides of the disk 4.

A light receiving element group 6 is provided between the disk 4 and the light receiving element group 6.
A fixing slit 7 is fixedly mounted on the housing 1 in order to prevent the device from being affected by optical disturbance.

Further, a circuit board 8 on which an electronic circuit for executing signal processing described later is mounted is housed in the housing 1.

The output from the housing 1 of the hybrid encoder is transmitted via the cable 20 to the hybrid encoder conversion device 30.
Is transmitted to

FIG. 4 is a view showing a pattern formed on the disk 4.

That is, an increment pattern 41 composed of slits arranged at equal intervals is formed on the outermost periphery of the disk 4.

The fixed slit 7 is provided with two slits for one increment pattern 41. The light receiving element 6 corresponding to each slit is provided with two slits of A phase and B phase shifted from each other by a quarter period. One increment pulse is output.

Inside it, one digit below the least significant digit (9 bits) of the 8-bit absolute value expressed in Gray code format in order to combine the absolute signal and the increment signal
A timing signal generation pattern 42 corresponding to (eye) is formed.

Absolute signal generation patterns 44A-44H for generating an 8-bit rotation angle absolute signal are formed inside the first light quantity correction track 43A formed inside.

A second light quantity correction track 43B is also formed between the absolute signal generation patterns 44D and 44E.

In this embodiment, it is assumed that the absolute signal generation pattern is formed so as to output a digital signal represented by a gray code.

FIG. 5 is a diagram showing functions of the circuit board 8 housed in the housing 1 for signal processing and the hybrid encoder conversion device 30 connected thereto via the cable 20.

That is, in order to make the amount of light emitted from the light emitting element group 5 constant on the circuit board 8, the amount of light passing through the two light amount correction tracks 43A and 43B is detected by the corresponding light receiving element in the light receiving element group 6, and the light emitting element A light amount correction function 81 for adjusting the amount of light emitted from the five groups, an amplifier function 82 for amplifying a signal received by the light receiving element group 6, a parallel-serial for converting an 8-bit parallel signal detected by an absolute pattern into a serial signal Line driver receiver function 84 for adjusting the state of signals transmitted to and received from hybrid encoder conversion function 30 via signal conversion function 83 and cable 20
Is included.

The hybrid encoder conversion device 30 includes a cable 20
, A line driver receiver function 301 for adjusting the state of a signal transmitted to and received from the circuit board 8 via the interface, a serial-parallel signal conversion function 302 for converting an absolute signal transmitted in a serial signal format into a parallel signal, an increment pattern , And an increment counter 303 for setting an initial value at power-on according to the present invention, an increment latch function 304 for latching the output of the counter 303, and a serial-parallel signal conversion function 302. The absolute value of the rotation angle expressed in 8-bit parallel gray code format output from is converted to an absolute value expressed in 8-bit parallel binary code, and the absolute value is calculated using the most significant digit of the increment count value. Data processing for correction 305, a data latch function 306 for latching a 15-bit absolute value of the rotation angle, which is the final output, and a control signal generation for controlling the parallel-serial signal conversion function 302, the increment value latch function 304, and the data latch function 306 Function 307 is included.

The control signal is transmitted from the terminal 211 to the terminal 201 via the cable 20, the absolute value converted into a serial signal is transmitted from the terminal 202 to the terminal 212, and the timing signal is transmitted to the terminal 20.
From 3 to terminal 213, the two-phase increment pulse is applied to terminal 20.
4 and 205 to the terminals 214 and 215 respectively.

The timing signal is generated on the disk 100 so as to generate a signal corresponding to the next lower digit (m + 1 bit) of the least significant digit of the m-bit absolute value expressed in the gray code format expressed in the binary code. Further, it is generated based on the formed pattern.

Note that the least significant digit of the m-bit absolute value represented by the binary code is 4 bits with respect to the timing signal.
It is adjusted to have a phase delay of one-half cycle.

FIG. 6 is a functional diagram for setting an initial value according to the present invention, and FIG. 7 is a truth table for determining the initial value.

That is, the increment counter 303 of the present invention includes a forward / reverse discrimination / clock pulse generation unit 3031, an exclusive OR operation unit 3032, a negative determination unit 3033, and an initial value setting signal generation unit 30.
34, and an up-down counter 3035.

Then, the forward / reverse determination and clock pulse generation unit 3031
Determines the rotation direction from the A-phase pulse and the B-phase pulse, and outputs a logical signal “0” if the rotation direction is positive, for example.
In the reverse rotation direction, a logic signal “1” is output, and
A clock pulse is generated at the edges of the A-phase pulse and the B-phase pulse.

The exclusive OR operation unit 3032 outputs the least significant digit of the rotation angle represented by the 8-bit binary code output from the data unit 305 and the 8-bit absolute value represented by the gray code transmitted from the terminal 213. The exclusive OR of the timing signal corresponding to the digit (the ninth digit) immediately below the least significant digit is calculated.

Negation determining section 3033 calculates a negative value of the output from exclusive OR operation section 3032.

The initial value setting signal generating unit 3034 outputs an initial value reading signal to the up / down counter 3035 after a predetermined time has elapsed since the power was turned on.

The up / down counter 3035 receives the clock pulse output from the forward / reverse determination / clock pulse generator 3031 and counts up, for example, when the output of the forward / reverse determination unit 3031 is a logic signal “0”, and outputs the logic signal “ Counts down at 1 ". When the initial value read signal is output from the initial value setting signal generation unit 3034, the output of the exclusive OR operation unit 3032 is output from the 0th to fourth bit input terminals.
From the input terminals of the fifth and sixth bits to the negative judgment unit 3033
, The timing signal is read from the seventh bit input terminal.

The 8-bit output of the up / down counter 3035 is the lower 8 bits of the 15-bit output of the hybrid encoder.
Bit. When an initial value setting signal is generated from the initial value setting signal generating unit 3034 a predetermined time after power-on, when the initial value setting signal is generated from the least significant digit of the m-bit absolute value expressed in the gray code format, (m + 1 bit)
, And four types of initial values determined from the least significant bit of an 8-bit absolute value represented by a binary code are set in an up-down counter according to the position of the disk at the time of power-on.

That is, the eighth bit of the 15-bit rotation angle data can be determined by the logic signal of the timing signal.

Next, the value of the sixth bit of the up / down counter 3035 is exclusive of these two signals because the phase of the timing signal is shifted by a quarter period from the eighth digit of the absolute value represented by the binary code. It can be defined as the negation of the logical sum.

Further, the value of the fifth bit or less of the up / down counter 3035 is the minimum value “0000” of the 6-bit data expressed in binary.
00 is set to "100000" when the sixth bit is a logical signal "1", and is set to "011111" when the sixth bit is a logical signal "0" as a half value of the maximum value "111111". .

For example, when the 8th digit of the absolute value expressed in the binary code format is a logical value “1” and the timing signal is a logical value “0”, the truth value table of FIG. According to the first digit of “000111
11 "is set.

[Effects of the Invention] According to the present invention, it is possible to set four types of initial values in the increment counter in accordance with the position of the disk when the power is turned on. The initial setting error can be reduced to one-fourth as compared with the case where resetting is uniformly performed by turning on.

[Brief description of the drawings]

FIG. 1 is a view showing a basic configuration of the present invention, FIG. 2 is a side view of a hybrid encoder according to the present invention, FIG. 3 is an enlarged view of a Y part of the hybrid encoder according to the present invention, and FIG. FIG. 5 is a diagram schematically showing a pattern of a disk included in the housing of FIG. 5, FIG. 5 is a diagram showing a circuit board included in the hybrid encoder housing and a signal processing function of the hybrid encoder conversion device, and FIG. FIG. 7 is a truth table for determining an initial value according to the present invention. In the figure, 100: disk, 101: reading means, 102: signal processing means, 103: counting means, 104: timing signal generating means, 105: initial value calculating means, 106: initial value setting signal generation means.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-1-305316 (JP, A) JP-A-1-305317 (JP, A) JP-A-1-153910 (JP, A) JP-A-63- 117214 (JP, A) JP-A-1-79619 (JP, A) JP-A-1-305314 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G01D 5/245 G01D 5 / 249 G01D 5/36

Claims (1)

(57) [Claims] An upper m bits (1) of an n-bit digital signal value output as a detection value of a rotation angle of a rotation axis.
A disk (100) having a concentric pattern to output a rotation angle of <m <n) as an absolute value and to output a number of pulses proportional to the rotation angle of the rotation shaft; Reading means (101) for reading a pattern formed thereon; signal processing means (102) for outputting an absolute value of the rotation angle read by the reading means (101) in a binary code; A counting means (103) for counting the pulses read by the reading means (101), one of the least significant digits of an m-bit absolute value expressed in a gray code format. The pattern further formed on the disc (100) so as to generate a signal corresponding to the lower digit (the (m + 1) th bit) Timing signal generating means (104) for generating a timing signal based on the least significant digit (LSBabs) of the m-bit absolute value expressed in a binary code format which is the timing signal and the output of the signal processing means (102) And an initial value calculating means (105) for calculating an initial value of the counting means (103) from the above, and an initial value setting signal generating means (106) for generating an initial value setting signal a predetermined time after power-on. A hybrid encoder with a special feature.