JP3198420B2 - Microprocessor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a microprocessor having a semiconductor memory suitable for supplying power to a memory cell.

[0002]

2. Description of the Related Art Conventionally, as a power supply wiring of a semiconductor memory, there is an example in which a second-layer aluminum film is used as a power supply wiring of a memory cell as described in Japanese Patent Application Laid-Open No. 64-35934. In a semiconductor memory using two aluminum films as described above, the first and second aluminum films are used for data lines, word reinforcing lines, and the like. Forming three or more aluminum films on a semiconductor memory has not been realized because a manufacturing process has not been established.
Therefore, when the aluminum film is used as the power supply wiring, it is necessary to take special consideration such as providing a power supply wiring area in a vacant area of the data line or the word reinforcing line in the memory cell or a special power supply wiring area in a portion other than the memory cell. There is.

[0003]

In a semiconductor integrated circuit, the number of elements that can be integrated in one chip is increasing as the wiring becomes finer. However, more than that, the number of elements to be incorporated in one chip increases due to the demand for increasing the memory capacity, and the chip size tends to increase. Against this background, the wiring of the memory element is becoming thinner and longer. The same applies to the power supply wiring. According to the above-described conventional technology, there is a problem that as the wiring becomes thinner and longer, the wiring resistance increases and the power supply impedance increases. That is, there is a problem in that an increase in the power supply impedance causes a reduction in the power supply voltage, which lowers the operation margin and operation speed of the circuit.

[0004] In short, the problem to be solved by the present invention
Increases chip area for power supply wiring of semiconductor memory
The idea is not to let them .

[0005]

The object of the present invention can be solved by the following means.

The present invention relates to a memory cell array and a memory peripheral.
Semiconductor memory unit comprising a circuit and another circuit
Micro-processor formed on a semiconductor chip with
In the sessa, formed on the periphery of the semiconductor chip
The memory cell array in a region facing the I / O unit
And the opposite side of the I / O section across the memory cell array.
The memory peripheral circuit is arranged in the area of
Power supply wiring is arranged in the upper layer along the periphery of the semiconductor chip
And a power supply from the power supply wiring to the upper layer of the memory cell array.
Pull out the wiring and supply power to each part from the power supply wiring
It is characterized by the following .

[0007] With this configuration, externally
The main line of the wiring of the power supply to be supplied is arranged in the upper layer of the I / O section.
The memory cell array area is not congested
A memory cell array in the area facing the I / O section
And the wiring of the power supply to the memory cells, etc. is congested.
By placing them in the upper layer of the memory cell array
Space can be used effectively. As a result,
Power supply wiring without increasing noise
Wear.

[0008]

Further, the memory cell array is formed above the memory cell array.
Power lines are connected to the data lines in this memory cell array and
It must be formed of wiring material having a different sheet resistance from the word line.
Can be. Here, the memory cell array is a memory cell
A data line for reading / writing data from / to a memory cell.
The main word line to specify the address and the power to the memory cells
And a power supply line for supplying a power source.
The inward line is aluminum formed on the first and second layers
Allocated to the film, the power supply wiring is in the third layer and the layer above the third layer
Can be allocated to the aluminum film formed on the substrate.
In this case, the power supply wiring is wired in the same direction as the data line
Is preferred.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same parts are denoted by the same reference numerals.

FIG. 1 is a perspective plan view showing the configuration of a semiconductor memory according to a first embodiment. In the figure, 100 is a memory unit, 101 is a memory cell array in which memory cells are arranged in a matrix,
102 is an X decoder for designating a row address, 103 is a peripheral circuit composed of a Y decoder and a sense amplifier for designating a column address, 104 is a main word line output from the X decoder 102, and 105 is a data line for the memory cell. Data lines for reading and writing, 106 and 10
Reference numeral 7 denotes a power supply line provided in the upper layer of the memory cell array 101. In the example of this drawing, the power supply wirings 106 and 107 are provided in parallel with the data line 105 of the memory cell.
In addition, it can be provided in a direction parallel to the main word line 104.

FIG. 2 is a perspective plan view showing the configuration of the memory unit of the first embodiment. In the figure, reference numeral 200 denotes a memory unit, 201 denotes a memory cell array in which memory cells are arranged in a matrix, 202 denotes an X decoder that specifies a row address, and 203 denotes a peripheral circuit including a Y decoder and a sense amplifier that specifies a column address. It is. Reference numeral 204 denotes a power supply wiring of a ground potential, and 205 denotes a power supply wiring of a power supply potential, both of which are formed of a third-layer aluminum film and provided above the memory cell array 201. Although the formation of the third aluminum film has conventionally not been carried out because of the cost and time, it has become possible with the progress of the manufacturing process. Ground potential power supply wiring 204 and power supply potential power supply wiring 205
Are connected to a ground potential power supply wiring and a power supply potential power supply wiring made of a second-layer aluminum film provided in the memory cell. The power supply wiring of the ground potential and the power supply wiring of the power supply potential made of the second-layer aluminum film provided in the memory cell are connected to each other between the memory cells in a direction orthogonal to the power supply wirings 204 and 205.
Further, the power supply wiring 205 of the power supply potential is connected to a power supply wiring of the power supply potential formed of a second-layer aluminum film provided in a part of the memory cell and the peripheral circuit. According to the present embodiment, the power supply wiring made of the second-layer aluminum film provided in the memory cell or in the peripheral circuit is connected to the memory cell array 2.
01 can be reinforced by a third-layer aluminum film provided on the entire upper layer. Therefore, the power supply impedance of the memory cells and peripheral circuits can be reduced without providing a power supply main line in an area other than the memory unit 200. That is, it is possible to prevent each circuit in the memory unit 200 from reducing the operation margin and the operation speed of the circuit due to the decrease in the power supply voltage without increasing the area of the LSI chip. When a semiconductor device is formed in multiple layers as in this embodiment, the upper layer becomes thicker, so that the sheet resistance becomes smaller. If a power supply trunk line is provided in the uppermost third layer, the power supply impedance can be further reduced.

FIG. 3 is a perspective plan view of a memory cell wiring pattern of the memory unit shown in FIG. Reference numeral 301 denotes a memory cell, 302 a word line made of a polysilicon film, 303
And 304, a differential data line pair made of a first-layer aluminum film. Reference numeral 305 denotes a main word line, 306 denotes a word reinforcing line, and 307 and 308 denote power supply lines provided in the memory cell for a power supply potential and a ground potential. The main word line 305, the word reinforcement line 306, and the power supply lines 307 and 308 in the memory cell are made of a second-layer aluminum film. The word line 302 and the word reinforcement line 306 are connected in an area other than the memory cell 301. In the figure, the differential data line pairs 303 and 304 are formed of the first layer of aluminum film, and the main word line 305, the word reinforcing line 306, and the power supply lines 307 and 308 are formed of the second layer of aluminum film. The first data layer and the second data layer are reversed so that the differential data line pairs 303 and 304 are composed of the second data layer, and the main word line 305, the word reinforcement line 306, and the power supply in the memory cell are formed. The wirings 307 and 308 can be made of a first-layer aluminum film.

Next, a first example of power supply to a memory cell will be described. FIG. 4 is a perspective plan view showing a power supply wiring to the memory cell shown in FIG. A power supply wiring 204 having a ground potential and a power supply wiring 2 having a power supply potential are formed above a memory cell array 201 in which memory cells 301 are arranged in a matrix.
05 are provided alternately. The memory cells 301 are arranged in the direction of the data line pairs 303 and 304 while being mirror-inverted around the main word line 305. Therefore,
One main word line 305 is shared by two memory cells on both sides. A contact hole 401 connects the power supply wiring 204 at the ground potential and the power supply wiring 308 at the ground potential in the memory cell. Reference numeral 402 also denotes a contact hole for connecting the power supply wiring 205 of the power supply potential to the power supply wiring 307 of the power supply potential in the memory cell. Thus, the ground potential power supply wiring 204 is connected to the adjacent ground potential power supply wiring 204 via the ground potential power supply wiring 308 in the memory cell. Similarly, the power supply wiring 205 of the power supply potential is connected to the power supply wiring 205 of the adjacent power supply potential via the power supply wiring 307 of the power supply potential in the memory cell. In this drawing, a power supply wiring 204 of a ground potential and a power supply wiring 205 of a power supply potential are provided in parallel with the data lines 303 and 304 in the memory cell. In two memory cells on both sides of the main word line 305,
Only the selected word, that is, the memory cell whose word line 302 has become H, operates. Accordingly, regarding one power supply wiring 204 of the ground potential and the power supply wiring 205 of the power supply potential, the memory cell current is supplied to the memory cell whose word line 302 has become H through the contact hole, and It is sufficient to supply the memory cell current to the adjacent memory cell having no contact hole via the power supply wirings 307 and 308 and supply the two memory cell currents, so that the power supply wirings 204 and 205 have the effect of reducing the voltage drop. There is. Although a power supply wiring of a ground potential or a power supply wiring of a power supply potential is provided for each memory cell in this drawing, a plurality of memory cells are collectively arranged in the direction of the word line 302 to form a power supply wiring of a ground potential or a power supply wiring of a power supply potential. It may be provided.

FIG. 5 is a longitudinal sectional view showing a section of the memory cell shown in FIG. The diffusion layer 31 is formed on the semiconductor on the substrate 310
4 is formed, and an in-cell wiring of tungsten 315 is connected to the diffusion layer 314. A polysilicon gate 316 is formed between the wirings of the tungsten 315 in the cell. A first aluminum film 311 is formed on a layer above tungsten 315 and used as data lines 303 and 304. A second aluminum film 312 is formed on a layer above the first aluminum film 311 and a main word line 305 is formed.
A word reinforcement line 306, a power supply line 307 in a memory cell,
308, and a third-layer aluminum film 313 is formed on a layer above the second-layer aluminum film to be used as power supply wirings 204 and 205. Incidentally between aluminum film layers are arranged insulating film 317.

Next, a second example showing the power supply to the memory cells will be described. FIG. 6 is a perspective plan view showing a power supply wiring to the memory cell shown in FIG. Reference numeral 501 denotes a memory cell, and 502 denotes a power supply wiring of a ground potential in the memory cell, which is constituted by a second-layer aluminum film. 503
Is a power supply wiring of a power supply potential in the memory cell, and is constituted by a second-layer aluminum film. A contact hole 504 connects the ground potential power supply wiring 204 and the ground potential power supply wiring 502 in the memory cell. 505
Are also contact holes, and the power supply wiring 205 of the power supply potential
And the power supply wiring 503 of the power supply potential in the memory cell. In this figure, since both the power supply wiring 204 of the ground potential and the power supply wiring 205 of the power supply potential are provided for each memory cell, the power supply wiring 502 of the ground potential and the power supply of the power supply potential provided in the memory cell are provided. The wiring 503 does not need to be connected to both adjacent memory cells. Therefore, the power supply wiring 502 of the ground potential and the power supply wiring 503 of the power supply potential in the memory cell are provided.
Does not need to extend the wiring to the cell boundary, and has the effect that the memory cell size can be reduced.

Next, two examples of typical configurations of the memory cell will be described. FIG. 7 is a circuit diagram of a general 4MOS memory cell. Reference numerals 601 and 602 denote differential data line pairs, which are made of, for example, a first layer aluminum film. A word line 603 is formed of, for example, a polysilicon film. 60
4, 605 and 608, 609 are NMOSFETs, 60
6, 607 are high resistance, 610 is a power supply terminal, and 611 is a ground terminal.

FIG. 8 is a circuit diagram of a general 6MOS memory cell. 701 and 702 are PMOSFETs.

FIG. 9 is a perspective plan view showing the arrangement of memory units in an LSI chip. 801 is an LSI chip, 802 is a bonding pad, 803 is an I / O cell, 804 is a ground potential power supply wiring for a chip internal circuit,
Reference numeral 805 denotes a power supply wiring of a power supply potential for a chip internal circuit, and both are formed of a second-layer aluminum film above the I / O cell 803. Reference numeral 806 denotes a ground potential power supply wiring made of a third-layer aluminum film. The power supply wiring 806 is connected to the memory unit 200 or 810 via the contact hole 808 from the ground potential power supply wiring 804 for the chip internal circuit. Reference numeral 807 denotes a power supply wiring of a power supply potential composed of a third-layer aluminum film, which is connected from the power supply wiring 805 of the power supply potential for the internal circuit of the chip to the memory unit 200 or 810 via the contact hole 809. 811 and 814 are memory cell arrays, 812,
815 is an X decoder, and 813 is a memory peripheral circuit.
In this figure, the power supply wiring is directly connected to the memory unit 200 or 810 from the power supply wirings 804 and 805 in the upper layer of the I / O cell. Thus, there is no need to provide a power supply main line in an area other than the memory unit 200 or 810, and the area of the LSI chip can be reduced.

Second Embodiment FIG. 10 is a perspective plan view showing the structure of a semiconductor memory according to a second embodiment. Reference numerals 206, 207, and 208 denote a power supply line for a ground potential and a power supply line for a power supply potential having different potentials. For example, reference numeral 206 denotes a power supply wiring of a ground potential connected to a peripheral circuit, 207 denotes a power supply wiring of a power supply potential connected to a memory cell and a peripheral circuit, and 208 denotes a third potential of a ground potential for connection to a memory cell. Power wiring.
Although three types of power supply wirings having different potentials are described in this drawing, three or more types of power supply wirings having different potentials may exist.

Third Embodiment FIG. 11 is a perspective plan view showing a configuration of a semiconductor memory according to a third embodiment. Reference numerals 209 and 210 denote power supply lines for supplying a ground potential or a power supply potential, which are formed on the entire upper surface of the memory cell array 201. The power supply wirings 209 and 210 are
The same power supply potential or different power supply potentials may be used.

Fourth Embodiment FIG. 12 is a perspective plan view showing a configuration of a semiconductor memory according to a fourth embodiment. Reference numerals 211 and 212 denote power supply lines for ground potential or power supply potential, each of which is composed of a different wiring layer. For example, the power supply wiring 211 is made of a third aluminum film for ground potential, and the power supply wiring 212 is made of a fourth aluminum film for power supply potential. In this drawing, different potentials are applied to the third and fourth aluminum films. However, it is also possible to provide three or more types of wiring layers and allocate the same potential or different potential power supply potentials in various examples.

As described above, since the upper layer of the memory cell array in the memory unit can be used as the entire power supply wiring area, it is necessary to secure an extra power supply wiring area other than the memory unit in order to strengthen the power supply wiring. Absent. Therefore, a static RAM, a microprocessor, a gate array, and the like using such a semiconductor memory can prevent a power supply voltage drop inside the chip without increasing the chip area, and can operate the circuit in a margin due to the power supply voltage drop. And the operating speed can be prevented from lowering.

[0024]

As described above, according to the present invention,
Power supply for semiconductor memory without increasing chip area
Lines can be placed.

[Brief description of the drawings]

FIG. 1 is a perspective plan view showing a configuration of a semiconductor memory according to a first embodiment of the present invention.

FIG. 2 is a perspective plan view showing the configuration of the memory unit according to the first embodiment of the present invention.

FIG. 3 is a perspective plan view of a memory cell wiring pattern of the memory unit shown in FIG. 2;

FIG. 4 is a perspective plan view showing power supply wiring to the memory cell shown in FIG. 3;

FIG. 5 is a longitudinal sectional view showing a section of the memory cell shown in FIG. 4;

6 is a perspective plan view showing power supply wiring to the memory cell shown in FIG. 3;

FIG. 7 is a circuit diagram of a general 4MOS memory cell.

FIG. 8 is a circuit diagram of a general 6MOS memory cell.

FIG. 9 is a perspective plan view showing the arrangement of memory units in an LSI chip.

FIG. 10 is a perspective plan view showing a configuration of a semiconductor memory according to a second embodiment of the present invention.

FIG. 11 is a perspective plan view showing a configuration of a semiconductor memory according to a third embodiment of the present invention.

FIG. 12 is a perspective plan view showing the configuration of a semiconductor memory according to a fourth embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 memory unit 101 memory cell array 102 X decoder 103 memory peripheral circuit 104 main word line 105 data line 106 power wiring 107 power wiring 204 power wiring 205 power wiring 206 power wiring 207 power wiring 208 power wiring 209 power wiring 210 power wiring 211 power wiring 212 power supply wiring 307 power supply wiring in memory cell 308 power supply wiring in memory cell 311 first layer aluminum film 312 second layer aluminum film 313 third layer aluminum film 806 power supply wiring 807 power supply wiring

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-62-217631 (JP, A) JP-A-62-267835 (JP, A) JP-A-1-272149 (JP, A) JP-A-62-26731 188363 (JP, A) JP-A-64-61051 (JP, A) JP-A-64-35934 (JP, A) JP-A-2-36563 (JP, A) JP-A-1-166553 (JP, A) JP-A-60-170966 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/108 H01L 21/3205 H01L 21/82 H01L 21/8242

Claims (4)

(57) [Claims] A memory cell array and a memory peripheral circuit;
The built-in semiconductor memory unit, together with other circuits
For microprocessors formed on semiconductor chips
An I / O formed at a peripheral portion of the semiconductor chip.
Placing the memory cell array in a region facing the
In the area on the opposite side of the I / O section across the Morisel array
The memory peripheral circuit is arranged, and the memory peripheral circuit is disposed above the I / O section.
Power supply wiring is provided along the periphery of the semiconductor chip.
Power supply wiring from the power supply wiring to the upper layer of the memory cell array.
Power supply to each part from the power supply wiring.
Microprocessor . 2. A power supply wiring formed on an upper layer of the memory cell array, according to claim 1, characterized in that it is formed by a wiring material having a different sheet resistance data lines and word lines of said memory cell array A microprocessor according to claim 1 . 3. The memory cell array includes a data line for reading and writing data from and to a memory cell, a main word line for specifying an address of the memory cell, and a power supply line for supplying power to the memory cell. And the main word line is allocated to an aluminum film formed on a first layer and a second layer, and the power supply wiring is allocated to an aluminum film formed on a third layer and an upper layer above the third layer. The microprocessor according to claim 1 . 4. The microprocessor according to claim 3 , wherein a power supply line for supplying power to the memory cell is arranged in the same direction as the data line.