JP3198047U - Synchronous rectifier control circuit - Google Patents

Abstract

A synchronous rectifier control circuit for reducing switch loss at a light load of a power converter is provided. A synchronous rectifier control circuit includes a signal processing unit 1 and a drive unit 20. The signal processing unit is electrically connected to a secondary winding of a transformer T. The drive unit includes power switching elements MOS11-14, Electrically connected to the MOSs 21 to 24 and the signal processing unit. The signal processing unit detects the output current of the secondary winding and determines the quantity by which the power switching element is operated in the follow state. When the output current is smaller than the first predetermined value, one power switching element of each switching group is operated in the follow state, and when the output current is larger than the second predetermined value, all the power switching elements are all in the follow state. When operated and the output current is between the first predetermined value and the second predetermined value, the signal processing unit increases the number of power switching elements operating in the follow state as the output current increases. [Selection] Figure 2

Description

  The present invention relates to a synchronous rectifier in a power converter, and more particularly to a synchronous rectifier control circuit.

  In the rectification method using a conventional diode or Schottky diode, the voltage is large due to forward conduction, and the overall wear is the main wear of the power converter. The metal oxide semiconductor field effect transistor has a low conduction resistance, a short switching time, a high input resistance, and is a suitable rectifying member for a power converter with a low voltage and a large current. As an advantage of control, it has a technique of synchronous rectification (SR).

  Reference is made to FIG. 1, which is a circuit diagram of a conventional synchronous rectifier control circuit. The synchronous rectifier control circuit 4 is electrically connected to the secondary winding of the transformer and is used to control the operation state of the power switching element of the synchronous rectifier. The synchronous rectifier is electrically connected to the secondary winding of the transformer T of the power converter (eg, DC-DC power converter), the synchronous rectifier includes a first switching group SR1 and a second switching group SR2, Each of the first switching group SR1 and the second switching group SR2 includes four power switching elements, of which the first switching group SR1 includes power switching elements MOS11 to MOS14, and the second switching group SR2 includes MOS21 to MOS24. Including. The power switching elements MOS11 to MOS14 in the first switching group SR1 are connected in parallel, and the power switching elements MOS21 to MOS24 in the second switching group SR2 are also connected in parallel. More specifically, in the first switching group SR1 and the second switching group SR2, the gates of the power switching elements MOS11 to MOS24 are all electrically connected to the synchronous rectifier control circuit 4, and the drains are all of the transformer T. Electrically connected to the secondary winding, and all sources are electrically connected to the ground terminal.

  Thereby, the synchronous rectifier control circuit 4 can simultaneously control the operation states of the power switching elements included in the first switching group SR1 and the second switching group SR2. For example, the operation of all the power switching elements MOS11 to MOS24 in the first switching group SR1 and the second switching group SR2 is stopped or all the power switching elements in the first switching group SR1 and the second switching group SR2 are stopped. The MOS 11 to MOS 24 are switched according to the drive signal output from the synchronous rectifier control circuit 4.

The power switching elements MOS11 to MOS24 of the synchronous rectifier have the advantage that the control method is simple and the circuit is simple. However, the synchronous rectifier control circuit 4 outputs all the power switching elements MOS11 to MOS24 regardless of whether the power converter is operated to a heavy load or a light load after the power converter is started. The switch operation is performed based on the drive signal, and the power converter cannot effectively reduce the loss of the switch when the load is light.
As a prior art, there is one that discloses a power converter having a synchronous rectification function that further reduces power consumption (see, for example, Patent Document 1).

Utility Model Registration No. 3126122

  The purpose of the present invention is to determine the number of power switching elements in the synchronous rectifier to be operated in the follow state based on the output current of the secondary winding of the power converter, and to operate in the follow state when the output current increases. An object of the present invention is to provide a synchronous rectifier control circuit applied to control of a synchronous rectifier in a power converter, which increases the number of power switching elements to be reduced and reduces switch loss at the time of light load of the power converter. The follow state will be described later.

  The synchronous rectifier control circuit provided by the present invention is applied to a synchronous rectifier that controls a power converter. The synchronous rectifier is electrically connected to the secondary winding of the transformer of the power converter, and includes a plurality of switching groups, and each switching group includes a plurality of power switching elements.

  The synchronous rectifier control circuit includes a signal processing unit and a plurality of driving units, and the signal processing unit is electrically connected to the secondary winding of the transformer T. The drive units are electrically connected to the open / close group and the signal processing unit, respectively.

  The signal processing unit detects the output current of the secondary winding of the transformer T, and determines the number of power switching elements to be turned off based on the output current. When the output current is smaller than the first predetermined value, one power switching element of the switching group is operated in the follow state, and when the output current is larger than the second predetermined value, the power switching elements are all operated in the follow state, When the output current is between the first predetermined value and the second predetermined value, the signal processing unit increases the number of power switching elements that operate in the follow state as the output current increases.

  The synchronous rectifier control circuit of the present invention is applied to control of the synchronous rectifier in the power converter, and the power switching element in the synchronous rectifier is operated in the follow state based on the output current of the secondary winding of the power converter. The quantity is determined, and when the output current increases, the quantity of the power switching elements operated in the follow state is increased, and the switch loss at light load of the power converter is reduced.

It is a circuit diagram of the synchronous rectifier control circuit of a prior art. It is a circuit diagram of the synchronous rectifier control circuit of one embodiment of the present invention. It is a timing diagram of an output current and an open / close state in an embodiment of the present invention. It is a circuit block diagram of the signal processing unit of 1st Example of this invention. It is a circuit block diagram of the signal processing unit of 2nd Example of this invention. It is a circuit block diagram of the signal processing unit of 3rd Example of this invention. It is a circuit block diagram of the drive unit of 1st Example of this invention. It is a circuit block diagram of the drive unit of 2nd Example of this invention. It is a circuit block diagram of the drive unit of 3rd Example of this invention.

  Detailed description and technical contents of the present invention will be described below with reference to the drawings. However, the drawings are only provided for reference and explanation, and are not used to limit the present invention. .

  Referring to FIG. 2, it is a circuit diagram of a synchronous rectifier control circuit according to an embodiment of the present invention. The synchronous rectifier control circuit is applied to a synchronous rectifier that controls the power converter, and the synchronous rectifier is electrically connected to the secondary winding of the transformer T of the power converter, and includes a plurality of switching groups SR1 to SR2, The switching groups SR1 and SR2 include a plurality of power switching elements MOS11 to MOS24, and the power switching element can be, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET). . In particular, the synchronous rectifier circuit according to an embodiment of the present invention is described as an example by controlling two power switching elements of two switching groups. The quantity of power switching elements can be adjusted based on actual requirements. The drains of the power switching elements MOS11 to MOS24 are each electrically connected to the secondary winding of the transformer T, and the sources are connected to the ground terminal.

  The synchronous rectifier control circuit includes a signal processing unit 1 and a plurality of drive units 20. The signal processing unit 1 is electrically connected to the secondary winding of the transformer T and used to sense the output current of the secondary winding. Among them, the signal processing unit 1 senses the output current of the secondary winding in a non-contact manner through a current transformer or in a contact manner through a current detection resistor (shunt resistor). Obtain the output current of the next winding. The signal processing unit 1 includes a current detection end I_SENSE, a plurality of drive output ends, and a plurality of control signal output ends. In the present invention, the signal processing unit 1 includes two drive output terminals and three control output terminals, and each includes a first drive output terminal Drv1, a second drive output terminal Drv2, a first control signal output terminal MOS2_EN, and a second control output terminal. The control signal output terminal MOS3_EN and the third control signal output terminal MOS4_EN.

  When the drive unit 20 includes a drive signal input terminal DrvI, a plurality of control signal input terminals, and a plurality of output terminals, the number of control signal input terminals is P, and the number of output terminals is Q, the following conditions are satisfied. : P = Q-1 is satisfied. In the present invention, the drive unit 20 includes three control signal input terminals, which are a first control signal input terminal Cntl2, a second control signal input terminal Cntl3, and a third control signal input terminal Cntl4, respectively. The drive unit 20 further includes four output ends, and is a first output end Out1, a second output end Out2, a second output end Out3, and a fourth output end Out4, respectively.

  The first drive signal output terminal Drv1 of the signal processing unit 1 is electrically connected to the drive signal input terminal DrvI of one drive unit 20, and the second drive signal output terminal Drv2 is connected to the drive signal input terminal of the other drive unit 20. Electrical connection to DrvI. The first control signal output terminal MOS2_EN of the signal processing unit 1 is electrically connected to the first control signal input terminal Cntl2 of the drive unit 20, and the second control signal output terminal MOS3_EN is connected to the second control signal input terminal Cntl3 of the drive unit 20. The third control signal output terminal MOS4_EN is electrically connected to the third control signal input terminal Cntl4 of the drive unit 20.

  The first output terminal Out1, the second output terminal Out2, the third output terminal Out3, and the fourth output terminal Out4 located in the upper drive unit 20 shown in FIG. 2 are electrically connected to the gates of the power switching elements MOS11 to MOS14, respectively. The first output terminal Out1, the second output terminal Out2, the third output terminal Out3, and the fourth output terminal Out4 located in the lower drive unit 20 are electrically connected to the gates of the power switching elements MOS21 to MOS24, respectively.

  The current detection terminal I_SENSE of the signal processing unit 1 is electrically connected to the secondary winding of the transformer T and detects the output current of the secondary winding. Based on the detected output current, the signal processing unit 1 determines the quantity of the power switching elements MOS11 to MOS24 to be operated in the off state, and the first control signal output terminal MOS2_EN, the second control signal output terminal MOS3_EN, and the third control signal. A corresponding control signal is sent from the output terminal MOS4_EN to the first control signal input terminal Cntl2, the second control signal input terminal Cntl3, and the third control signal input terminal Cntl4 of the drive unit 20, and the operation states of the power switching elements MOS11 to MOS24 are transmitted. Control.

  The operating states of the power switching elements MOS11 to MOS24 include an off state and a follow state, and when the gates of the power switching elements MOS11 to MOS24 receive an off signal (here, a continuous low level signal) in the off state, The sources and drains of the power switching elements MOS11 to MOS24 are not conducted and are turned off. In the follow state, the power switching elements MOS11 to MOS24 perform a switching operation in accordance with the driving signal sent out by the driving unit 20, and the driving signal at that time is formed from alternately arranged low level signals and high level signals.

  When the output current of the secondary winding of the transformer T is smaller than the first set value I1 (see FIG. 3), the synchronous rectifier control circuit is one of the power switch elements SR1, SR, for example, the power switch element MOS11. And the MOS 21 is operated in the follow state, and the other power switching elements MOS12, MOS13, MOS14, MOS22, MOS23, and MOS24 are operated in the off state. In other words, only the power switching elements MOS11 and MOS21 are not operated to be turned off.

  When the output current of the secondary winding of the transformer T is larger than the second set value I2 (see FIG. 3), the synchronous rectifier control circuit operates all the power switching elements MOS11 to MOS24 in the follow state, and Each of the power switching elements MOS11 to MOS24 performs a switching operation with a driving signal output from the driving unit 20. In other words, none of the power switching elements MOS11 to MOS24 is operated to the off state. The second set value I2 at that time can be, for example, a current value when the power converter is half loaded, and the second set value I2 is larger than the first set value I1.

  When the output current of the secondary winding of the transformer T is between the first set value I1 and the second set value I2, and the first set value I1 gradually increases with respect to the second set value I2, The rectifier control circuit gradually increases the number of power switching elements MOS11 to MOS24 operated in the follow state. In short, when the output current of the secondary winding of the transformer T is small, the number of power switching elements MOS11 to MOS24 operated in the follow state decreases (that is, the number of power switching elements MOS11 to MOS24 in the off state). Many). When the output current of the secondary winding is large, the number of power switching elements MOS11 to MOS24 operated in the follow state increases (that is, the number of power switching elements MOS11 to MOS24 operated in the off state decreases). And preferably, the number of power switching elements MOS11 to MOS24 operated in the follow state and the numerical value of the output current are directly proportional. Thereby, the switch loss of the power switching element when the power converter is operated to a light load can be effectively reduced.

The operation state of the synchronous rectifier control circuit of the present invention will be described according to Table 1 below.

  Table 1 shows detailed operation data of the synchronous rectifier control circuit of FIG. 2, in which L represents a low level signal output and H represents a high level signal output. “Off” indicates that the power switching elements MOS11 to MOS24 are operated in an off state, that is, the power switching elements MOS11 to MOS24 are not electrically connected to each other. “Follow” indicates that the power switching elements MOS11 to MOS24 are operated in the follow state, that is, the power switching elements MOS11 to MOS24 output the first or second drive signal output terminals Drv1 and Drv2 of the signal processing unit 1. Drive signal and switch operation.

  In brief, the synchronous rectifier control method of the present invention first detects the output current of the secondary winding of the transformer T, and when the output current is larger than the first set value and smaller than the second set value, Based on the output current, the operating states of the power switching elements MOS11 to MOS24 in the switching groups SR1 and SR2 are controlled, and when the output current gradually increases, the power switching elements MOS11 to MOS24 in the switching groups SR1 and SR2 follow. Increase the quantity manipulated to the state.

  Reference is made to FIG. 4a, which is a block diagram of the signal processing unit of the first embodiment of the present invention. The signal processing unit 1 includes a signal processor 10. The signal processor 10 includes a current detection terminal I_SENSE, first to third control signal output terminals MOS2_EN to MOS4_EN, a first drive signal output terminal Drv1, and a second drive signal output. The signal processing unit 1 includes a terminal Drv2 and is used as a current detection terminal I_SENSE, first to third control signal output terminals MOS2_EN to MOS4_EN, a first drive signal output terminal Drv1, and a second drive signal output terminal Drv2, respectively.

  Reference is made to FIG. 4b, which is a block diagram of the signal processing unit of the second embodiment of the present invention. The signal processing unit 1 includes a signal processor 10 and a pulse width modulation controller 12. The signal processor 10 includes a current detection terminal I_SENSE and first to third control signal output terminals MOS2_EN to MOS4_EN, and is used as the current detection terminal I_SENSE and the first to third control signal output terminals MOS2_EN to MOS4_EN of the signal processing unit 1. It is done.

  The pulse width modulation controller 12 includes a first drive signal output terminal Drv1 and a second drive signal output terminal Drv2, and serves as a first drive signal output terminal Drv1 and a second drive signal output terminal Drv2 of the signal processing unit 1. Used.

  Reference is made to FIG. 4c, which is a block diagram of the signal processing unit of the third embodiment of the present invention. The signal processing unit 1 includes a signal processor 10 and a switch member 11. The signal processor 10 includes a first current detection terminal I_SENSE, first to third control signal output terminals MOS2_EN to MOS4_EN, an enable terminal Enable, a switch control terminal SW, and a plurality of operation mode signal output terminals SR1_MODE1 to SR2_MODE2. The terminal I_SENSE and the first to third control signal output terminals MOS2_EN to MOS4_EN are used as the current detection terminal I_SENSE and the first to third control signal output terminals MOS2_EN to MOS4_EN of the signal processing unit 1.

  The switch member 11 includes a first drive signal output terminal Drv1, a second drive signal output terminal Drv2, an enable terminal Enable, a switch control terminal SW, and a plurality of drive selection terminals Drv1_Select_1 to Drv2_Select_2, and includes a first drive signal output terminal Drv1 and a first drive signal output terminal Drv1. The two drive signal output terminals Drv2 are used as the first drive signal output terminal Drv1 and the second drive signal output terminal Drv2 of the signal processing unit 1.

  The enable end Enable and the switch control end SW of the signal processor 10 are electrically connected to the enable end Enable and the switch control end SW of the switch member 11, respectively, and are used to control the operating state of the switch member 11. The operation mode signal output terminals SR1_MODE1 to SR2_MODE2 of the signal processor 10 are electrically connected to the drive selection terminals Drv1_Select_1 to Drv2_Select_2 of the switch member 11, respectively. The switch member 11 is based on signals output from the operation mode signal output terminals SR1_MODE1 to SR2_MODE2. The operating states of the power switching elements MOS11 to MOS24 are determined.

The operation state of the synchronous rectifier control circuit including the signal processing unit of the third embodiment will be described below with reference to Table 2.

  Table 2 shows detailed operation data of the synchronous rectifier control circuit of the signal processing unit shown in FIG. 4c, of which X represents an arbitrary signal output, L represents a low level signal output, and H represents a high level. Represents level signal output. “Off” indicates that the power switching elements MOS11 to MOS24 are operated in an off state, that is, the power switching elements MOS11 to MOS24 are not electrically connected to each other. “Follow” indicates that the power switching elements MOS11 to MOS24 are operated in the follow state, that is, the power switching elements MOS11 to MOS24 output the first or second drive signal output terminals Drv1 and Drv2 of the signal processing unit 1. Drive signal and switch operation.

  Referring to FIG. 5a, it is a circuit block diagram of the driving unit of the first embodiment of the present invention. The drive unit 20 includes a main driver 30 and a sub-driver 32. The main driver 30 and the sub-driver 32 are a first drive input terminal Drv_In_1, a second drive input terminal Drv_In_2, a first control terminal Cntl_1, a second control terminal Cntl_2, a first drive output terminal Drv_Out_1, and a second drive output terminal, respectively. Drv_Out_2 is included.

  The first drive input terminal Drv_In_1 and the second drive input terminal Drv_In_2 of the main driver 30 and the first drive input terminal Drv_In_1 and the second drive input terminal Drv_In_2 of the sub-driver 32 are connected to each other and do not drive the drive unit 20. Used as the input terminal DrvI.

  The second control terminal Cntl_2 of the main driver 30 is used as the first control signal input terminal Cntl2 of the drive unit 20, and the first control terminal Cntl_1 of the sub-driver 32 is the second control signal input terminal Cntl3 of the drive unit 20. The second control terminal Cntl_2 of the sub-driver 32 is used as the third control signal input terminal cntl4 of the driving unit 20, and the first control terminal Cntl_1 of the main driver 30 is electrically connected to the enable signal and enabled. The state that has been turned on is retained at any time.

  The first drive output terminal Drv_Out_1 and the second drive output terminal Drv_Out_2 of the main driver 30 are used as the first output terminal Out1 and the second output terminal Out2 of the drive unit 20, respectively, and the first drive output terminal of the sub-driver 32. The Drv_Out_1 and the second drive output terminal Drv_Out_2 are used as the third output terminal Out3 and the fourth output terminal Out4 of the drive unit 20.

  Referring to FIG. 5b, it is a circuit block diagram of the driving unit of the second embodiment of the present invention. The driving unit 20 may be composed of a main driver 30 and a sub driver 32. The main driver 30 and the sub-driver 32 include a first drive input terminal Drv_Out_1 and a first drive output terminal Drv_Out_1, respectively.

  The sub-driver 32 further includes a second drive input terminal Drv_In_2, a third drive input terminal Drv_In3, a fourth drive input terminal Drv_In_4, a first control terminal Cntl_1, a second control terminal Cntl_2, a third control terminal Cntl_In_3, and a fourth control. A terminal Cntl_4, a second drive output terminal Drv_Out_2, a third drive output terminal Drv_Out_3, and a fourth drive output terminal Drv_Out_4 are included.

  The first drive input terminal Drv_In_1 of the main driver 30 and the first drive input terminal Drv_In_1, the second drive input terminal Drv_In_2, and the third drive input terminal Drv_In_3 of the sub-driver 32 are connected to each other, and the drive input of the drive unit 20 Used for the end Drv1.

  The first control terminal Cntl_1, the second control terminal Cntl_2, and the third control terminal Cntl_3 of the sub-driver 32 are used as the first control signal input terminal Cntl2, the second control terminal Cntl3, and the third control terminal Cntl4 of the drive unit 30, respectively. It is done.

  The first drive output terminal Drv_Out1 of the main driver 30 is used as the first output terminal Out1 of the drive unit 20, and the first drive output terminal Drv_Out_1, the second drive output terminal Drv_Out_2, and the third drive output terminal of the sub-driver 32. Drv_Out_3 is used as the second output terminal Out2, the third output terminal Out3, and the fourth output terminal Out4 of the drive unit 20, respectively.

  Referring to FIG. 5c, it is a circuit block diagram of the driving unit of the third embodiment of the present invention. The drive unit 20 can include a main driver 30 and an opening / closing circuit 40. The main driver 30 includes a first drive input terminal Drv_In_1, a second drive input terminal Drv_In_2, a third drive input terminal Drv_In_3, a fourth drive input terminal Drv_In_4, a first drive output terminal Drv_Out_1, a second drive output terminal Drv_Out_2, and a third drive input terminal Drv_In_1. A drive output terminal Drv_Out_3 and a fourth drive output terminal Drv_Out_4 are included.

  The first drive input terminal Drv_In_1, the second drive input terminal Drv_In_2, the third drive input terminal Drv_In_3, and the fourth drive input terminal Drv_In_4 are connected to each other and used as the drive signal input terminal DrvI of the drive unit 20.

  The open / close circuit 40 includes a first open / close input terminal Sw_In_1, a second open / close input terminal Sw_In_2, a third open / close input terminal Sw_In_3, a fourth open / close input terminal Sw_In_4, a first open / close enable terminal Sw_1_En, a second open / close enable terminal Sw_2_En, and a third open / close circuit. It includes an enable end Sw_3_En, a fourth open / close enable end Sw_4_En, a first open / close output end Sw_Out_1, a second open / close output end Sw_Out_2, a third open / close output end Sw_Out_3, and a fourth open / close output end Sw_Out_4.

  The first opening / closing input end Sw_In_1, the second opening / closing input end Sw_In_2, the third opening / closing input end Sw_In_3, and the fourth opening / closing input end Sw_In_4 are respectively a first opening / closing output end Drv_Out_1, a second opening / closing output end Drv_Out_2, and a third opening / closing output end Drv_Out_3. The fourth open / close output terminal Drv_Out_4 is electrically connected.

  The first open / close enable end Sw_1_EN is electrically connected to the enable signal and keeps the enabled state as needed. The second open / close enable end Sw_2_En, the third open / close enable end Sw_3_En, and the fourth open / close enable end Sw_4_En are the first control signal input end Cntl2, the second control signal input end Cntl3, and the third control signal input end Cntl4 of the drive unit 20, respectively. Used as

  The first opening / closing output end Sw_Out_1, the second opening / closing output end Sw_Out_2, the third opening / closing output end Sw_Out_3, and the fourth opening / closing output end Sw_Out_4 are the first output end Out1, the second output end Out2, the third output end Out3 of the drive unit 20, respectively. And the fourth output terminal Out4.

  The drive unit 20 shown in FIGS. 5a to 5c can combine any one signal processing unit 1 shown in FIGS. 4a to 4c with the synchronous rectifier control circuit of the present invention, and the circuit connection method is the same as the previous sentence. It is not described here. In addition, any one type of combination synchronous rectifier control circuit can control the operation state (off state and follow state described in the previous sentence) of each power switching element in the control switching group. The switch loss at the time of load can be reduced effectively.

 In the present invention, preferred embodiments have been disclosed as described above, but these are not intended to limit the present invention in any way, and anyone who is familiar with the technology has an equivalent scope that does not depart from the spirit and scope of the present invention. Of course, various changes and modifications can be added.

DESCRIPTION OF SYMBOLS 1 Signal processing unit 10 Signal processor 11 Switch member 12 Pulse width modulation controller 20 Drive unit 30 Main driver 32 Sub-driver 40 Switching circuit 4 Synchronous rectifier control circuit Cntl2 First control signal input terminal Cntl3 Second control signal input terminal Cntl4 Third control signal input terminal Cntl_1 First control terminal Cntl_2 Second control terminal Cntl_3 Third control terminal Cntl_4 Fourth control terminal Drv_In_1 First drive input terminal Drv_In_2 Second drive input terminal Drv_In_3 Third drive input terminal Drv_In_4 Fourth drive Terminal Drv_Out_1 first driving output terminal Drv_Out_2 second driving output terminal Drv_Out_3 third driving output terminal Drv_Out_4 fourth driving output terminal Drv1 first driving signal output terminal Drv2 second driving signal output terminal DrvI driving signal input terminal Drv1_S Lect_1 to Drv2_Select_2 Drive selection end Enable enable end 11 First set value 12 Second set value I_SENSE Current detection end MOS11 to MOS24 Power switch MOS2_EN First control output end MOS3_EN Second control output end MOS4_EN Third control output end Out1 First output Terminal Out2 second output terminal Out3 third output terminal Out4 fourth output terminal SR1, SR2 switching groups SR1_MODE1 to SR2_MODE2 operation mode signal output terminal SW switch control terminal Sw_1_En first switching enable terminal Sw_2_En second switching enable terminal Sw_3_En third switching enable End Sw_4_En Fourth open / close enable end Sw_In_1 First open / close input end Sw_In_2 Second open / close input end Sw_In_3 Third open / close input end Sw_In _4 4th switching input terminal Sw_Out_1 1st switching output terminal Sw_Out_2 2nd switching output terminal Sw_Out_3 3rd switching output terminal Sw_Out_4 4th switching output terminal T Transformer

Claims (9)

A synchronous rectifier control circuit applied to control a synchronous rectifier of a power converter, the synchronous rectifier being electrically connected to a secondary winding of the transformer of the power converter and including a plurality of switching groups Each of the switching groups includes a plurality of power switching elements, and the synchronous rectifier control circuit includes:
A signal processing unit that is electrically connected to the secondary winding of the transformer, detects an output current of the secondary winding of the transformer, and the output current determines a quantity to be operated in a follow state of the power switching element When,
A plurality of drive units each electrically connected to the open / close group and the signal processing unit;
And when the output current is smaller than a first predetermined value, one power switching element of the switching group operates in a follow state, and when the output current is larger than a second predetermined value, the power switching All the elements are operated in the follow state, and when the output current is between the first predetermined value and the second predetermined value, the signal processing unit operates in the follow state as the output current increases. A synchronous rectifier control circuit, wherein the number of power switching elements is increased.   The signal processing unit includes a current detection end, a plurality of drive signal output ends, and a plurality of control signal output ends. The power supply detection end is electrically connected to the secondary winding of the transformer, and each of the drive units A drive signal input end, a plurality of control signal input ends, and a plurality of output ends, wherein the drive signal output end of the signal processing unit is electrically connected to the drive signal input end of the drive unit, and the signal processing unit The control signal output terminal of the drive unit is electrically connected to the control signal input terminal of the drive unit, and the output terminal of each drive unit is electrically connected to one of the power switching elements. 2. The synchronous rectifier control circuit according to 1.   The number of the control signal input ends of each of the drive units is P, and the number of the output ends of each of the drive units is Q, which is the following condition: P = Q−1 The synchronous rectifier control circuit according to claim 2.   The signal processing unit includes a signal processor and a pulse width modulation controller, the signal processor includes the current selection terminal and the control signal output terminal, and the pulse width modulation controller includes the drive signal output terminal. The synchronous rectifier control circuit according to claim 2, comprising:   The signal processing unit includes a signal processor and a switch member, and the signal processor includes the current detection end, the control signal output end, an enable end, a switch control end, and a plurality of drive selection ends. The enable end and the switch control end of the switch are electrically connected to the enable end and the switch control end of the switch member, respectively, and the operation mode signal output end of the signal processor is respectively connected to the drive selection of the switch member. The synchronous rectifier control circuit according to claim 2, wherein the synchronous rectifier control circuit is electrically connected to an end.   The drive unit includes a main driver and a sub-driver. The main driver and the sub-driver are respectively a first drive input end, a second drive input end, a first control end, a second control end, A first drive output end and a second drive output end, wherein the first drive input end and the second drive input end of the main driver and the sub drive are used as the drive signal input end of the drive unit; The second control end of the main driver is used as the first control signal input end of the drive unit, and the first control end of the sub-driver is used as the second control signal input end of the drive unit. 6. The synchronous rectifier control circuit according to claim 4, wherein the second control terminal of the sub-driver is used as the third control signal input terminal of the driving unit.   The drive unit includes a main driver and a sub-driver. The main driver includes a first drive input end and a first drive output end. The sub-driver includes a first drive input end and a second drive input. Input end, third drive input end, fourth drive input end, first control end, second control end, third control end, fourth control end, first drive output end, second drive output end, third drive An output end and a fourth drive output end, the first drive input end of the main driver, the first drive input end of the sub-driver, the second drive input end and the third drive input end are: Connected to each other and used as the drive signal input terminal of the drive unit, the first control terminal, the second control terminal and the third control terminal of the sub-driver are the first control signal of the drive unit. 6. The synchronization according to claim 4, wherein the synchronization is used as an input terminal, the second control signal input terminal, and the third control signal input terminal. Nagareki control circuit.   The drive unit includes a main driver and a switching circuit, and the main driver includes a first drive input terminal, a second drive input terminal, a third drive input terminal, a fourth drive input terminal, a first drive output terminal, Including a second drive output end, a third drive output end, and a fourth drive output end, and the first drive input end, the second drive input end, the third drive input end, and the fourth drive input end are connected to each other. And used as the drive signal input end of the drive unit, and the open / close circuit includes a first open / close input end, a second open / close input end, a third open / close input end, a fourth open / close input end, a first open / close enable end, A second opening / closing enabling end, a third opening / closing enabling end, a fourth opening / closing enabling end, a first opening / closing output end, a second opening / closing output end, a third opening / closing output end, and the fourth opening / closing output end; The first to fourth open / close input terminals are electrically connected to the first to fourth drive output terminals of the main driver, respectively. The second to fourth open / close enable ends of the open / close circuit are used as the second to fourth control signal input ends of the drive unit, respectively, and the first to fourth open / close output ends of the open / close circuit are 6. The synchronous rectifier control circuit according to claim 4, wherein the synchronous rectifier control circuit is used as the first to fourth output terminals of the drive unit.   2. The synchronous rectifier control circuit according to claim 1, wherein the number of the power switching elements operated in the follow state and the magnitude of the output current are in direct proportion.