JP3193890B2 - Bit synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention is used for data transfer between high-speed interconnections. The present invention relates to a synchronization technique between high-speed interconnections. The present invention relates to a technique for determining a logical value of data on a high-speed interconnection at a receiving side and transferring data in synchronization with a clock synchronized with a system, when a clock is not transmitted between high-speed interconnections.

[0002]

2. Description of the Related Art Conventionally, logic value determination of a high-speed signal is performed by extracting a clock component from input data, shaping a clock, and arranging a clock synchronized with the data on the input data, based on the accuracy of the logic value determination. The method of sending and outputting is used.

[0003] This conventional example will be described with reference to FIG.
FIG. 20 is a diagram showing a configuration example of a conventional clock extraction type bit synchronization circuit. In the bit synchronization circuit of this system, first, a clock extraction circuit 30
The clock component is extracted by the voltage-controlled oscillator 3
3: Compares the phase with the clock of the VCO (Voltage Control Ocillator) output.

At this time, since the phase comparator 31 outputs a phase difference signal between the two clocks, the filter 32 removes high frequency components from the output phase difference signal, and inputs the low frequency components to the VCO 33 again. At this time, the control signal, which is a low frequency component, works so as to make the two frequencies coincide. In this manner, the output clock of the VCO 33 is applied to the VCO 3 while following the loop constituting the feedback circuit.
The output of 3 is locked to a clock synchronized with the clock component of the data, so that a synchronized clock can be output. Accordingly, the discriminator 34 determines the input data using this clock, whereby the phase relationship between the input data and the discrimination clock is always in an ideal state, so that ideal discrimination is possible.

[0005]

In such a conventional bit synchronization circuit, when the clock rate of input data increases, the overhead required for performing ideal bit synchronization cannot be ignored. For example, when bit synchronization is performed using a clock having a clock rate of 10 GHz, the input data signal is NRZ (Non Return to Zero).
o) If it is a signal, the signal width of 1 bit is only 100p
s. In this case, when discrimination is performed by the flip-flop using the clock change point, the phase margin allowed for the flip-flop constituting the discriminator is usually 50 p.
It is limited to about s to 60 ps.

Therefore, for example, in the conventional clock extraction type bit synchronization circuit shown in FIG. 20, it is necessary to stabilize the extraction clock within the above-mentioned phase margin. For this purpose, a filter 32 having a high Q value for stabilizing a clock within an allowable phase margin is provided downstream of the phase comparator 31.
It is necessary to prepare. In order to realize this by using a dielectric resonator filter, it is necessary to control the shape in an analog manner, and the size of the filter tends to be increased due to the problem of processing accuracy. Therefore, it is difficult to integrate the bit identification unit and the frequency shaping unit of the extracted clock, and the entire system of the bit synchronization circuit cannot be downsized.

The present invention has been made in view of such a background, and an object of the present invention is to provide a bit synchronization circuit which does not require a large and complicated control circuit, analog device, and the like. SUMMARY OF THE INVENTION It is an object of the present invention to provide a bit synchronization circuit capable of performing accurate logic value determination using a system clock. SUMMARY OF THE INVENTION It is an object of the present invention to provide a bit synchronization circuit which is resistant to input data waveform fluctuations and phase fluctuations.

[0008]

FIG. 2 shows the optimum positional relationship between data and clock for judging the logical value of input data.
It is shown in FIG. When a flip-flop that identifies data using a rising edge of a clock is used as a discriminator that identifies the logical value, in order to perform ideal identification, the rising edge of the clock must be at the center of the data, that is, 1 Assuming that the bit data width is 2π, it is necessary to arrange the bit data at a position shifted by π from the data change point. If identification is constantly performed on input data using clocks having such a phase relationship, ideal logical value determination will be performed.
At this time, the inverted component of the ideal clock, that is, the clock whose phase is shifted by π, has its clock rising edge coincident with the data change point.

That is, if the reverse is used, a plurality of clocks are prepared, the rising edge of the clock is detected, and if a clock that matches the change point of the input data can be selected, the logical value of the data is calculated using the inverted component. The judgment can be made ideally.

The present invention has been made based on such a viewpoint, and detects a rising edge (or a falling edge) of a clock and a change point of input data,
The most important feature is that by detecting the overlap between the two, the clock most inappropriate for identification is constantly selected, and ideal identification is performed using the inverted component clock.

The difference from the conventional technique is that the worst clock is constantly detected, the ideal clock is constantly selected by using the inverted component, and the logical value is determined. In addition to this, in addition to the data change point detection circuit, the clock rising edge (or falling edge)
There is a great difference in that an optimum clock can be selected by a selector control circuit including a detection circuit and detecting a phase difference between the two.

That is, according to the present invention, the conventional passive approach of performing identification while avoiding the worst clock is revised, and an aggressive approach of constantly detecting an optimum clock and performing identification using the clock is improved. Since this is adopted, a phase-locked loop can be constructed in which a plurality of discrete clocks are used to pseudo-lock to the input data signal. Therefore, the input data can be discriminated and determined while constantly locking to the optimum clock without using a dielectric resonator as in the related art.

Further, according to the present invention, a bit synchronization protection circuit for transmitting a selector switching signal for the first time after n consecutive bit determination errors can be provided in the selector logical value control block. It is possible to prevent the switching of the logical value determination output due to the phase fluctuation of the input data.

Further, according to the present invention, a data waveform shaping circuit can be introduced before the logical value judgment block and the logical value information holding block, so that the present invention can be implemented without depending on the input data waveform inputted to the present invention. Since it is only necessary to perform bit synchronization with respect to the data of the shaped waveform depending on the circuit used to implement the invention, the logical value can be constantly determined under the same conditions.

That is, the present invention is a bit synchronization circuit including an input terminal for inputting data synchronized with a clock, and a determination circuit for determining the data at the input terminal based on the own device clock signal. The present invention is characterized in that there is provided means for setting a clock having a change point at a time having a phase difference of about 180 degrees from the time of the change point of the data of the input terminal as its own clock supplied to the determination circuit. There.

The setting means includes: means for generating a plurality of clocks having different phases; and selecting a clock having a change point at substantially the same time as a change point of the data at the input terminal among the plurality of clocks having different phases. It is preferable to include means for performing this operation, means for inverting the clock, and means for setting the inverted clock as its own clock for inverting the data at the input terminal. Further, it is desirable that the waveform integer form circuit is inserted in the signal path of the input terminals.

[0017]

Embodiments of the present invention will be described with reference to FIG. FIG. 1 is a block diagram of a bit synchronization circuit according to an embodiment of the present invention.

According to the present invention, there is provided an input terminal IN for inputting data synchronized with a clock, and a discriminator 4 as a judgment circuit for judging the data at the input terminal IN based on its own clock signal.
And a bit synchronization circuit comprising:

Here, the feature of the present invention is that a clock having a change point at a time that is substantially 180 degrees out of phase from the time of the change point of the data at the input terminal IN is supplied to the discriminator 4 as its own clock. It is provided with a clock setting unit 9 as means for setting.

The clock setting section 9 includes a clock generation circuit 7 as means for generating a plurality of clocks having different phases.
And the input terminal I of the plurality of clocks having different phases.
A selector control circuit 5 as means for selecting a clock having a transition point at substantially the same time as the transition point of the N data, inverting this clock, and setting the inverted clock as its own clock for determining the data at the input terminal IN. And is included. The data waveform shaping circuit 1 is provided in the signal path of the input terminal IN.

[0021]

【Example】

(First Embodiment) A first embodiment of the present invention will be described. FIG. 2 is a block diagram of the data waveform shaping circuit 1. First, input data is branched into two, one input data is input to the buffer 10, and the other data is input to the inversion buffer 11. The output of each buffer 10 and inverting buffer 11 is input to two T flip-flop circuits (shown as TFF) 12 and 13, respectively. continue,
The output results of the two T flip-flop circuits 12 and 13 are respectively branched into two, and EXOR as shown in FIG.
(Exclusive OR) Circuit 14 and EXNO
An R (Exclusive NOR: Exclusive NOR) circuit 15 determines a logical value for each.

FIG. 3 is a block diagram of the data change point detection circuit 2. The data change point detection circuit 2 divides the input data into two as shown in FIG.
, And a circuit which takes EXOR (exclusive OR) of both.

FIG. 4 is a block diagram of the clock rise detection circuit 3. Clock rising detection circuit 3
As shown in FIG. 4, the clock input is divided into three branches, of which two branches have the same configuration as that of the data change point detection circuit 2 and are configured by a circuit which takes an AND (logical product) with the remaining one branch. Is done.

FIG. 5 is a block diagram of the selector control circuit 5. The selector control circuit 5, as shown in FIG.
The output of the data change point detection circuit 2 is ANDed with a plurality of clock rise detection circuits, and a part of the output is input to the set terminal of the SR-FF. At this time, the remaining output of AND is input to the reset terminal of another SR-FF. This SR-
The output of the FF is connected to a coder circuit 56 that converts an input signal into a binary code. FIG. 6 shows an example of a circuit of a coder that converts the data into binary data of two bits.

FIG. 7 is a diagram for explaining the clock generation circuit 7. In the clock generation circuit 7, as shown in FIG. 7, the data width is divided into two, and a clock whose phase is shifted so that the clock and its inverted component fall within the data width is prepared. These phase-shifted clocks and their inverted components are realized by the delay buffers 70 to 73 and the inverted buffer 74 shown in FIG.

Next, an operation example of the present invention will be described. FIG. 8 is a diagram showing the waveform observation points of the data waveform shaping circuit 1, and FIG. 9 is a diagram showing the observation results. As shown in FIG.
The data input to the data waveform shaping circuit 1 is subjected to EXOR (exclusive OR) and EXNOR (exclusive NOT OR) of the outputs of the two T flip-flops 12 and 13 described in FIG. Formatted into data. FIG. 9 shows the state of the waveform at this time.

FIG. 10 is a diagram showing the waveform observation points of the data waveform shaping circuit 1, and FIG. 11 is a diagram showing the observation results. As shown in FIG. 11, the waveform fluctuation of the input data waveform is shaped, and the T flip-flops 12 and 1
3. The signal is shaped depending on the output waveforms of the EXOR circuit 14 and the EXNOR circuit 15.

The shaped input data is thereafter branched. One of them is input to the data change point detection circuit. FIG. 12 is a diagram showing the waveform observation points of the data change point detection circuit, and FIG. 13 is a diagram showing the observation results. In the data change point detection circuit 2, the data and the data delay component E
In order to take XOR (exclusive OR), as shown in FIG. 13, a pulse having a width corresponding to the delay is generated at a position corresponding to the data change point.

At this time, the clock input to the system is branched into two, and one of the two is converted to the opposite phase component through the inversion buffer 74. The converted components are passed through delay buffers 70 and 71 to provide a phase difference between them.
Thereafter, the respective negative-phase components are input to the clock rise detection circuit 3.

FIG. 14 is a diagram showing the waveform observation points of the clock rise detection circuit 3, and FIG. 15 is a diagram showing the observation results. Here, first, a clock transition point is detected, and thereafter, an AND (logical product) of the transition point pulse and the clock is taken to detect a rising edge of the clock. The data change point pulse and the clock rise detection pulse thus detected are input to the selector control circuit 5, and the worst clock is selected by detecting coincidence between the two pulses.

FIG. 16 is a diagram showing the waveform observation points of the selector control circuit 5, and FIG. 17 is a diagram showing the observation results. This example shows a case where the rising edge of the first clock coincides with the data change point. At this time, since there is no phase difference between the two pulses, a coincidence pulse is detected by AND (logical product). At this time, since the other clock edges do not match the data change point, no match detection pulse is detected. Thereafter, the detected coincidence pulse is branched, and the set terminal of the SR-FF 53 corresponding to the first clock and the SR corresponding to clocks other than the first clock are connected.
-Input to reset terminals of FFs 54 and 55. Therefore, each time the coincidence detection pulse arrives, the SR-FF 53 corresponding to the first clock is set, and the remaining SR-Fs 53 are set.
F54 and F54 are reset. After this, SR-
The outputs of the FFs 53 to 55 are input to a coder circuit 56, converted into binary codes, and input to a selector 6 for selecting a clock having a positive phase. In this example, a selector signal for selecting a clock having an inverted component of the first clock is generated in the binary code corresponding to the first clock.

Next, the operation when the selected clock changes due to fluctuations in the data phase will be described with reference to FIG.
In this example, the edge of the n-th clock initially coincides with the data change point, but thereafter the data fluctuates and the (n + 1) -th clock
This shows a case where the edges of the clock match. As shown in FIG. 18, before the data fluctuates, a coincidence detection pulse is generated in an AND circuit (shown as ANDn) corresponding to the n-th clock, and the SR-FF corresponding to the n-th clock is generated.
(Shown as SR-FFn) and other SR-
The FF is reset, but after the data fluctuates, an AND circuit (ANDn + 1) corresponding to the (n + 1) th clock.
It can be seen that a coincidence detection pulse rises at the timing shown in FIG. 5, the SR-FF (illustrated as SR-FFn + 1) corresponding to the (n + 1) th clock is set, and the SR-FFn corresponding to the nth clock is reset. With such an operation, the selector signal changes via the coder circuit 56, and it is possible to switch from the inverted component of the nth clock to the inverted component of the (n + 1) th clock.

(Second Embodiment) FIG. 19 shows a second embodiment of the present invention.
This will be described with reference to FIG. FIG. 19 is a block diagram of the selector control circuit according to the second embodiment of the present invention. In the second embodiment of the present invention, the SR in the selector control circuit 5 of the bit synchronization circuit is
-FF a protective circuit 22 ₁ through 22 _n in place of. Each of the protection circuits 22 _{1 to} 22 _n is configured by, for example, an n-bit counter, and is configured to be set only when a detection pulse is continuously input n times. By introducing such protection circuits 22 _{1 to} 22 _n , it is possible to prevent clock movement due to sudden data phase fluctuations, and it is possible to guarantee a stable bit synchronization operation.

[0034]

As described above, according to the present invention,
An accurate logical value determination can be performed using a system clock without requiring a large and complicated control circuit or analog device. Further, it is possible to realize a bit synchronization circuit that is resistant to waveform fluctuation and phase fluctuation of input data.

[Brief description of the drawings]

FIG. 1 is a block diagram of a bit synchronization circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram of a data waveform shaping circuit.

FIG. 3 is a block diagram of a data change point detection circuit.

FIG. 4 is a block diagram of a clock rise detection circuit.

FIG. 5 is a block diagram of a selector control circuit.

FIG. 6 is a block diagram of a coder circuit.

FIG. 7 is a diagram illustrating a clock generation circuit.

FIG. 8 is a diagram showing waveform observation points of the data waveform shaping circuit.

FIG. 9 is a diagram showing a waveform observation result of the data waveform shaping circuit.

FIG. 10 is a diagram showing a waveform observation point of the data waveform shaping circuit.

FIG. 11 is a diagram showing a waveform observation result of the data waveform shaping circuit.

FIG. 12 is a diagram showing waveform observation points of the data change point detection circuit.

FIG. 13 is a diagram showing a waveform observation result of the data change point detection circuit.

FIG. 14 is a diagram showing a waveform observation point of the clock rising detection circuit.

FIG. 15 is a diagram showing a waveform observation result of the clock rising detection circuit.

FIG. 16 is a diagram showing waveform observation points of a selector control circuit.

FIG. 17 is a diagram showing a waveform observation result of a secretor control circuit.

FIG. 18 is a diagram for explaining an operation in a case where a selected clock changes due to fluctuation of the data phase of the selector control circuit.

FIG. 19 is a block diagram of a selector control circuit according to a second embodiment of the present invention.

FIG. 20 is a diagram illustrating a configuration example of a conventional clock extraction type bit synchronization circuit.

FIG. 21 is a diagram showing a positional relationship between data and a clock which is optimal for determining a logical value of input data.

[Explanation of symbols]

Reference Signs List 1 data waveform shaping circuit 2 data change point detection circuit 3 clock rise detection circuit 4, 34 discriminator 5 selector control circuit 6 selector 7 clock generation circuit 9 clock setting unit 10 buffer 11, 74 inversion buffer 12, 13 T flip-flop 14, 21, 31 EXOR circuit 15 EXNOR circuit 19 OR circuit 20, 25, 30 delay circuit 22 _{1 to} 22 _n protection circuit 32, 50 to 52 AND circuit 53 to 55 SR-FF 56 coder circuit 30 clock extraction circuit 31, 40 phase comparison Filter 32 Filter 33 VCO 70, 71 Delay buffer az, α, β, γ Observation point

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Ryusuke Kawano 3-19-2 Nishi-Shinjuku, Shinjuku-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Inventor Kohei Shiomoto 3-19, Nishishinjuku, Shinjuku-ku, Tokyo No. 2 Within Nippon Telegraph and Telephone Corporation (56) References JP-A-4-13325 (JP, A) JP-A-5-102954 (JP, A) JP-A-3-240336 (JP, A) (58) ) Surveyed field (Int.Cl. ⁷ , DB name) H04L 7/02 H04L 25/40

Claims (2)

(57) [Claims] An input terminal for inputting data synchronized with a clock, a judgment circuit for judging data input to the input terminal by a clock signal of its own device , and a judgment circuit for the judgment circuit.
Clock setting method for setting the clock signal of the own device to be supplied
In the bit synchronization circuit and a stage, said clock setting means, a plurality of phase from a single clock
Clock group consisting of different clocks
Means for generating an inverted clock group having a phase opposite to that of the clock group;
A plurality of clocks having different phases of the one clock group.
A change point and a change point of the input signal data are detected and detected.
For selecting a clock at which the change points of the clocks are almost the same time
And 180 degrees out of phase with this selected clock
Selecting a clock from the other inverted clock group and
Bit synchronization circuit, characterized in that it includes a setting means for setting a clock of the apparatus for supplying to the decision circuit. 2. A bit synchronization circuit of claim 1, wherein the waveform integer form circuit is inserted in the signal path of the input terminals.