JP3190865B2 - Delay detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay detection circuit, and more particularly to a delay detection circuit for a communication device such as an FM teletext receiver using digital circuit technology.

[0002]

2. Description of the Related Art With the advancement of digital circuit technology and semiconductor technology, digital circuits have been widely used in the field of communication devices such as this type of FM teletext receiver.

For example, Kenji Miwa et al., "Development of Decoder LSI for FM Teletext Broadcasting", Sharp Giho, No. 63,
A conventional delay detection circuit for an FM text multiplex broadcasting receiver described in Sharp Corporation, pp. 63-66 (Document 1), December 1995, is a digital signal obtained by quantizing an input analog signal and performing a predetermined filtering process. And a delay detection unit that performs a delay detection process on the signal. The delay detection unit is larger than a theoretical value of a quantization error noise level in order to secure an operation margin for preventing an erroneous response to noise caused by a quantization error. A certain level was set as the detection threshold.

FIG. 5 is a block diagram showing a conventional delay detection circuit.
Referring to FIG. 1, this conventional delay detection circuit has an input FM
An amplification unit 1 that receives the supply of the composite signal SI and outputs an FM composite amplification signal SA; and a second-order ΔΣ-type AD conversion (ADC) unit that quantizes the supplied FM composite amplification signal SA and converts it into a quantized signal Q. 2, a third-order moving average type thinning-out filter 3 for thinning out the quantized signal Q to 1/16 to output a thinning-out filter signal P, and attenuating the audio band of the supplied filter signal P to obtain a predetermined high frequency A high-pass filter (HPF) 4 that passes a band and outputs a high-pass filter signal HS, and a band-pass filter 5 that extracts a band-pass signal DI having a band of 76 KHz ± 10 KHz from the supplied high-pass filter signal HS.
And delay detection processing of the bandpass signal DI to detect the detection signal DO.
And a low-pass filter (LPF) 7 for removing a high-frequency component of the detection signal DO and outputting a detection output signal SO.

Next, the operation of the conventional delay detection circuit will be described with reference to FIG. 5. Since this conventional delay detection circuit is for an FM teletext receiver, a known FM teletext signal is used. From the format, the L + R component on the lower side and the L on the upper side around the stereo pilot signal 19 KHz
Each frequency signal of a -R component and a character multiplexed signal component of 76 KHz ± 4 KHz is input.

First, the amplifying unit 1 amplifies the supplied FM composite signal SI so as to match the input level of the ADC unit 2 in the next stage, outputs an FM composite amplified signal SA, and supplies it to the ADC unit 2. I do. Next, the ADC unit 2 is a known oversampling type ΔΣ ADC. That is, it is a second-order ΔΣ type with a sampling frequency of 4.864 MHz and 64 times oversampling, performs AD conversion on the FM composite amplified signal SA and has a data rate of 4.86.
The quantized signal Q having a 1-bit width of 4 MHz is output and supplied to the thinning filter 3.

The decimating filter 3 is of a third-order moving average type, decimates the quantized signal Q to 1/16, outputs a decimated signal P as a result of 11-bit width digital conversion at a data rate of 304 KHz, and supplies it to the HPF 3. . Next, HP
F3 is a 6th-order IIR (infinite impulse response) type digital filter that attenuates the audio band of the supplied filter signal P, passes a frequency band of 60 KHz or more, outputs a high-pass filter signal HS, and outputs it to the BPF5. Output. The BPF 5 is a 23-tap FIR (finite impulse response) type digital filter, extracts a bandpass signal DI having a band of 76 KHz ± 10 KHz from the high-pass filter signal HS, and supplies it to the delay detection unit 6.

Next, the delay detection section 6 comprises a 19-stage shift register and exclusive logic of the MSB and LSB of the shift register, and the time slot (1T) delay time is 62.5
μs and a sampling frequency of 304 KHz. That is, it corresponds to 19 band pass signals DI in the preceding stage.
In response to the supply of the band-pass signal DI, delay detection is performed by comparing the data with 1T of past data, and a detection signal DO is output and supplied to the LPF 7. LPF7 is secondary I
This is an IR filter that removes unnecessary high-frequency components contained in the detection signal DO and outputs a detection output signal SO consisting of 1-bit wide character data at a data rate of about 16 KHz.

In the above operation, noise such as a quantization error in the ADC unit 2 and the amplification unit 1 may further increase from the theoretical value due to factors such as a low-quality power supply having much noise. In the detection circuit, the erroneous response due to the noise is prevented by sacrificing the signal processing dynamic range by setting the threshold value of the signal detection to a large value.

As an example, the signal processing dynamic range D for FM character multiplex broadcasting receivers A to D having four types of characteristics in which the relationship between the threshold value TH and the noise level NL is different.
Referring to FIG. 6, which shows the relationship between R and the noise level NL in a graph, the signal processing dynamic range DR of each receiver shown in this diagram is in the range from the threshold value TH indicated by a thick solid line to 0 dB. The reception limit value RGL is indicated by a broken line.

The receiver A having a small noise level NL and a threshold value TH sufficiently higher than the noise level NL has a sufficiently large reception sensitivity margin RSM, which is a difference between the reception limit value RGL and the threshold value TH, and a sufficiently large noise margin NM. Since it is large, the noise existence region (noise floor) does not fall within the dynamic range DR, and therefore, no erroneous response occurs in the delay detection. However, since the signal below the threshold value TH cannot be detected, the receiving sensitivity is sacrificed accordingly.

Each of the other receivers B to D has a threshold T
Since H is equal to or less than the noise level NL, the noise margin NM is eliminated and the receiving sensitivity can be maximized, but an erroneous response in the delay detection occurs because the noise floor exists within the dynamic range DR.

Therefore, in order to improve the power supply quality such as reducing the noise level of the power supply, it is necessary to make adjustments such as improving the wiring such as separating the power supply wiring from the noise source.

[0014]

In the conventional delay detection circuit described above, in order to prevent an erroneous response due to noise such as a quantization error, the threshold value for signal detection is sacrificed at the expense of input sensitivity. Is fixed at a constant level value with a sufficient margin so as to be equal to or greater than the noise existence area, so that the input signal level fluctuates greatly, as in mobile reception, etc. However, there is a drawback that it is impossible to optimize the system input sensitivity in a usage method of giving priority to the reception sensitivity.

Further, in order to suppress the increase in the quantization noise level due to the low-quality source, it is necessary to make adjustments such as improving the wiring such as separating the power supply wiring from the noise source. There was a drawback that it became a factor.

An object of the present invention is to provide a delay detection circuit capable of setting an optimum reception margin capable of suppressing sacrifice of reception sensitivity to a minimum and reducing erroneous responses, and eliminating a cost increase factor such as adjustment. It is in.

[0017]

SUMMARY OF THE INVENTION A delay detection circuit of the present invention quantizes an input analog signal to be subjected to delay detection and outputs a quantized signal. The analog-to-digital conversion means performs a predetermined filtering process on the quantized signal. A delay detection circuit comprising: digital filter means for outputting a filter signal; and delay detection means for performing a predetermined delay detection process on a detection input signal corresponding to the filter signal and outputting a detection output signal. The detection circuit is provided with a threshold varying means for varying a signal detection threshold and generating the detection input signal.

[0018]

FIG. 5 shows an embodiment of the present invention.
Referring to FIG. 1, which is similarly denoted by a block with common reference characters / numerals attached to common components, the delay detection circuit of this embodiment shown in FIG.
An amplification unit 1 that receives the supply of the composite signal SI and outputs an FM composite amplification signal SA; and a second-order ΔΣ-type AD conversion (ADC) unit that quantizes the supplied FM composite amplification signal SA and converts it into a quantized signal Q. 2, a delay detection unit 6 for delay-detecting the input signal DI and outputting a detection signal DO
In addition to the above, the quantized signal Q
4A thinning filter 3A that outputs a 16-bit thinning filter signal PA by thinning out 1/16
And a band-pass filter 5A for extracting a band-pass signal HB having a band of 76 kHz ± 10 kHz from the thinning-out filter signal PA instead of the band-pass filter 5, and a slice level of the band-pass signal HB is varied according to the value of the threshold value TH1. A level determining unit 12 for generating a delayed detection input signal DI, a numerical conversion unit 13 for performing a predetermined numerical conversion of the detection signal DO and outputting a converted detection signal DA, and a low-pass detection for removing a high frequency component of the converted detection signal DA. A low-pass filter (LPF) 7 for outputting a signal SD, and a threshold value TH2
Level determining section 14 for determining the result of comparison between the threshold value and low-pass detection signal SD and outputting detection output signal SO, register 11 for storing threshold value TH1, and threshold value TH2
And a microcomputer (MC) 16 for setting the threshold value TH1 in the register 11.

Next, the operation of the present embodiment will be described with reference to FIG.
It is assumed that it is used for an FM teletext receiver as in the conventional case. Therefore, from the signal format of the teletext broadcasting, the L + R component is located below the stereo pilot signal at 19 KHz, the LR component is located above, and 76 KHz ± 4 KHz.
Are input.

First, the amplifier 1 amplifies the supplied FM composite signal SI so as to match the input level of the ADC 2 at the next stage, outputs an FM composite amplified signal SA, and supplies the amplified signal to the ADC 2. I do. Next, the ADC unit 2 is a sampling frequency 4.864 MHz, a 64 times oversampling second order ΔΣ type, AD-converts the FM composite amplified signal SA, and converts the 1-bit quantized signal Q having a data rate of 4.864 MHz into one bit. Output and thinning filter 3
A.

The bandwidth of the FM composite signal SI is 1K
Hz and the quantized signal Q converted at 4.864 MHz
With reference to FIG. 2 showing the spectrum of
To explain the / N (SN ratio), the signal processing band BS shown in this figure is 76 KHz ± 10 KHz, and the S / N in this signal processing band BS is about 65 db. This value is similar to the theoretical SNR SNL when 76 KHz is converted at 4.864 MHz.

Next, the decimation filter 3A is a fourth-order moving average type, and decimates the quantized signal Q having a data rate of 4.864 MHz to 1/16 to obtain a decimation signal which is a 16-bit digital signal having a data rate of 304 KHz. The PA is output and supplied to the BPF 5A.

Next, the BPF5A is a 65 tap FIR
(Finite impulse response) type digital filter,
A band pass signal HB having a band of 76 KHz ± 10 KHz is extracted from the thinned-out signal PA and supplied to the level determination unit 12.

The S / N of the bandpass signal HB will be described with reference to FIG. 3 which shows the characteristics of the BPF 5A in a graph.
Since A is 16 bits, 16-bit arithmetic processing is performed, and therefore, the theoretical value of the dynamic range DR is 96 db. Further, from the lower limit level DMIN of the signal based on the dynamic range DR, the theoretical SN ratio SN
The noise level of L is large.

Therefore, in order to prevent an erroneous response due to noise, the level determination section 15 compares the bandpass signal HB output from the BPF 5A with the threshold value TH1 from the register 11, and 1 is output as the differential detection input signal DI, and is 1 when the value is large, and 0 otherwise.

The register 11 can set the threshold value setting data THN of an arbitrary value from the MC 16 as a new threshold value TH1 at any time in response to the supply of the update control signal CR from the MC 16.

F characteristics of four types having different noise levels NL
Signal processing dynamic range DR, threshold value TH1, and noise level N for receivers A to D for M teletext broadcasting
Referring to FIG. 4 which graphically shows the relationship with L, threshold T
Explaining the setting of H1, the signal processing dynamic range DR of each receiver shown in FIG.
B. The reception limit value RGL is indicated by a broken line.

As shown in this figure, the threshold value TH1 of each of the receivers A to D is set higher than the noise level NL. In this way, for various noise levels NL and reception limit levels RGL that differ for each receiver,
Threshold value TH to register 11 by setting data THN
By changing 1, a false detection response is prevented, and
An optimum threshold value TH1 that can hold the sensitivity at the maximum can be set.

That is, by setting the threshold value TH1 higher than the noise level NL, a delay detection input signal DI having a sufficient noise margin NH is obtained, and an erroneous detection response (error) of the delay detection unit 6 is prevented. Further, by setting the threshold value TH1 lower than the reception limit level RGL, it is possible to obtain the differential detection input signal DI in which the reception sensitivity margin RGM is sufficiently secured.

Specifically, an error rate (erroneous response rate) is measured by an error rate measuring device or the like while changing the threshold value TH1, and the threshold value TH1 at which a desired error rate can be obtained can be determined. The margin NM can be optimized. Therefore, the threshold value TH1 is set in the register 11 so that the reception sensitivity margin RGM is large and the noise margin NM is optimal.

Next, the delay detection section 6 comprises a shift register having the same time slot (1T) delay time of 62.5 μs and a sampling frequency of 304 KHz as in the prior art, and responds to the supply of the delay detection input signal DI by 1T. The delay detection is performed by comparing the data with the past data, and a detection signal DO is output.

Next, the numerical converter 13 uses the 1-bit detection signal DO as a pre-process of the low-pass processing in the LPF 7A at the next stage. If the detection signal DO is 1, it is 128;
The conversion of 128 is performed, and a conversion detection signal DA having a 16-bit width is output.

The reason why this numerical conversion process is necessary will be described. The LPF 7A is a conversion detection signal D having a 16-bit width.
A 16-bit operation is performed to process A.
It has a dynamic range of about 96 db. Also,
Since the conversion detection signal DA is a square wave, this signal D
The spectrum of the input signal is made larger than the low-order harmonic spectrum in order to prevent a response when the spread of the low-order harmonic spectrum of A enters the pass band.

Next, the LPF 7A is a 27-tap FIR
The filter removes unnecessary high-frequency components contained in the conversion detection signal DA, that is, a low-order harmonic spectrum, and outputs a 1-bit low-pass detection signal SD having a data rate of about 16 KHz.

The level judging section 14 compares the threshold value TH2 from the register 15 with the level of the low-pass detection signal SD. The detection output signal SO becomes 1 if the low-pass detection signal SD is large, and becomes 0 otherwise. Is output.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made. For example, the present invention can also use a combination of a conventional high-pass filter and a band-pass filter instead of the band-pass filter of the present embodiment, and use an ADC of a successive approximation type or the like instead of the oversampling ADC. It goes without saying that the present invention can be applied as long as it does not depart from the gist of the present invention.

[0037]

As described above, the delay detection circuit of the present invention is provided with threshold variable means for varying the signal detection threshold in the delay detection circuit for the filter signal and generating a detection input signal. In addition, it is possible to set an optimum operating point at which the reception sensitivity margin is large and the noise margin is optimum.

Further, even if the quantization noise is increased from the theoretical value due to a low-quality power supply or the like, it is not necessary to adjust the wiring by changing wiring or adding components, so that the factor of cost increase can be eliminated. This has the effect.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a differential detection circuit according to the present invention.

FIG. 2 is a characteristic diagram illustrating an example of a spectral characteristic of the ADC unit in FIG. 1;

FIG. 3 is a characteristic diagram showing an example of a band characteristic of the BPF of FIG. 1;

FIG. 4 is a receiver 4 using the delay detection circuit according to the present embodiment.
It is a characteristic view showing an example of the kind of S / N characteristics.

FIG. 5 is a block diagram illustrating an example of a conventional delay detection circuit.

FIG. 6 shows four types of S / S signals of a receiver using a conventional delay detection circuit.
FIG. 9 is a characteristic diagram illustrating an example of an N characteristic.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Amplification part 2 ADC part 3, 3A Decimation filter 4 HPF 5, 5A BPF 6 Delay detection part 7, 7A LPF 11, 15 Register 12, 14 Level judgment part 13 Numerical conversion part

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H04H 5/00

Claims (7)

(57) [Claims] 1. An analog-to-digital converter for quantizing an input analog signal to be subjected to differential detection and outputting a quantized signal; a digital filter for outputting a filter signal by performing a predetermined filtering process on the quantized signal; A delay detection means for performing a predetermined delay detection process on the detection input signal corresponding to the signal and outputting a detection output signal, wherein a signal detection threshold value in the delay detection circuit is varied with respect to the filter signal. A delay detection circuit comprising a threshold varying means for generating a detection input signal. 2. The apparatus according to claim 1, wherein said threshold varying means includes a level determination circuit for generating said detection input signal in accordance with a comparison result between an arbitrarily set comparison value and a level of said filter signal. The delay detection circuit according to claim 1. 3. The delay detection circuit according to claim 1, wherein said threshold value changing means includes a register for storing said comparison value supplied in response to control of a control signal. 4. The delay detection circuit according to claim 1, wherein the input analog signal is an FM text multiplex broadcast signal. 5. A ΔΣ-type analog-to-digital converter for quantizing an FM composite signal, which is an input analog signal, and converting it into a quantized signal, and thinning out the quantized signal to a predetermined integer, and thinning out a predetermined bit width A decimation filter that outputs a filter signal, a bandpass filter that extracts a bandpass signal of a predetermined band from the decimation filter signal, and a delay detection unit that performs delay detection on the detection input signal corresponding to the bandpass signal and outputs a detection signal. A low-pass filter for removing a high-frequency component of the detection signal and outputting a detection output signal composed of character data, wherein a signal detection threshold value in the delay detection circuit is varied with respect to the band-pass signal. A delay detection circuit comprising a threshold varying means for generating a detection input signal. 6. The apparatus according to claim 1, wherein said threshold value changing means includes a level determination circuit for generating said detection input signal in accordance with a comparison result between an arbitrarily set comparison value and a level of said filter signal. The delay detection circuit according to claim 5. 7. The delay detection circuit according to claim 5, wherein said threshold value changing means includes a register for storing and setting said comparison value supplied in response to control of a control signal.