JP3189783B2 - Variable data width crossbar switch device, connection method therefor, and recording medium recording control program therefor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable data width type crossbar switch device, a method of connecting the same, and a recording medium on which a control program is recorded, and more particularly to a crossbar switch device for connecting ports having different data widths.

[0002]

2. Description of the Related Art Conventionally, in this type of crossbar switch device, as shown in FIG.
1 to # 3) 2-1 to 2-3 and a memory board (# 1 to # 3)
3) 3-1 to 3-3 and I / O (input / output) boards (# 1 to # 3)
# 6) 4-1 to 4-6 are mutually connected via the crossbar switch 5.

In this case, the processor boards (# 1 to ##)
3) 2-1 to 2-3 and memory board (# 1 to # 3) 3-
1-3 and I / O (input / output) board (# 1- # 6) 4
-1 to 4-6 have different data widths. That is, the crossbar switch 5 connects ports having different data widths.

Here, the processor board (# 1) 2-1
40, a processor 21-1, a controller 22-1, an input buffer 23-1, and an output buffer 24-1 are mounted, as shown in FIG. Interconnected.

Although not shown, the other processor boards (# 2, # 3) 2-2, 2-3 have the same configuration as the above-mentioned processor board (# 1) 2-1. Although not shown as above, the memory board (#
1 to # 3) 3-1 to 3-3 and I / O (input / output) boards (# 1 to # 6) 4-1 to 4-6 also have memory and I / O instead of the processor 21-1. Otherwise, the configuration is the same as that of the above-described processor board (# 1) 2-1.

In the above crossbar switch device, the controller 22-1 controls the input buffer 23-1 and the output buffer 24-1 to perform communication between ports having the same data width.

[0007]

In the above-described conventional crossbar switch device, the crossbar switch connects between ports having different data widths. However, when the crossbar switch connects between different data widths, the data width becomes narrow. When communicating with a port, data cannot be transferred to / from a port with a wide data width.

The above problem can be solved by preparing a transfer path having a wide data width separately for a portion of the memory or the like where a simultaneous access request is likely to occur. And the amount of hardware increases.

Further, the above problem can be solved by providing a plurality of ports having a narrow data width on the same board in place of the ports having a wide data width. However, the board is connected to a crossbar switch. A plurality of address lines and controllers are required, resulting in a large increase in the amount of hardware.

[0010] Therefore, an object of the present invention is to solve the above-mentioned problems, and to increase the data width of a destination port even when communicating with a narrow data port in a wide data port connected to a crossbar switch. It is an object of the present invention to provide a variable data width crossbar switch device capable of performing communication regardless of the connection method, a connection method thereof, and a recording medium recording a control program therefor.

[0011]

SUMMARY OF THE INVENTION A variable data width crossbar switch device according to the present invention has a plurality of ports of the same data width to which a plurality of boards are connected, respectively, and the plurality of ports are connected via the plurality of ports. A variable width crossbar switch device for connecting boards , wherein the boards communicate with each other.
A board with a wide data width when the data widths are different
Detects a free port among the connected ports.
Detection means, and a port detected by the detection means
Means for communicating with another board, wherein said data width
Configured to assign the plurality of ports to a wide board
And the detecting means divides the data into wide boards.
Search for available ports from among the assigned ports.
Configured to output the communication to the previous board between which the communication
Use one address line for communication with other boards.
I am trying to do it.

[0012]

A method of connecting a variable data width crossbar switch device according to the present invention includes a plurality of ports having the same data width to which a plurality of boards are respectively connected, and connects the plurality of boards via the plurality of ports. a method of connecting data width variable crossbar switch device connected, volume communicating
When the data width of each code is different,
Detect an available port among the ports to which the
And other ports via the detected port.
Performing communication with the data width.
Assign the ports to a wide board,
The step of detecting the vacant port includes the step of
In multiple ports assigned to wide boards
Detect free ports and communicate
One board is used for communication between boards and for communication with the other board.
This is done using address lines .

[0014]

A recording medium storing a connection control program according to the present invention has a plurality of ports having the same data width to which a plurality of boards are respectively connected, and connects the plurality of boards via the plurality of ports. A recording medium recording a connection control program for causing a processor to perform processing, wherein the connection control program is transmitted to the processor by a communication medium.
When the data width of the boards to be
Of the ports to which the wide board is connected
Port is detected and another port is detected via the detected port.
Communication with the port and detect the vacant port.
The data assigned to the board with the wider data width.
To detect free port among several ports, the
Communication between boards to communicate and communication with the other boards
Using one address line .

[0016]

That is, when the data widths of the boards to communicate with each other are different from each other, the data width variable type crossbar switch device of the present invention communicates with another board at an open port of the board having a port with a wider data width. I can do it.

That is, an in-board switch is provided to distribute data for each communication partner. In addition, in the data section, in addition to the switches in the board, two systems of buffer groups having the same data width as the maximum data width of the wide data port are provided.
The data distributed by the switches in the board are stored. The on-board switch control unit instructs each switch (SW) provided on the on-board switch based on a signal from the on-board address control unit on the path of input / output data.

As described above, by having a mechanism for storing two systems of data and a control mechanism for distributing data, it is possible to divide and use a port to a crossbar switch in a board having a port having a wide data width. It becomes possible.

[0020]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a crossbar switch device according to one embodiment of the present invention. In the figure, a crossbar switch device 1 includes a crossbar switch 5 and crossbar switch side input / output units 6-1 to 6--6.
4 and a wide data width processor board (# 1,
# 2) 2-1 and 2-2 and memory board (# 1 and # 2)
Data parts 7-1 to 7-4 corresponding to 3-1 and 3-2, respectively.
And address control units 8-1 to 8-4.

The crossbar switch 5 has twelve 128-bit ports and has a data width of 128 bits.
(Input / Output) Boards (# 1 to # 4) 4-1 to 4-4 are 12
Connected directly to an 8-bit port and the data width is 256
The processor boards 2-1 and 2-2 having a bit width and the memory boards 3-1 and 3-2 are respectively connected to two 128-bit ports.

That is, the crossbar switch device 1 includes the processor boards 2-1 and 2-2 and the memory boards 3-1 and 2-1.
3-2 is connected via the crossbar switch side input / output units 6-1 to 6-4 connected to the two ports of the crossbar switch 5.

The crossbar switch side input / output unit 6-1
6-4, the data units 7-1 to 7-4, and the address control units 8-1 to 8-4 when the data widths of the boards to communicate with each other are different (for example, the processor board 2).
-1 and 2-2 and the memory boards 3-1 and 3-2 are I / O
The board (# 1 to # 4) has a data width larger than that of 4-1 to 4-4), and communication with another board can be performed through an empty port of the board having a port with a wider data width. .

That is, an in-board switch (not shown) is provided in each of the data units 7-1 to 7-4 to distribute data to each communication partner. In addition, the data sections 7-1 to 7-4 are provided with two systems of buffers (not shown) having a width of 256 bits in addition to the switches in the board. Saved in.

An on-board switch control unit (not shown) provided in each of the address control units 8-1 to 8-4 routes a path of input / output data based on a signal from the on-board address control unit (not shown). Instruct each switch (SW) provided in the inner switch.

As described above, by having a mechanism for storing two systems of data and a control mechanism for distributing the data, the port to the crossbar switch 5 in the board having a port having a wide data width can be divided and used. Becomes possible.

In one embodiment of the present invention, the crossbar switch device 1 is of an address / data separation type, and uses an address line and secures a communication path by a predetermined signal, and starts and ends transfer. And implement a mechanism that can input and output appropriate data.

FIG. 2 is a block diagram showing the configuration of the crossbar switch side input / output unit 6-1 of FIG. In the figure, the crossbar switch side input / output unit 6-1 includes a crossbar switch side address control unit 61-1.

The crossbar switch side input / output unit 6-1 is connected to two ports of the crossbar switch 5 by an address line (A) and a 128-bit data line (D), and is connected to the processor board 2-1 by an address line (A). And the identification bit (bi
t) (Sa, Sb) and two 128-bit data lines (a, b).

The crossbar switch side address controller 61-
1 inputs addresses from two ports and outputs an address and an identification bit to the processor board 2-1.
Although not shown, the other crossbar switch side input / output units 6-1 to 6-4 have the same configuration as the above crossbar switch side input / output unit 6-1.

FIG. 3 is a block diagram showing the configuration of the data section 7-1 of FIG. In the figure, a data section 7-1 includes an on-board switch 71-1 and buffers 72-1 and 73-1.
And switches (SW # 1 to SW # 3) 74-1, 75-
1, 76-1, buffer A group 77-1, buffer B
Group 78-1. Note that the other data part 7
-2 to 7-4 have the same configuration as the data section 7-1.

FIG. 4 shows the address control unit 8- of FIG.
1 is a block diagram showing a configuration of FIG. In the figure, an address control unit 8-1 includes an on-board address control unit 81.
-1 and an in-board switch control unit 82-1. The other address control units 8-2 to 8-4 have the same configuration as that of the address control unit 8-1.

FIG. 5 is a block diagram showing the configuration of the in-board switch 71-1 of FIG. In the figure, the in-board switch 71-1 is a switch (SW # 11 to SW # 20)
71a-1 to 71j-1.

FIG. 6 is a diagram showing a configuration example of the switch.
FIG. 6A shows the switches (SW # 2, SW #) shown in FIG.
3) 75-1 and 76-1 and the switch (SW) shown in FIG.
# 11 to SW # 16) 71a-1 to 71f-1 are shown. FIG. 6B shows the switch (SW # 1) 7 shown in FIG.
4-1 and the switches (SW # 17 to SW # 2) shown in FIG.
0) shows the configuration of 71g-1 to 71j-1.

FIG. 7 is a block diagram showing the configuration of the crossbar switch-side address control section 61-1 shown in FIG. The crossbar switch-side address control unit 61-1 includes a controller 61a-1, a memory (A) 61b-1, and a memory (B) 61c-1.

FIG. 8A shows the memory (A) 61b-
8 is a diagram showing the storage contents of the memory (B) 61c-1 of FIG. 7. In these figures, the memory (A) 61b-1 has a board name (processor # 1, processor # 2, memory # 1, memory # 2, I / O # 1, I / O # 2, I / O # 3). , I / O
# 4) and port names (a, b) are stored in association with each other.

The memory (B) 61c-1 stores the communication destination board name of port a and the communication destination port name of port a, and the communication destination board name of port b and the communication destination of port b. Port names are stored in association with each other.

FIG. 9 shows the in-board address control unit 81 of FIG.
FIG. 3 is a block diagram showing a configuration of -1. In the figure, an in-board address control section 81-1 is provided with a controller 81a-1.
, A memory (C) 81b-1 and a memory (D) 81c-
1 and counters 81d-1 to 81g-1.

FIG. 10A shows the memory (C) 81b of FIG.
FIG. 10B is a diagram showing the storage contents of the memory (D) 81c-1 in FIG. 9. In these figures, the value of the current identification bit Sa and the value of the current identification bit Sb are stored in the memory (C) 81b-1.
The value of the identification bit Sa one clock before and the value of the identification bit Sb one clock before are stored.

The memory (D) 81c-1 stores address information and data transmission order information for the buffer A group 77-1 and address information and data transmission order information for the buffer B group 78-1. ing.

Here, the address information AA1, AA2, A
.., A3, AA4,... Indicate the contents of address line signals transmitted in relation to the data entered into the buffer A group 77-1, and the data transmission order information NAA1, NAA2, NAA3.
NAA4,... Indicate how many data from the beginning of the block have been sent at the same time as the contents of the corresponding address line signal.

Address information AB1, AB2, AB3, A
B4,... Indicate the contents of the address line signals transmitted in relation to the data entered into the buffer B group 78-1, and the data transmission order information NAB1, NAB2, NAB3, NAB4.
.. Indicate the number of data sent simultaneously with the contents of the corresponding address line signal from the head of the block.

FIG. 11 shows the on-board switch controller 8 of FIG.
Switch (SW # 1 to SW # 3) 7 of FIG. 3 according to 2-1
4-1 to 76-1 and the switches (SW # 11 to S #
W # 20) is a diagram showing control of 71a-1 to 71j-1.

The in-board switch controller 82-1 connects the port a to the port c of the in-board switch 71-1 shown in FIGS. 3 and 5 (a → c) and connects the port b to the port d. (B → d), switch (SW #)
11) 71a-1 and switch (SW # 13) 71c-1
And switch (SW # 16) 71f-1 and switch (SW # 16)
# 18) 71h-1 is connected to the “0” side, and the switch (SW # 12) 71b-1 and the switch (S
W # 17) 71g-1 is controlled to be connected to the "1" side.

At this time, the switches (SW # 1 to SW # 3)
74-1 and 76-1 and switch (SW # 14) 71d-
1 and switch (SW # 15) 71e-1 and switch (S
W # 19) 71i-1 and switch (SW # 20) 71j
-1 may be connected to either the “1” side or the “0” side. In FIG. 11, this state is indicated by "-".

The on-board switch control unit 82-1 performs the following operations when connecting from the port a to the port e of the on-board switch 71-1 (a → e) and when connecting from the port b to the port f (b → f). Switch (SW # 2) 75-1, switch (SW # 3) 76-1, and switch (SW # 11) 7
1a-1 and the switch (SW # 20) 71j-1 are controlled to be connected to the "0" side.
2) 71b-1, switch (SW # 13) 71c-1, switch (SW # 16) 71f-1, and switch (SW #
19) Control is performed so that 71i-1 is connected to the "1" side.

At this time, the switch (SW # 1) 74-1, the switch (SW # 14) 71d-1 and the switch (SW #
15) 71e-1 and switch (SW # 17) 71g-1
And the switch (SW # 18) 71h-1 may be connected to either the “1” side or the “0” side.

The in-board switch control section 82-1 switches the switch (SW # 2) 75 when connecting from the port a to the ports c and d of the in-board switch 71-1 (a → c, d).
-1 and the switch (SW # 3) 76-1 are controlled to be connected to the "0" side. The in-board switch control unit 82-1 switches the switch (SW # 11) 71a-1 to the "1" side and the "0" side in synchronization with the clock of the crossbar switch 5, and sets the switch (SW # 13) 71c- A switch (SW) is connected to either the “1” side or the “0” side and the “0” side.
# 14) 71d-1 is on the “0” side and one of the “1” side and “0” side, and the switch (SW # 17) 71g-1 is on the “1” side and one of the “0” side and “1”. The switch (SW # 18) 71h-1 is controlled to be repeatedly and alternately connected to the "1" side and any of the "1" and "0" sides.

At this time, the switch (SW # 1) 74-1 and the switch (SW # 12) 71b-1 and the switch (SW #
15) 71e-1 and switch (SW # 16) 71f-1
And switch (SW # 19) 71i-1 and switch (SW # 19)
# 20) 71j-1 may be connected to either the “1” side or the “0” side.

The on-board switch control unit 82-1 switches the switch (SW # 2) 75 when connecting from the port a to the ports e and f of the on-board switch 71-1 (a → e, f).
-1 and the switch (SW # 3) 76-1 are controlled to be connected to the "0" side. The in-board switch control unit 82-1 switches the switch (SW # 11) 71a-1 to the "1" side and the "0" side in synchronization with the clock of the crossbar switch 5, and sets the switch (SW # 13) 71c- A switch (SW) is connected to either the “1” side or the “0” side and the “1” side.
# 14) 71d-1 is on the “1” side or any of the “1” side and “0” side, and the switch (SW # 19) 71i-1 is on the “1” side or any of the “0” side and “1” side. The switch (SW # 20) 71j-1 is repeatedly and alternately connected to the "1" side and any of the "1" and "0" sides.

At this time, the switch (SW # 1) 74-1, the switch (SW # 12) 71b-1 and the switch (SW #
15 to SW # 18) 71e-1 to 71h-1 may be connected to either the "1" side or the "0" side, respectively.

The on-board switch control section 82-1 switches the switch (SW # 2) 75 when connecting from the port b to the ports c and d of the on-board switch 71-1 (b → c, d).
-1 and the switch (SW # 3) 76-1 are controlled to be connected to the "0" side. Further, the in-board switch control unit 82-1 switches the switch (SW # 12) 71b-1 to the "1" side and the "0" side in synchronization with the clock of the crossbar switch 5, and switches (SW # 15, SW #). 17) 71e-
The switch (SW # 16, SW # 18) 7 is connected to either the “1” side or the “0” side and the “0” side.
1f-1 and 71h-1 are "0" side, "1" side and "0" side.
It is controlled so that it is connected alternately and alternately to one of the sides.

At this time, the switch (SW # 1) 74-1 and the switch (SW # 11) 71a-1 and the switch (SW #
13) 71c-1 and switch (SW # 14) 71d-1
And switch (SW # 19) 71i-1 and switch (SW # 19)
# 20) 71j-1 may be connected to either the “1” side or the “0” side.

The on-board switch control section 82-1 switches the switch (SW # 2) 75 when connecting from the port b to the ports e and f of the on-board switch 71-1 (b → e, f).
-1 and the switch (SW # 3) 76-1 are controlled to be connected to the "0" side. The in-board switch control unit 82-1 switches the switch (SW # 12) 71b-1 to the "1" side and the "0" side in synchronization with the clock of the crossbar switch 5, and sets the switch (SW # 15) 71e- A switch (SW) is connected to either the “1” side or the “0” side and the “1” side.
# 16) 71f-1 is on the “1” side or any of the “1” and “0” sides, and the switch (SW # 19) 71i-1 is on the “1” side or any of the “0” side and “0”. And the switch (SW # 20) 71j-1 is repeatedly and alternately connected to the "0" side and either the "1" side or the "0" side.

At this time, the switch (SW # 1) 74-1, the switch (SW # 11) 71a-1 and the switch (SW #
13) 71c-1 and switch (SW # 14) 71d-1
And switch (SW # 17) 71g-1 and switch (SW # 17)
# 18) 71h-1 may be connected to either the “1” side or the “0” side.

The on-board switch control section 82-1 switches the switch (SW # 2) 75 when connecting from the ports c and d to the port a of the on-board switch 71-1 (c, d → a).
-1 and the switch (SW # 3) 76-1 are controlled to be connected to the "1" side. Further, the in-board switch control unit 82-1 switches the switch (SW # 11) 71a-1 to the "0" side and the "1" side in synchronization with the clock of the crossbar switch 5, and sets the switch (SW # 13) 71c- 1 is switched to the “0” side and to either the “1” side or the “0” side by a switch (SW
# 14) 71d-1 is on either the “1” side or “0” side and “0” side, and the switch (SW # 17) 71g-1 is on the “1” side, “1” side and “0” side. And the switch (SW # 18) 71h-1 is repeatedly and alternately connected to either the "1" side or the "0" side and the "1" side.

At this time, the switch (SW # 1) 74-1, the switch (SW # 12) 71b-1 and the switch (SW #
15) 71e-1 and switch (SW # 16) 71f-1
And switch (SW # 19) 71i-1 and switch (SW # 19)
# 20) 71j-1 may be connected to either the “1” side or the “0” side.

The on-board switch control unit 82-1 switches the switch (SW # 2) 75 when connecting from the ports c and d to the port b of the on-board switch 71-1 (c, d → b).
-1 and the switch (SW # 3) 76-1 are controlled to be connected to the "1" side. The in-board switch control unit 82-1 switches the switch (SW # 12) 71b-1 to the "0" side and the "1" side in synchronization with the clock of the crossbar switch 5, and sets the switch (SW # 15) 71e- 1 is switched to the “0” side and to either the “1” side or the “0” side by a switch (SW
# 16) 71f-1 is on either the “1” side or “0” side and “0” side, and the switch (SW # 19) 71i-1 is on the “0” side, “1” side and “0” side. And the switch (SW # 20) 71j-1 is repeatedly and alternately connected to either the "1" side or the "0" side and the "0" side.

At this time, the switch (SW # 1) 74-1 and the switch (SW # 11) 71a-1 and the switch (SW #
13) 71c-1 and switch (SW # 14) 71d-1
And switch (SW # 17) 71g-1 and switch (SW # 17)
# 18) 71h-1 may be connected to either the “1” side or the “0” side.

When connected to the output side of the on-board switch 71-1, the on-board switch control section 82-1 switches the switch (SW # 2) 75-1 and the switch (SW # 3) 76
-1 is connected to the "0" side.

At this time, the switch (SW # 1) 74-1 and the switches (SW # 11 to SW # 20) 71a-1 to 71 # 1
j-1 may be connected to either the "1" side or the "0" side.

When the in-board switch control section 82-1 is connected to the input side of the in-board switch 71-1, the switch (SW # 2) 75-1 and the switch (SW # 3) 76
-1 is connected to the "1" side.

At this time, the switch (SW # 1) 74-1 and the switches (SW # 11 to SW # 20) 71a-1 to 71
j-1 may be connected to either the "1" side or the "0" side.

When the in-board switch 71-1 is connected to the output of the buffer A group 77-1, the on-board switch control section 82-1 connects the switch (SW # 1) 74-1 to the "1" side. To be controlled.

At this time, the switches (SW # 2, SW # 3)
75-1, 76-1 and switches (SW # 11 to SW # 2)
0) 71a-1 to 71j-1 may be connected to either the "1" side or the "0" side.

The in-board switch control section 82-1 connects the switch (SW # 1) 74-1 to the "0" side when the in-board switch 71-1 is connected to the output of the buffer B group 78-1. To be controlled.

At this time, the switches (SW # 2, SW # 3)
75-1, 76-1 and switches (SW # 11 to SW # 2)
0) 71a-1 to 71j-1 may be connected to either the "1" side or the "0" side.

The crossbar switch device 1 according to one embodiment of the present invention will be described with reference to FIGS. The I / O boards (# 1 to # 4) 4-1 to 4-4 are connected to respective ports of the crossbar switch 5, and use only one port of the crossbar switch 5.

On the other hand, the processor boards 2-1 and 2-2
2 and the memory boards 3-1 and 3-2 are connected to each port of the crossbar switch 5 via the crossbar switch side input / output units 6-1 to 6-4 shown in FIG. You are using

Crossbar switch side input / output units 6-1 to 6-
4 is a data part 7-1 to 7-1 in each board shown in FIGS.
7-4 and the address control units 8-1 to 8-4. Crossbar switch side input / output units 6-1 to 6
In -4, in response to a transfer request via a conventional crossbar switch, an empty port is confirmed by an identification bit, and then a response is made as to whether transfer is possible or an appropriate board is connected in response to a transfer request from a connected board. A transfer request is made to the crossbar switch-side address control unit 61-1.

Data portions 7-1 to 7-1 in each board shown in FIG.
7-4 are data distribution switches 74-1 and 75-
1, 76-1 and two systems of a buffer A group 77-1 and a buffer B group 78-1. The address control units 8-1 to 8-4 in each board shown in FIG. 4 include an in-board address control unit 81-1 and an in-board switch control unit 82-1.
Consists of

The in-board switches 71-1 of the data sections 7-1 to 7-4 are a plurality of switches 71a-1 to 71a-7 shown in FIG.
1j-1. Each of the switches 71a-1 to 71a-1 based on an instruction from the in-board switch control unit 82-1.
71j-1 is switched. The buffer A group 77-1 and the buffer B group 78-1 collect the input data to each board for each port so that the conventional board can receive the data without being aware of the data width.
It is held at 56 bit width.

As shown in FIG. 9, the in-board address control unit 81-1 of the address control units 8-1 to 8-4 includes an address line to the crossbar switch 5, an identification bit line (Sa, Sb), a, b port identification lines, a signal line to the controller 22-1 of the conventional device shown in FIG. 40, a signal line for data fetch timing to the buffer A group 77-1 and the buffer B group 78-1, and a preceding stage thereof Signal lines for fetching data into the 128-bit buffers 72-1 and 73-1 and the input buffer 23-1 of the conventional device.
And a signal line for data fetch timing.

The in-board address controller 81-1 receives the transfer request from the controller 22-1 of the conventional device, updates the identification bit, and makes a transfer request to the crossbar switch 5. The in-board address control unit 81-1 receives the transfer request from the crossbar switch 5, recognizes the width and port of the data to be transferred from the information of the identification bits, and recognizes the buffer A group 77-1 and the buffer B group. Data is fetched into the memory 78-1 and the data is transferred at an empty timing of the data input / output unit of the conventional device.

When receiving the instruction from the on-board address control section 81-1, the on-board switch control section 82-1 receives the instruction shown in FIG.
The switching instruction is issued to the necessary switches with reference to the contents shown in FIG.

Referring to FIG. 7, there is shown a configuration of an address control unit 61-1 in the crossbar switch side input / output unit 6-1 shown in FIG. 2, and the address control unit 61-1 is connected to the controller 61a-1. It comprises a memory (A) 61b-1 and a memory (B) 61c-1.

The memory (A) 61b-1 stores the configuration environment of the entire crossbar switch device 1 (see FIG. 8A), and determines whether or not there is a possibility that the corresponding communication partner is capable of 256-bit width transfer. It is a means to know. Memory (B)
Reference numeral 61c-1 stores the board name and port name of the other party currently communicating (see FIG. 8B), and refers to the address line signal when transmitting it.

Referring to FIG. 9, there is shown a detailed configuration of the on-board address control unit 81-1 shown in FIG.
1, memory (C) 81b-1, and memory (D) 81c
-1 and counters 81d-1 to 81g-1.

The memory (C) 81b-1 stores the identification bit S
It holds the value of one clock before a and Sb [see FIG. 10A], and serves as a means for the controller 81a-1 to know what the value has changed at the corresponding clock.

The memory (D) 81c-1 has a data section 7-1.
Signal contents AA1 and AA sent together with the data of buffer A group 77-1 and buffer B group 78-1 of FIG.
2, AA3, AA4, ..., AB1, AB2, AB3
AB4,..., NAA1, NAA2, NAA3, NAA4,.
B1, NAB2, NAB3, NAB4,... [See FIG. 10B].

The counters 81d-1 to 81g-1 determine how much data is stored in the buffer A group 77-1 and the buffer B group 78-1, respectively, and what data of the block is input to the data input section of the conventional device. Indicates whether or not it is provided.

This is because when a data capture clock is sent to the buffer A group 77-1 and the buffer B group 78-1,
At the same time, it outputs a count-up instruction to the corresponding counters 81d-1 and 81f-1, and simultaneously sends a countdown instruction to the counters 81d-1 and 81f-1 when sending a data fetch instruction to the buffer of the data input unit of the conventional device. Outputting a count-up instruction to each of the counters 81e-1 and 81g-1, and sending a zero reset instruction to the counters 81e-1 and 81g-1 together with an instruction to fetch the last data of the block data into the buffer of the data input unit of the conventional device. Is realized.

FIGS. 12 to 15 are flowcharts showing the operation of the crossbar switch side address control section 61-1 shown in FIGS. 2 and 7. FIGS. 16 to 23 are the in-board address control sections shown in FIGS. It is a flowchart which shows the operation | movement of the part 81-1.

The operation of the crossbar switch device 1 according to one embodiment of the present invention will be described with reference to FIGS. The operation of the above-described flowchart can be realized by each control unit executing a program of a control memory (not shown), and a ROM (read only memory) or the like can be used as the control memory.

FIGS. 12 to 15 show the operation when the processor board 2-1 directly connected to the crossbar switch-side address control section 61-1 makes a transfer request. In this case, the address control unit 61-1 on the crossbar switch side is the address control unit 8-1 of the processor board 2-1.
When a transfer request is received from the in-board address control unit 81-1 via an address line (step S1 in FIG. 12), if the connected processor board 2-1 is a 256-bit board (step S2 in FIG. 12), With reference to the identification bit, the vacancy status of the port of the own circuit is confirmed (step S3 in FIG. 12).

If 256 bits can be secured for the port of the crossbar switch 5, that is, the input / output section 6 on the crossbar switch side
If two ports of the crossbar switch 5 to which the -1 is connected can be secured (step S4 in FIG. 12), the crossbar switch side address control unit 61-1 stores the memory (A) 61b-1.
And confirms the maximum data width of the communication partner (see FIG. 12).
Step S5).

The crossbar switch side address controller 61-
If the maximum data width of the communication partner is 256 bits (step S6 in FIG. 12), ports a and b of the communication partner
Are transmitted to the two address lines corresponding to (1) in FIG.
In step S7, if it is 128 bits, a transfer request is sent to the address line (one) corresponding to the port of the communication partner (step S12 in FIG. 12).

The address control section 61-on the crossbar switch side
When the transfer OK is returned from both of the two address lines (step S8 in FIG. 12), 1 relays the signal to the in-board address control unit 81-1 of the processor board 2-1. Thereafter, the crossbar switch-side address control unit 61-1 relays the signal on the same route until the transfer is completed (step S9 in FIG. 12).

On the other hand, if there is a transfer OK from only one address line (step S18 in FIG. 14), the crossbar switch-side address control unit 61-1 responds to one of the ports by a predetermined method. Set the identification bit to “0”
(Step S19 in FIG. 14).

The crossbar switch side address control unit 61-
1 is the transfer OK after securing the route on the identification bit side of "1".
The signal is relayed to the in-board address control section 81-1 of the processor board 2-1 (step S20 in FIG. 14).

In this case, the crossbar switch-side address control section 61-1 records the route and the destination information secured in the memory (B) 61c-1 (step S20 in FIG. 14), and thereafter, the in-board address control section 81 -1 is checked with reference to the route recorded in the memory (B) 61c-1 and the destination information, and if the signal is from the same communication partner, the relay of the signal is continued until the transfer is completed (FIG. 14 step S21). When the transfer is completed, the crossbar switch side address control unit 61-1 simultaneously stores the data in the memory (B) 61-1.
The route information of c-1 is deleted (step S2 in FIG. 14).
2).

The crossbar switch side address controller 61-
When the transfer failure is returned from both address lines (step S23 in FIG. 14), 1 relays the signal to the in-board address control unit 81-1 of the processor board 2-1 (step S24 in FIG. 14).

On the other hand, if the port of the processor board 2-1 can secure only a 128-bit width, the crossbar switch-side address control section 61-1 (step S1 in FIG. 12).
0), a single address line of the other party is selected by a predetermined method and a transfer request is sent (step S11 in FIG. 12).

The crossbar switch side address controller 61-
When the transfer OK is returned in response to the transfer request (step S18 in FIG. 14), a path is secured in the same manner as described above (step S20 in FIG. 14), and the in-board address control unit 81 of the processor board 2-1. The transfer OK is relayed to -1 (step S21 in FIG. 14).

Also in this case, the crossbar switch side address control section 61-1 records the route and the destination information secured in the memory (B) 61c-1 (step S20 in FIG. 14).
Thereafter, the signal from the in-board address control unit 81-1 is checked with reference to the path recorded in the memory (B) 61c-1 and the other party information. The relay of the signal is continued (step S21 in FIG. 14). When the transfer is completed, the crossbar switch side address control unit 61-1 simultaneously stores the data in the memory (B) 61-1.
The route information of c-1 is deleted (step S2 in FIG. 14).
2).

The crossbar switch side address control unit 61-
1 also indicates that transfer is impossible (step S in FIG. 14).
23), the signal is transferred to the same in-board address control unit 81-
1 (step S24 in FIG. 14).

When the port of the processor board 2-1 is 256
If it is not a bit (step S2 in FIG. 12), the crossbar switch side address control unit 61-1 stores the memory (A) 61b
-1 and relays the transfer request signal to the address line corresponding to the data width of the communication partner (step S1 in FIG. 13).
3).

The crossbar switch side address control unit 61-
When the transfer OK is returned in response to the transfer request (step S14 in FIG. 13), the transfer OK is transmitted to the in-board address control unit 81-1 of the processor board 2-1 in the same manner as described above.
Relay. Thereafter, the crossbar switch-side address control unit 61-1 continues to relay the signal until the transfer is completed (FIG. 1).
3 steps S15).

Crossbar switch side address control section 61-
1 also indicates that transfer failure has been returned (step S in FIG. 13).
16), the signal is transferred to the same in-board address control unit 81-
1 (step S17 in FIG. 13).

FIG. 15 shows the operation when the crossbar switch-side address control section 61-1 receives a transfer request from the crossbar switch 5 side. In this case, upon receiving the transfer request from the crossbar switch 5 (step S31 in FIG. 15), the crossbar switch-side address control unit 61-1 refers to the identification bit and checks the vacancy of the port of the own circuit (step S31 in FIG. 15). S32).

The crossbar switch side address controller 61-
1 indicates that if the connected processor board 2-1 is a 256-bit board (step S33 in FIG. 15), it is determined whether or not the transfer request comes from two address lines (FIG. 1).
5 steps S34).

The crossbar switch side address controller 61-
If the transfer request comes from two address lines, 1 checks whether a port for the transfer request can be secured (step S35 in FIG. 15). Crossbar switch side address controller 6
1-1, if the port of the transfer request can be secured, the identification bits Sa and Sb are both changed to "1" to secure the port (step S36 in FIG. 15), and the address line corresponding to the secured identification bit is set. A transfer OK is returned via (step S37 in FIG. 15).

The crossbar switch side address control section 61-
No. 1 transfers the transfer request to the on-board address control unit 81-1 (step S38 in FIG. 15), and the memory (B) 61c-1
, The transfer path and the partner information are stored. Thereafter, the signal from the corresponding address line refers to the contents of the memory (B) 61c-1.
If the signal is from the corresponding port, it is relayed to the in-board address control unit 81-1 (step S39 in FIG. 15).

At this time, the in-board address control section 81-
1 is an address signal from the data transfer destination of the a port when the 1-bit a / b port identification line is “0”, and is “1”.
At the time, the address signal is identified as an address signal from the data transfer destination of the port b.

After the transfer is completed, the crossbar switch-side address control section 61-1 clears the contents of the memory (B) 61c-1, and returns the identification bit changed to "1" (FIG. 15).
Step S40).

The crossbar switch side address controller 61-
1 indicates that the connected processor board 2-1 is a 128-bit board (step S33 in FIG. 15), and if the corresponding port is vacant (step S41 in FIG. 15), the transfer request is relayed as it is, and the vacant state of the conventional device Is relayed and returned (step S42 in FIG. 15). Thereafter, the crossbar switch-side address control section 61-1 performs the same operation as described above (steps S38 to S40 in FIG. 15).

The crossbar switch side address control section 61-
1 indicates that the corresponding port is not empty (step S41 in FIG. 15), or if the port is not empty when the transfer request does not come from two address lines (steps S34 and S43 in FIG. 15), or the port of the transfer request is If the transfer cannot be secured (step S44 in FIG. 15), the transfer failure is returned on the route for which the transfer was requested (step S47 in FIG. 15).

The crossbar switch side address controller 61-
If the transfer request port can be secured when the transfer request does not come from two address lines (step S43 in FIG. 15),
Or, when the transfer request comes from two address lines,
If one transfer request port can be secured (step S44 in FIG. 15), the identification bit corresponding to the empty port is changed to “1” (step S45 in FIG. 15).

The crossbar switch side address control unit 61-
1 returns transfer OK using the address line corresponding to the secured port (step S46 in FIG. 15), and thereafter performs the same operation as described above (steps S38 to S4 in FIG. 15).
0).

FIGS. 16 to 23 show the operation of the in-board address control section 81-1 (not mounted on the 128-bit board) of the address controller section 8-1 of the processor board 2-. In this case, the in-board address control unit 81-1 is directly connected to the controller 22 of the conventional device.
-1 (see FIG. 40) (step S51 in FIG. 16), the data section 7 of the processor board 2-1 receives the transfer request.
It is confirmed that the ports c and d of the in-board switch 71-1 of -1 are not used, and the transfer request is relayed as it is (step S52 in FIG. 16). If it has been used, transfer failure is returned to the controller 22-1.

Thereafter, the in-board address control section 81-1
Receives the transfer OK notification from the transfer destination and confirms the identification bit (steps S61 and S62 in FIG. 17), and if a 256-bit band can be secured, that is, if Sa = 1 and Sb = 1 (step S63 in FIG. 17) ), A route to the switch control unit 82-1 in the board so that data can be directly sent to the switch, that is, a route of c → a, d → b and a switch (SW).
(# 2, # 3) An instruction is given to change 75-1 and 76-1 to the transmission side routes (step S64 in FIG. 17).

Thereafter, the in-board address control section 81-1
Transmits the clock of the crossbar switch 5 to the output buffer 24-1 (see FIG. 40) of the conventional device, and enables new data to be transmitted to the crossbar switch 5 every clock (step S65 in FIG. 17).

The in-board address control section 81-1 relays the address line signal from the controller 22-1 as it is until the transfer is completed (step S66 in FIG. 17), and confirms that the transfer completion signal has been sent from the controller 22-1. At the beginning, the identification bits Sa and Sb are returned to "0" (step S67 in FIG. 17).

The on-board address control section 81-1 has 128 addresses.
If only the band can be secured, that is, if the identification bits are Sa = 1 and Sb = 0 (FIG. 17, step S6)
8) Or, if the identification bits are Sa = 0 and Sb = 1 (step S74 in FIG. 18), a mode in which the path is switched for each clock to the in-board switch controller 82-1 so that data can be sent in order from c and d. Instruct to work with.

When the identification bits are Sa = 1 and Sb = 0,
The in-board address control unit 81-1 provides the in-board switch control unit 82-1 with securing the c → a path and performing the switch (SW #
2, # 3) to instruct 75-1 and 76-1 to change to the sending side (step S69 in FIG. 17).

Thereafter, the in-board address control unit 81-1 sets the path of c → a and d for each clock of the crossbar switch 5.
→ It instructs the in-board switch controller 82-1 to switch to the path a (step S70 in FIG. 17). The in-board address control unit 81-1 is the output buffer 2 of the conventional device.
In 4-1, the clock of the crossbar switch 5 is transmitted once every two times, and new data can be transmitted to the crossbar switch 5 once every two clocks (step S71 in FIG. 17).

The in-board address control section 81-1 relays the address line signal from the controller 22-1 as it is until the transfer is completed (step S72 in FIG. 17), and confirms that the transfer completion signal has been sent from the controller 22-1. The identification bit Sa is reset to “0” as a trigger (step S7 in FIG. 17).
3).

When the identification bits are Sa = 0 and Sb = 1,
The in-board address control section 81-1 provides the in-board switch control section 82-1 with securing the c → b path and the switch (SW #
(2, # 3) Instruct to change 75-1 and 76-1 to the sending side (step S75 in FIG. 18).

Thereafter, the in-board address control section 81-1 sets the path of c → b and d for each clock of the crossbar switch 5.
→ The in-board switch controller 82-1 is instructed to switch to the route b (step S76 in FIG. 18). The in-board address control unit 81-1 is the output buffer 2 of the conventional device.
At 4-1 the clock of the crossbar switch 5 is transmitted once every two times, and new data can be sent out to the crossbar switch 5 once every two clocks (step S77 in FIG. 18).

The in-board switch control section 82-1 relays the address line signal from the controller 22-1 as it is until the transfer is completed (step S78 in FIG. 18), and confirms that the transfer completion signal has been sent from the controller 22-1. The identification bit Sb is reset to “0” as a trigger (FIG. 18, step S7).
9).

If the above-mentioned band cannot be ensured, the in-board address control section 81-1 sends the signal to the controller 22 of the conventional device.
-1 is relayed to indicate that transfer is impossible, and the retransmission is left to the conventional device (step S80 in FIG. 18).

FIGS. 19 to 23 show the operation when the in-board address control unit 81-1 receives a transfer request from the controller 22-1 of the conventional device via the crossbar switch 5. FIG. In this case, the in-board address control unit 81-
1 refers to the memory (C) 81b-1 and checks the identification bit that has changed to “1” as compared to one clock before (steps S91 and S92 in FIG. 19) and recognizes the port to which the data is sent.

The in-board address control section 81-1 selects a usable buffer A group 77-1 or a usable buffer B group 78-1 which can be determined from this information and the confirmation of the path in use, and determines an appropriate path. It instructs the internal switch control unit 82-1.

At this time, when data is transmitted in units of 128 bits, clocks are alternately transmitted to the preceding buffers 72-1 and 73-1 and the buffer A group 77-1 or the buffer B group 78-1. The data is stored in the buffer A group 77-1 or the buffer B group 78-1 while being aligned with 256-bit data.

In parallel with this, on the other hand, the controller 2 to which the in-board address control section 81-1 is directly connected is connected.
A transfer request is sent to allow 2-1 to receive the data. If the data cannot be received because the controller 22-1 is transferring data from the other buffer group, the transfer request is repeated.

When transfer OK is returned, the in-board address control section 81-1 switches to the corresponding buffer side (SW #
1) The 74-1 is switched, and at the same time, clock transmission to the input buffer 23-1 (see FIG. 40) of the conventional device is started, and the data in the buffer is taken in. However, this clock is sent only when there is 256-bit data in the buffer while referring to the counters 81d-1 to 81g-1.

The operation of transmitting a control signal from the in-board address control section 81-1 to the buffer when data is stored in the buffer of the data section 7-1 will be described below. When data is being transferred with a transfer partner in a 256-bit width, the in-board address control unit 81-1 communicates with the corresponding buffer group and the preceding 12 bits.
The data capture signal is sent to the 8-bit buffer in synchronization with the clock on the crossbar switch 5 side. At the same time, the counter 81d-1 or the counter 81e-1 of the in-board address controller 81-1 is counted up.

Similarly, when data is received in 128 bits, the in-board address control section 81-1 sends a fetch instruction to the corresponding preceding buffer at the timing of the lower 128 bits received first, and the crossbar switch 5 side At the next clock timing, a signal is sent to the corresponding buffer group to depress the old data, and the new upper 128 bits that are directly seen via the on-board switch 71-1 and the lower 128 bits of the previous buffer are added together. Import as important data. At the same time, the corresponding one of the counter 81d-1 or the counter 81e-1 of the in-board address control unit 81-1 is counted up.

Data transfer from the buffer of the data unit 7-1 to the data input unit of the conventional device directly connected is performed by transferring the data from the controller 22-1 to the corresponding data block.
On-board address control unit 81-
Performed after 1 is received.

This data transfer is performed by the counters 81d-1 to 81d-8.
Referring to 1g-1, if 256-bit data is stored in the buffer group, a predetermined normal clock signal is sent to the clock line of the buffer of the data input unit of the conventional device. If there is no 256-bit data in the buffer group, the transmission of the clock signal is forgotten.

That is, the in-board address control unit 81-
1 indicates that data is transferred with a transfer partner in a 256-bit width, that is, the identification bits are Sa = 0 → 1, Sb = 0 → 1
(Step S93 in FIG. 19), the in-board switch control unit 82-1 secures the a → c, b → d paths and switches (SW # 2, # 3) 75-1, 76-1. An instruction to change to the transmission side route is issued (step S9 in FIG. 19).
4).

If the transfer request to the controller 22-1 of the conventional device is OK (step S95 in FIG. 19), the in-board address control unit 81-1 switches the in-board switch control unit 8-1.
2-1 to switch the switch (SW # 1) 74-1 to the buffer A group 77-1 (step S9 in FIG. 19).
6). If the transfer request to the controller 22-1 of the conventional device is NG (in FIG.
Nine steps S95), the address line transfer request is stored in the address buffer for the buffer A group 77-1 of the memory (D) 81c-1 (FIG. 19, step S99).

The in-board address control section 81-1 records the recording NAAn (n = 1, 2, 3, 3) of the memory (D) 81c-1.
4,...) And the clock signal, and address information A
An is relayed to the controller 22-1 of the conventional device at the same time as the corresponding data, and the operation clock of the crossbar switch 5 is transmitted to the input buffer 23-1 of the conventional device as it is (step S97 in FIG. 19). The in-board address control unit 81-1 resets the identification bits Sa and Sb to “0” when the transfer completion signal is sent from the controller 22-1 (step S98 in FIG. 19).

The in-board address control section 81-1 transfers data with the transfer partner in a 128-bit width, that is, when the identification bit changes from Sa = 0 to 1 (step S100 in FIG. 20). Then, the connection route of the port b is confirmed (step S101 in FIG. 20).

If the port b is connected to the buffer A group 77-1 (FIG. 20)
Step S102), in-board switch control section 82-1
Is instructed to change the route to a, e, and f (see FIG. 2).
0 step S103).

If the transfer request to the controller 22-1 of the conventional device is OK (step S104 in FIG. 20), the in-board address control section 81-1 switches the in-board switch control section 82-1 to the switch (SW # 1). 74-1 to buffer B
Instruct to switch to group 78-1 (step S in FIG. 20)
105). If the transfer request to the controller 22-1 of the conventional device is NG (step S104 in FIG. 20), the in-board address control unit 81-1 sends the transfer request of the address line to the buffer B group 78 of the memory (D) 81c-1. -1 is stored in the address buffer (step S10 in FIG. 20).
9).

If there is 256-bit width data in the buffer B group 78-1 (step S106 in FIG. 20), the in-board address control section 81-1 records the recording NABn (n = 1, 2) of the memory (D) 81c-1. , 3, 4,...) And the clock signal, the address information ABn is relayed to the controller 22-1 of the conventional device at the same time as the corresponding data, and the operation clock of the crossbar switch 5 is directly input to the conventional device every time. The data is transmitted to the buffer 23-1 (step S107 in FIG. 20). The in-board address controller 81-1 returns the identification bit Sa to "0" upon receiving the transfer completion signal from the controller 22-1 (step S108 in FIG. 20).

If the port b is not connected to the buffer A group 77-1 (step S102 in FIG. 20), the in-board address control unit 81-1 switches the in-board switch control unit 82-1.
-1 to secure a → c, d paths and switch (SW # 2, #SW)
3) An instruction is given to change 75-1 and 76-1 to the transmission side path (step S119 in FIG. 22).

If the transfer request to the controller 22-1 of the conventional device is OK (step S120 in FIG. 22), the in-board address control section 81-1 sends a switch (SW # 1) to the in-board switch control section 82-1. 74-1 buffer A
An instruction to switch to group 77-1 (step S in FIG. 22)
121). If the transfer request to the controller 22-1 of the conventional device is NG (step S120 in FIG. 22), the in-board address control unit 81-1 sends the address line transfer request to the buffer A group 77 of the memory (D) 81c-1. -1 is stored in the address buffer (step S12 in FIG. 22).
5).

If the buffer A group 77-1 has 256-bit width data (step S122 in FIG. 22), the in-board address control section 81-1 records the recording NAAn (n = 1, 2) of the memory (D) 81c-1. , 3, 4,...) And the clock signal, the address information AAn is relayed to the controller 22-1 of the conventional device at the same time as the corresponding data, and the operation clock of the crossbar switch 5 is input to the input of the conventional device every time. The data is transmitted to the buffer 23-1 (step S123 in FIG. 22). The in-board address control section 81-1 returns the identification bit Sa to "0" upon receiving the transfer completion signal from the controller 22-1 (step S124 in FIG. 22).

The in-board address control unit 81-1 transfers data with the transfer partner in a 128-bit width, that is, when the identification bit changes from Sb = 0 to 1 (FIG. 2).
1 step S110), the port a is set to the buffer A group 77-
1 (step S111 in FIG. 21), the in-board switch controller 82-1 is instructed to change to secure the a → e, f path (step S112 in FIG. 21).

If the transfer request to the controller 22-1 of the conventional device is OK (step S113 in FIG. 21), the on-board address control section 81-1 sends a switch (SW # 1) to the on-board switch control section 82-1. 74-1 to buffer B
Instruct to switch to group 78-1 (step S in FIG. 21)
114). If the transfer request to the controller 22-1 of the conventional device is NG (step S113 in FIG. 21), the in-board address control unit 81-1 sends the address line transfer request to the buffer B group 78 of the memory (D) 81c-1. -1 is stored in the address buffer (step S11 in FIG. 21).
8).

If there is 256-bit width data in the buffer B group 78-1 (step S115 in FIG. 21), the in-board address control section 81-1 records the recording NABn (n = 1, 2) of the memory (D) 81c-1. , 3, 4,...) And the clock signal, the address information ABn is relayed to the controller 22-1 of the conventional device at the same time as the corresponding data, and the operation clock of the crossbar switch 5 is input to the input of the conventional device every time. The data is transmitted to the buffer 23-1 (step S116 in FIG. 21). The in-board address control section 81-1 returns the identification bit Sb to "0" upon receiving the transfer completion signal from the controller 22-1 (step S117 in FIG. 21).

If the port a is not connected to the buffer A group 77-1 (FIG. 21, step S111), the on-board address control section 81-1 switches on the on-board switch control section 82-1.
-1 to secure a → c, d paths and switch (SW # 2, #SW)
3) Instruct to change 75-1 and 76-1 to the transmission side route (step S126 in FIG. 23).

If the transfer request to the controller 22-1 of the conventional device is OK (step S127 in FIG. 23), the on-board address control section 81-1 sends a switch (SW # 1) to the on-board switch control section 82-1. 74-1 buffer A
An instruction to switch to the group 77-1 (step S in FIG. 23)
128). If the transfer request to the controller 22-1 of the conventional device is NG (step S127 in FIG. 23), the in-board address control unit 81-1 sends the transfer request of the address line to the buffer A group 77 of the memory (D) 81c-1. -1 is stored in the address buffer (step S13 in FIG. 23).
2).

If there is 256-bit width data in the buffer A group 77-1 (step S129 in FIG. 23), the in-board address control section 81-1 records the recording NAAn (n = 1, 2) in the memory (D) 81c-1. , 3, 4,...) And the clock signal, the address information AAn is relayed to the controller 22-1 of the conventional device at the same time as the corresponding data, and the operation clock of the crossbar switch 5 is input to the input of the conventional device every time. The data is transmitted to the buffer 23-1 (step S130 in FIG. 23). The in-board address control unit 81-1 returns the identification bit Sb to “0” when the transfer completion signal is sent from the controller 22-1 (step S131 in FIG. 23).

FIG. 24 is a diagram showing a case of data transfer in the crossbar switch device 1 according to one embodiment of the present invention. In the figure, C1 represents 256-bit data as 2
C2 indicates a case where a 256-bit band can be secured when transferring to a 56-bit port, C2 indicates a case where a 128-bit band can be secured when transferring 256-bit data to a 256-bit port, and C3 indicates a case where a 256-bit band can be secured. This shows a case where a band cannot be secured when transferring data to a 256-bit port.

C4 indicates a case where a 128-bit band can be secured when transferring 128-bit data to a 256-bit port, and C5 indicates a case where a band cannot be secured when transferring 128-bit data to a 256-bit port. Is shown.

C6 indicates a case where a 128-bit bandwidth can be secured when transferring 256-bit data to a 128-bit port, and C7 indicates a case where a bandwidth cannot be secured when transferring 256-bit data to a 128-bit port. Is shown.

C8 indicates a case where a 128-bit band can be secured when transferring 128-bit data to a 128-bit port, and C9 indicates a case where a band cannot be secured when transferring 128-bit data to a 128-bit port. Is shown.

FIG. 25 shows a case where 256-bit data is transferred to a 256-bit port according to an embodiment of the present invention.
FIG. 26 is a diagram illustrating the operation on the request side when a 6-bit band can be secured (in the case of C1). FIG. 26 illustrates a case where a 256-bit band is transferred to a 256-bit port according to an embodiment of the present invention. It is a figure which shows operation | movement of the supply side when it can secure (C1).

FIG. 27 shows a case where 256-bit data is transferred to a 256-bit port according to an embodiment of the present invention.
FIG. 28 is a diagram showing the operation on the request side when an 8-bit band can be secured (in the case of C2). FIG. 28 shows a case where a 128-bit band is transferred to a 256-bit port according to an embodiment of the present invention. It is a figure which shows operation | movement of the supply side when it can secure (C2).

FIG. 29 is a diagram showing the operation on the request side when a band cannot be secured (in the case of C3) when transferring 256-bit data to a 256-bit port according to an embodiment of the present invention. FIG. 11 is a diagram illustrating an operation on the supply side when a band cannot be secured (in the case of C3) when transferring 256-bit data to a 256-bit port according to an embodiment of the present invention.

FIG. 31 shows a case where 128-bit data is transferred to a 256-bit port according to an embodiment of the present invention.
FIG. 32 is a diagram showing the operation on the request side when an 8-bit band can be secured (C4). FIG. 32 shows a case where a 128-bit band is transferred to a 256-bit port according to an embodiment of the present invention. It is a figure which shows operation | movement of the supply side when it can secure (C4).

FIG. 33 is a diagram showing an operation on the request side when a band cannot be secured (in the case of C5) when transferring 128-bit data to a 256-bit port according to an embodiment of the present invention. FIG. 8 is a diagram illustrating an operation on the supply side when a band cannot be secured (in the case of C5) when transferring 128-bit data to a 256-bit port according to an embodiment of the present invention.

FIG. 35 shows a case where 256-bit data is transferred to a 128-bit port according to an embodiment of the present invention.
FIG. 36 is a diagram showing the operation on the requesting side when an 8-bit band can be secured (C6). FIG. 36 shows a case where the 128-bit band is transferred to the 128-bit port according to an embodiment of the present invention. It is a figure which shows operation | movement of the supply side when it can secure (C6).

FIG. 37 is a diagram showing an operation on the request side when a band cannot be secured (in the case of C7) when transferring 256-bit data to a 128-bit port according to an embodiment of the present invention. FIG. 11 is a diagram illustrating an operation on the supply side when a band cannot be secured (in the case of C7) when transferring 256-bit data to a 128-bit port according to an embodiment of the present invention.

Data transfer using the crossbar switch device 1 according to one embodiment of the present invention will be described with reference to FIGS. 1 to 11 and FIGS. In the case of C8 and C9 shown in FIG. 24, the environment is the same as that of the conventional apparatus.

First, when a 256-bit band can be secured when transferring 256-bit data to a 256-bit port (in the case of C1), the requesting side identifies the identification bits Sa and Sb.
Are both "0", the controller 22-1 of the conventional device
When there is a transfer request from the server (process C1-1), the in-board address control unit 81-1 sets the identification bits Sa and Sb to both "1" and sends the transfer request (Sa = 0 → 1, Sb).
= 0 → 1) (Process C1-2). Here, on the supply side, the identification bits Sa and Sb are both "0" at the time of processes C-1 and C-2.

Thereafter, when the identification bits Sa and Sb both become "1", the request side crossbar switch side address control section 61-1 sends a transfer request to the two address lines of the communication partner. The supply-side crossbar switch-side address controller 61-1 detects a transfer request of two address lines. At this time, the identification bits Sa and Sb are "1" on the request side,
It is "0" on the supply side (process C1-3).

Since the identification bits Sa and Sb are both "0", the supply-side crossbar switch-side address control unit 61-1 replies "transfer OK" to both of the two address lines.
At the same time, the identification bits Sa and Sb are both set to “1” (Sa = 0 →
1, Sb = 0 → 1) and sends a transfer request to the board. Thereafter, the in-board address control unit 81-1 on the supply side
Instructs the in-board switch control unit 82-1 to set a path of a → c, b → d (process C1-4).

In-board address control section 81-1 on the supply side
Transmits a transfer request to the controller 22-1 of the conventional device. The request-side crossbar switch-side address control unit 61-
When 1 confirms the transfer OK from both of the two address lines, it keeps both the identification bits Sa and Sb at "1" and transmits the transfer OK to the board (process C1-5).

Request-side in-board switch control section 82-1
Instructs the in-board switch control unit 82-1 to set a path of a → c, b → d, and switches (SW # 2, SW # 3) 7
5-1 and 76-1 are set to the sending side (process C
1-6).

Request-side in-board switch controller 82-1
Sends the data when the specified setting is made. The in-board switch controller 82-1 on the supply side receives the transmitted data by the buffer A group 77-1 (process C1-7).

In-board address control section 81-1 on the supply side
Confirms from the buffer group that there is no data being fetched by the data input unit of the conventional device, or confirms the completion of the fetch (process C1-8).

In-board address control section 81-1 on the supply side
Sends the address to the controller of the conventional device after confirmation. The crossbar switch-side address control unit 61-1 instructs the switch (SW # 1) 74-1 to be set in the buffer A group 77-1 (process C1-9).

Request-side in-board address control section 81-1
Returns the identification bits Sa and Sb to “0” after the transmission is completed (Sa = 1 → 0, Sb = 1 → 0), and the in-board address control unit 81-1 on the supply side sets the identification bits Sa and Sb after the transfer is completed.
Return Sb to “0” (Sa = 1 → 0, Sb = 1 → 0)
(Process C1-10) (see FIGS. 25 and 26).

When a 128-bit band can be secured when transferring 256-bit data to a 256-bit port (in the case of C2), the above processing C is performed on both the requesting side and the supplying side.
Perform 1-1 to C1-3.

Thereafter, the supply-side crossbar switch-side address control unit 61-1 recognizes that the port a or the port b is in use by referring to the identification bits Sa and Sb, and transfers it to the vacant address line. OK is returned, and at the same time, the corresponding identification bits Sa and Sb are set to "1" (Sa = 0 → 1 or Sb = 0 → 1), and a transfer request is sent to the board (process C2-1).

In-board address control section 81-1 on the supply side
Instructs the in-board switch control unit 82-1 to secure a path from the secured port to a buffer group that can be secured. The request-side crossbar switch-side address control unit 61-
When 1 confirms transfer OK from one of the two address lines, 1 sets the identification bits Sa and Sb to which transfer OK has not been received to “0” (1, 1 → 0 or 1 → 0, 1) and transfers to the board. OK is transmitted (process C2-2).

Request-side in-board address controller 81-1
Transmits the transfer OK to the controller 22-1 of the conventional device, and sends the switch (SW) to the in-board switch controller 82-1.
# 2, SW # 3) Instruct the 75-1 and 76-1 to be the sending side (process C2-3).

In-board switch control section 82-1 on request side
Is c → a or in the on-board switch controller 82-1
b, d → a or b path setting is instructed, and new data is requested to the output unit of the conventional device once every two clocks. The in-board address control unit 81-1 on the supply side transmits a transfer request to the controller 22-1 of the conventional device, and the in-board switch control unit 82-1 switches each clock (SW # 11).
The switch 71a-1 or the switch (SW # 12) 71b-1 is switched to secure a path for sequentially transmitting data to the upper and lower bits of the buffer group (process C2-4).

Request-side in-board switch control section 82-1
Sends the data when the specified setting is made. The in-board switch control section 82-1 on the supply side sends the transmitted data to the buffer A group 77-1 or the buffer B group 78-1.
(Process C2-5). Thereafter, the above processes C1-8 to C1-10 are performed on both the requesting side and the supplying side (see FIGS. 27 and 28).

If the bandwidth cannot be secured when transferring 256-bit data to the 256-bit port (C3), the above processing C1-1 to C1-1 is performed on both the requesting side and the supplying side.
Perform 1-3.

Thereafter, the supply-side crossbar switch-side address control unit 61-1 recognizes that the ports a and b are in use by referring to the identification bits Sa and Sb, and replies a band securing impossible signal (processing). C3-1).

The crossbar switch-side address control section 61-1 on the request side transmits the band securing impossible signal to the board as it is, and sets both the identification bits Sa and Sb to "0" (Sa).
= 1 → 0, Sb = 1 → 0) (process C3-2).

Request-side in-board address control section 81-1
Transmits the band securing impossible signal as it is to the controller 22-1 of the conventional device (process C3-3). Thereafter, it is left to the retransmission request of the controller 22-1 of the conventional device. If the receiving side has triggered the retransmission in the conventional apparatus, the request can be made to the controller 22-1 of the conventional apparatus on the receiving side, and the system can be used as it is (see FIGS. 29 and 30).

When a 128-bit band can be secured when transferring 128-bit data to a 256-bit port (in the case of C4), the crossbar switch-side address control unit 61-1 on the requesting side transmits from the only address line to the receiving side on the receiving side. A transfer request is sent to one of the two address lines. The crossbar switch-side address control unit 61-1 on the supply side detects a transfer request for one of the two address lines (Process C
4-1).

The supply-side crossbar switch-side address control section 61-1 confirms that at least one of the ports a and b is free by checking the identification bits Sa and Sb, and checks the address line of one of the free ports. The identification bit on the side responding the transfer OK is set to "1" (process C4-2).

Upon confirming the transfer OK from one of the two address lines, the request-side crossbar switch-side address control unit 61-1 transmits the transfer OK to the board, and thereafter changes the data destination to the port to which the reply has been made. . The in-board address controller 81-1 transmits the transfer OK as it is to the controller 22-1 of the conventional device (process C4-3).

Thereafter, on the supply side, the above processes C2-2 to C2-2
Perform C2-5, C1-8 to 1-10. After the process C4-3 is performed on the request side, the signal and data from the controller 22-1 of the conventional device are output as they are (see FIGS. 31 and 32).

If the bandwidth cannot be secured when transferring 128-bit data to the 256-bit port (C5), the requesting crossbar switch-side address control unit 61
-1 sends a transfer request from only one address line to any address line on the receiving side. The supply-side crossbar switch-side address control unit 61-1 detects a transfer request of one of the two address lines (process C5-1).

The supply-side crossbar switch-side address control unit 61-1 recognizes that the ports a and b are in use by referring to the identification bits Sa and Sb, and returns a band securing impossible signal (process C5-2). ).

The request-side crossbar switch-side address control section 61-1 transmits the band securing impossible signal to the board as it is (process C5-3). Thereafter, it is left to the retransmission request of the controller 22-1 of the conventional device. If the receiving side has triggered the retransmission in the conventional device, the request can be made to the controller 22-1 of the conventional device on the receiving side, and the system can be used as it is (see FIGS. 33 and 34).

When a 128-bit band can be secured when transferring 256-bit data to a 128-bit port (C6), the request-side crossbar switch-side address control unit 61-1 connects to one of the two address lines. Send a transfer request. The supply-side crossbar switch-side address control unit 61-1 detects a transfer request from the address line (process C6-1).

The supply-side crossbar switch-side address control section 61-1 transfers the data to the address line at the sender port.
Reply K. When the request-side crossbar switch-side address control unit 61-1 confirms the transfer OK from the address line,
The transfer OK is transmitted to the board (process C6-2).

Thereafter, on the request side, the above processes C2-3 to C2-3
Perform C2-5, C1-8 to 1-10. After the process C6-2 is performed on the supply side, the signal and data are directly input to the controller 22-1 of the conventional device as it is (see FIGS. 35 and 36).

If the bandwidth cannot be secured when transferring 256-bit data to the 128-bit port (C7), the requesting crossbar switch-side address control unit 61
-1 sends a transfer request from one of the two address lines. Supply-side crossbar switch-side address controller 61
-1 detects a transfer request from the address line (process C7-
1).

The supply-side crossbar switch-side address control section 61-1 returns a band securing impossible signal to the address line having the sender port. When the request-side crossbar switch-side address control unit 61-1 confirms the band securing impossible signal from the address line, it transmits the band securing impossible signal to the board (process C7-2).

Thereafter, the retransmission request is sent to the controller 22-1 of the conventional device. If the receiving side has triggered the retransmission in the conventional apparatus, the request can be made to the controller 22-1 of the conventional apparatus on the receiving side, and the system can be used as it is (see FIGS. 37 and 38).

As described above, since a board capable of receiving wide data has two input buffers and a switch and a controller for distributing data to the two buffers, it is possible to simultaneously transfer two boards having different data widths. it can.

Further, since a switch and a controller for distributing data are provided at the end of an output buffer of a board capable of transmitting wide data, a port corresponding to half the data width even during data transfer is provided. If is not used, another data transfer can be performed.

Further, since one address line, two bits of identification bits, and one bit of a and b port identification lines are used instead of providing two sets of address lines, the physical size of the connection portion is used. Can be reduced and realized inexpensively.

Furthermore, since both data lines and address lines are shared without depending on the bus width of the communication partner, it can be realized at a lower cost than providing a plurality of ports corresponding to the data width of the communication partner. it can.

[0195]

As described above, according to the present invention, a plurality of boards each have a plurality of ports of the same data width to which a plurality of boards are connected, and a plurality of boards are connected via a plurality of ports sharing an address signal. In the variable data width crossbar switch device, when the data width between the communicating boards is different, communication with another board via an available port among the ports to which the board with the wider data width is connected Is performed, a port connected to the crossbar switch having a wide data width has an effect that communication can be performed irrespective of the data width of a destination port even during communication with a port having a small data width.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a crossbar switch device according to one embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a crossbar switch-side input / output unit in FIG. 1;

FIG. 3 is a block diagram illustrating a configuration of a data unit in FIG. 1;

FIG. 4 is a block diagram illustrating a configuration of an address control unit in FIG. 1;

FIG. 5 is a block diagram showing a configuration of an in-board switch of FIG. 3;

FIGS. 6A and 6B are diagrams showing the configuration of the switch shown in FIGS. 3 and 5. FIG.

FIG. 7 is a block diagram illustrating a configuration of a crossbar switch-side address control unit illustrated in FIG. 2;

8A is a diagram showing the contents stored in a memory (A) in FIG. 7, and FIG. 8B is a diagram showing the contents stored in a memory (B) in FIG.

FIG. 9 is a block diagram showing a configuration of an in-board address control unit of FIG. 4;

10A is a diagram showing the storage contents of a memory (C) in FIG. 9, and FIG. 10B is a diagram showing the storage contents of a memory (D) in FIG.

11 is a diagram showing control of the switches of FIGS. 3 and 5 by the in-board switch control unit of FIG. 4;

FIG. 12 is a flowchart showing an operation of the crossbar switch-side address control unit shown in FIGS. 2 and 7;

FIG. 13 is a flowchart showing an operation of the crossbar switch-side address control unit shown in FIGS. 2 and 7;

FIG. 14 is a flowchart showing the operation of the crossbar switch-side address control unit shown in FIGS. 2 and 7;

FIG. 15 is a flowchart illustrating an operation of the crossbar switch-side address control unit illustrated in FIGS. 2 and 7;

FIG. 16 is a flowchart showing the operation of the in-board address control unit shown in FIGS. 4 and 9;

FIG. 17 is a flowchart showing the operation of the in-board address control unit shown in FIGS. 4 and 9;

FIG. 18 is a flowchart showing the operation of the in-board address control unit shown in FIGS. 4 and 9;

FIG. 19 is a flowchart showing the operation of the in-board address control unit shown in FIGS. 4 and 9;

FIG. 20 is a flowchart showing the operation of the in-board address control unit shown in FIGS. 4 and 9;

FIG. 21 is a flowchart showing the operation of the in-board address control unit shown in FIGS. 4 and 9;

FIG. 22 is a flowchart showing the operation of the in-board address control unit shown in FIGS. 4 and 9;

FIG. 23 is a flowchart showing an operation of the in-board address control unit shown in FIGS. 4 and 9;

FIG. 24 is a diagram showing a case of data transfer in the crossbar switch device according to one embodiment of the present invention.

FIG. 25 is a diagram illustrating an operation on the request side when a 256-bit band can be secured when transferring 256-bit data to a 256-bit port according to an embodiment of the present invention.

FIG. 26 is a diagram illustrating an operation on the supply side when a 256-bit band can be secured when transferring 256-bit data to a 256-bit port according to an embodiment of the present invention.

FIG. 27 is a diagram illustrating an operation on the request side when a 128-bit band can be secured when transferring 256-bit data to a 256-bit port according to an embodiment of the present invention.

FIG. 28 is a diagram illustrating an operation on the supply side when a 128-bit band can be secured when transferring 256-bit data to a 256-bit port according to an embodiment of the present invention.

FIG. 29 is a diagram illustrating an operation on the request side when a band cannot be secured when transferring 256-bit data to a 256-bit port according to an embodiment of the present invention.

FIG. 30 is a diagram illustrating an operation on the supply side when a band cannot be secured when transferring 256-bit data to a 256-bit port according to an embodiment of the present invention.

FIG. 31 is a diagram illustrating an operation on the request side when a 128-bit band can be secured when transferring 128-bit data to a 256-bit port according to an embodiment of the present invention.

FIG. 32 is a diagram illustrating an operation on the supply side when a 128-bit band can be secured when transferring 128-bit data to a 256-bit port according to an embodiment of the present invention.

FIG. 33 is a diagram illustrating an operation on the request side when a band cannot be secured when transferring 128-bit data to a 256-bit port according to an embodiment of the present invention.

FIG. 34 is a diagram illustrating an operation on the supply side when a band cannot be secured when transferring 128-bit data to a 256-bit port according to an embodiment of the present invention.

FIG. 35 is a diagram illustrating an operation on the request side when a 128-bit band can be secured when transferring 256-bit data to a 128-bit port according to an embodiment of the present invention.

FIG. 36 is a diagram illustrating an operation on the supply side when a 128-bit band can be secured when transferring 256-bit data to a 128-bit port according to an embodiment of the present invention.

FIG. 37 is a diagram illustrating an operation on the request side when a band cannot be secured when transferring 256-bit data to a 128-bit port according to an embodiment of the present invention.

FIG. 38 is a diagram illustrating an operation on the supply side when a bandwidth cannot be secured when transferring 256-bit data to a 128-bit port according to an embodiment of the present invention.

FIG. 39 is a block diagram illustrating a configuration of a crossbar switch device according to a conventional example.

40 is a block diagram illustrating a configuration of the processor board in FIG. 39.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Crossbar switch device 2-1 and 2-2 Processor board 3-1 and 3-2 Memory board 4-1 to 4-4 I / O board 5 Crossbar switch 6-1 to 6-4 Crossbar switch side input / output unit 7 -1 to 7-4 Data section 8-1 to 8-4 Address control section 61-1 Crossbar switch side address control section 61a-1 Controller 61b-1 Memory (A) 61c-1 Memory (B) 71-1 On board Switch 72-1, 73-1 Buffer 74-1 to 76-1, 71a-1 to 71j-1 Switch 77-1 Buffer A group 78-1 Buffer B group 81-1 In-board address control unit 81a-1 Controller 81b -1 Memory (C) 81c-1 Memory (D) 81d-1 to 81g-1 Counter 82-1 In-board switch control unit

Claims (15)

(57) [Claims] 1. A variable data width crossbar switch device having a plurality of ports having the same data width to which a plurality of boards are respectively connected, and connecting the plurality of boards via the plurality of ports, When the data width between the communicating boards is different,
Free of the ports to which the wide board is connected
Detecting means for detecting the port, and detecting by the detecting means
Means for communicating with other boards via ports.
And assign the ports to the wide data board.
And the detecting means assigns to the board having the wide data width.
Of available ports from multiple ports
And so that arrangement, through the communication and the other boards of the board between the said communication
A variable-width data type crossbar switch device wherein a single address line is used for communication. 2. The method according to claim 1, wherein the detecting means includes a button having a wide data width.
Address from each of the multiple ports assigned to the mode
The used port among the plurality of ports based on the information.
The variable data width type crossbar switch device according to claim 1, wherein the crossbar switch device is configured to be specified . 3. The method according to claim 1, wherein the detecting means includes a plurality of boards.
Storage means for storing information on ports assigned to
Communication for each port assigned to each of the plurality of boards
Each board of the partner and each port assigned to the board
Holding means for holding information for specifying
The variable data width crossbar switch device according to claim 1 or 2, wherein: 4. A data width of a board having a large data width.
Data held and exchanged between the board and the communication partner
The board includes first and second storage means for storing data.
4. The method according to claim 1, wherein
Placing data width variable crossbar switch device. 5. A communication method between a board having a wide data width and a communication partner.
To set the input / output path for data exchanged between
2. The method according to claim 1, wherein steps are included on the board.
The variable data width crossbar switch device according to claim 4. 6. The same data to which a plurality of boards are respectively connected.
Having a plurality of ports of different widths, through the plurality of ports
A variable data width crossbar connecting the plurality of boards
A method of connecting a switch device , wherein the data width is different when data widths of boards communicating with each other are different.
Free of the ports to which the wide board is connected
Detecting a port and passing the detected port
Performing communication with another board by allocating the plurality of ports to the board having a large data width.
Teru as to, the step of detecting the free port said, the Day
In multiple ports assigned to wide boards
Vacant ports are detected to allow communication between the boards to communicate with each other and communication with the other boards.
To use one address line for communication.
Characteristic variable width crossbar switch device connection
Method. 7. A step for detecting said vacant port.
Group is assigned to a board with a large data width.
Ports based on address information from each of the ports.
Port that is being used
7. A variable width data type cross bus switch according to claim 6, wherein
How to connect switch devices. 8. A step for detecting a vacant port.
Group of ports assigned to each of the boards
Storage means for storing information; and
For each assigned port, the board of the communication partner and the board
Holds information identifying each port assigned to the
Detecting the vacant port using the holding means
8. The method according to claim 6, wherein
Connection method of the variable data width type crossbar switch device described above. 9. The data width of said wide data board
One of the first and second storage means has the board
To store data exchanged between and
9. A method according to claim 6, wherein
How to connect the described data width variable type crossbar switch device
Law. 10. A communication partner with the board having a wide data width.
For setting the input / output path for data exchanged with the
10. The method according to claim 6, further comprising:
The connection of the variable data width type crossbar switch device
How to continue. 11. The same data to which a plurality of boards are respectively connected.
It has a plurality of ports with different data widths, and
To connect the plurality of boards to the processor.
On a recording medium on which a connection control program for
The connection control program sends the data to the processor when the data width of the communicating boards is different.
Free of the ports to which the wide board is connected
Port is detected, and other ports are detected via the detected port.
Communication with the data port, and when detecting the vacant port, the data width
Is empty among multiple ports assigned to wide boards
Ports that are in communication with each other, and communication between the boards that communicate with each other and communication with the other boards.
Communication using a single address line.
Recording medium on which a connection control program to be connected is recorded. 12. The connection control program according to claim 1, wherein
When the server detects the vacant port,
Multiple ports assigned to wide data boards
Out of the plurality of ports based on address information from
2. The system according to claim 1, wherein the port in use is specified.
A recording medium on which the connection control program according to 1 is recorded. 13. The connection control program according to claim 1, wherein
When the server detects the vacant port,
Stores information on ports assigned to each of multiple boards
Storage means to be assigned to each of the plurality of boards.
Assigned to each board and the corresponding board for each port
Holding means for holding information for specifying each assigned port
And detecting the vacant port using
A connection control program according to claim 11 or 12, wherein
A recording medium on which a program is recorded. 14. The connection control program according to claim 1, wherein
The data width of the board with the wider data width.
One of the first and second storage means communicates with the board
Stores data exchanged with the other party
The connection according to any one of claims 11 to 13, wherein
A recording medium on which a control program is recorded. 15. The connection control program according to claim 15, wherein
Between the data wide board and the communication partner.
It is characterized by setting the input / output path of the data to be exchanged
The connection according to any one of claims 11 to 14, wherein
A recording medium recording a control program.