JP3188874B2 - Adaptive and variable rate symbol timing recovery system with asynchronous sampling for digital signal receivers and method for receiving symbols with variable timing in digital signal receivers - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a high-speed digital receiver, such as a digital television signal receiver, having an adaptive, ie, reconfigurable, symbol timing recovery system with asynchronous sampling. This system can be used to process signals with different data transmission rates and different modulation schemes.

[0002]

BACKGROUND OF THE INVENTION Certain types of digital data signals transmitted are of a type that is not readily effective with conventional phase locked loop detection techniques. In a typical phase locked loop detector, the timing of the sampling clock is adjusted for optimum symbol detection by synchronizing the sampling to the symbol rate of the input signal.

[0003] In certain cases, such as digital processing of asynchronous frequency multiplexed signals, sampling cannot be synchronized with the input signal.

When the sampling clock cannot be changed, by interpolating between asynchronous samples, the correct strobe value, which is the same strobe value that would have occurred if the original sampling had been synchronized with the symbol, was obtained. Systems for generating at the output of a digital processor have already been proposed.
(F. M. Gardner, "Interpolation in Digital Modems-Part I: Basics," IEEE Communication Division Bulletin 41-3
Issue, Pages 501-507, March 1993, and "Interpolation in Digital Modems-Part II," IEEE.
E-Communications Division Bulletin Vol. 41, No. 6, pp. 998-1008,
(See June, 1993)

Although the interpolation system proposed by Gardner is adjustable to a limited extent, high-speed data services, such as digital television signal transmission, have various data transmission standards that coexist, and therefore Gardner's interpolation system is difficult. More variability than is assumed in the proposal is required.

In a somewhat analogous situation involving an adaptable modem, the two inventors Bao and Poon of the present invention, along with their co-workers Oshiki Mitsutani and Hiroki Nakayama, are reconfigurable. An approach has been taken to provide a "universal modem for digital video, audio and data communications" (US application).
The configuration of the general-purpose modem is configured such that the modem can reconfigure software so as to support different data transmission rates and different modulation schemes.

[0007]

Accordingly, there has hitherto not been an adaptive and variable rate symbol timing recovery system by asynchronous sampling for digital signal receivers that can support different data transmission rates and different modulation schemes.

In this regard, the present invention seeks to provide a reconfigurable symbol timing recovery system programmed (software) controlled by asynchronous sampling for a digital signal receiver. This system uses vestigial sideband modulation (VSB-broadcast signal), horizontal amplitude modulation (QAM-cable signal), and horizontal phase shift modulation (Q
It is particularly suitable for processing high-resolution digital television signals with various criteria, such as PSK-satellite.

[0009]

SUMMARY OF THE INVENTION In view of the above, the present invention provides an A / D converter having an analog signal input terminal and a digital data signal output terminal , and the A / D converter.
For sampling a signal received at said input terminal at a predetermined, substantially fixed clock rate depending on its data transmission rate and modulation characteristics;
A selectable, substantially fixed rate data sampling clock signal source and coupled to the digital data signal output terminal, wherein the signal is asynchronous to the substantially fixed clock rate clock signal. Digital signal interpolation processing loop means for adjustably generating an interpolation signal synchronously with data at the output terminal; and a data sampling clock signal source according to the data transmission rate and modulation characteristics of the received signal. When
Controller means for variably configuring the digital signal interpolation processing loop means. Adaptive, variable rate symbol timing by asynchronous sampling for a digital signal receiver. In the recovery system. The present invention also relates to the digital signal interpolation processing routine.
Means for controlling the data sampling clock signal
The interpolated signal is obtained by interpolating between asynchronous data signals.
Interpolating means for generating
There is a timing interval between the interpolation signals
The imaging interval is adjusted by the loop means, and
Substantially synchronized with the data symbol of the digital data signal
2. A strobe according to claim 1, wherein
Asynchronous sampling for the described digital signal receiver
Adaptable, variable rate symbol timing recovery system
You. The present invention also relates to the digital signal interpolation processing routine.
Means can be connected to said A by selectively configurable coupling means.
/ D converter connected to the digital data signal output terminal
And the configuration is the data transmission rate of the received signal.
Selected by the controller means according to the degree and modulation characteristics.
3. The digital device according to claim 2, wherein
Adaptive, variable with asynchronous sampling for signal receivers
Speed symbol timing recovery system. The invention
Wherein said selectively configurable coupling means comprises at least one
And two low-pass filters, the pre-filter.
4. A non-digital signal receiver for a digital signal receiver as claimed in claim 3.
Adaptive, variable-speed symbol timing with synchronous sampling
In the recovery system. The present invention also provides
The configurable coupling means further comprises an alternative direct signal path
The digital signal reception according to claim 4, wherein
And variable speed symbols with asynchronous sampling for aircraft
In the timing recovery system. Also, the present invention
Digital signal interpolation processing loop means further includes the processing loop.
Coupled within the feedback control path of the
Extract timing information from digital data signals
Based on the high-pass filter and the timing information
Timing for supplying feedback correction signal
A phase error detector and the feedback correction signal
Supply an adjustable reference signal to the interpolation means in response to the signal
And a controlled oscillator for performing
An asynchronous sun for a digital signal receiver according to claim 3.
Adaptive, variable rate symbol timing recovery system by pulling
On the stem. Further, according to the present invention, the interpolation means further comprises:
Data signal samples in response to the controller means;
Circular buffer register for storing and rotating
7. The digital device according to claim 6, comprising:
Adaptive, variable with asynchronous sampling for signal receivers
Speed symbol timing recovery system. The invention
Means that the controlled oscillator has a plurality of
A selectable internal clock signal to the data sampler.
Multiple and multiple controllable clocking signals.
In the phase adjustment, the fixed speed data sampling clock
Numerically controlled source for supply regardless of lock signal source
The digitizer according to claim 6, further comprising a shaker.
Adaptive with asynchronous sampling for total signal receivers,
In a variable speed symbol timing recovery system. Also this
The invention is characterized in that the number controlled oscillator is controlled by the controller
Provides the ability to supply the internal clock signal at a selected multiple.
9. A non-digital signal receiver for a digital signal receiver as claimed in claim 8.
Adaptive, variable-speed symbol timing with synchronous sampling
In the recovery system. The present invention also relates to the aforementioned digital
Furthermore Le signal interpolation processing loop means, off for the interpolation hand stage
Register file means for storing filter coefficients
9. The digital signal according to claim 8, comprising:
And variable speed with asynchronous sampling for signal receivers
Symbol timing recovery system. The invention
The digital signal interpolation processing loop means further comprises
Data signal samples with each of the filter coefficients
And a vector multiplication circuit for
An asynchronous sun for a digital signal receiver according to claim 10.
Adaptive, variable rate symbol timing recovery system by pulling
On the stem. The present invention also provides the digital signal compensator.
Inter-processing loop means further includes the data signal sample and the
Addition times for combining multiple combinations of filter coefficients
12. The digitizer according to claim 11, comprising a path.
Adaptive with asynchronous sampling for total signal receivers,
In a variable speed symbol timing recovery system. Also this
The present invention relates to an A / D converter for receiving an analog signal, and an analog / digital converter.
Generates digital signal by sampling log signal
To generate a clock signal for the A / D converter
Data sampling clock signal source
The clock rate of the clock signal is
According to the data rate and modulation characteristics of the log signal
From the sampled analog signal.
Interpolation means for generating the signal and the data rate of the received signal
And the speed of the clock signal according to the modulation characteristics and
Controller means for setting the frequency of occurrence of the symbol.
Non-synchronous digital signal receiver characterized by having
Adaptive, variable speed symbol timing with periodic sampling
In the recovery system. The present invention also provides an A / D converter.
Receiving an analog signal in the
Clock according to data rate and modulation characteristics of log signal
Selecting the speed of the signal;
Sample the received analog signal at the rate of the clock signal
Generating a digital signal;
Decoding at a rate according to the data rate and modulation characteristics of the signal
Generating a symbol by interpolating digital symbols.
Variable signal in digital signal receiver characterized by the following:
There is a method for receiving symbols with imming.

[0010]

[0011]

[0012]

[0013]

[0014]

[0015]

[0016]

[0017]

[0018]

[0019]

[0020]

[0021]

BRIEF DESCRIPTION OF THE DRAWINGS The above and other features of the present invention will be more clearly understood from the detailed description with reference to the accompanying drawings, in which: FIG.

The basic equations for digital interpolation of data and signals as disclosed by Gardner are as follows.

[0023]

(Equation 1)

Where {x (n)} is a series of signal samples extracted during the interval T _s and h _I (t) is a virtual, time-continuous analog interpolation filter with a finite duration. It is an impulse response. Interpolation section at adjustable intervals T _i by digital operation based on the above equation y (k) is obtained. T _i is not commensurate to the generally T _s (incommensurate). In the equation, the filter index i = I ₁
To I ₂ , (I = I ₂ − used for the kth interpolation term
The base point index n _k (specifying the I ₁ +1 signal sample) and the period μ _{k of} the segment (specifying the filter index of I used for the kth interpolation term) are parameters of importance.

As shown in FIG. 1, adaptive by asynchronous sampling for a digital signal receiver according to the invention,
In operation of a variable rate symbol timing recovery system, samples of the input signal x (t) are sampled at a frequency of 1 / T _s
A predetermined sampling clock from the clock circuit 22
(“Sampling clk”)
It extracted with uniform spacing _{T s} at D converter 20. The operating frequency of the master clock circuit 22 is set by the controller 24 according to the nature of the input signal. The sample can be specified as x (nT _s ) = x (n).

The signal sample x (n) is supplied to the interpolation circuit 26 directly or via the pre-filter 28 depending on the modulation method and the data transmission rate of the input signal. Pre-filter 28 is a selectable low-pass filter that is switched based on control information provided from controller 24. As mentioned above, the controller 24 configures the system according to the information contained in the input signal or the nature of the signal received in response to locally provided control information.

The interpolation circuit 26 which details are supplemented illustrated in Figure 2 supplies a y (kT _i) = interpolation section can be identified as y (n) in interval T _i.

The interval T _i is actually strobes in the loop so that the data symbols and the synchronization state of the signal is adjusted by the timing loop. That is, the effective interpolation interval T _i is not constant, is set by operation of the timing recovery loop. The data output y (n) is provided by an interpolation circuit 26 as shown.

The output of the interpolator 26 is also provided to a high pass filter 30 in the feedback control path of the timing loop. The high-pass filter 30 extracts signal timing information.

The output of the high pass filter 30 is coupled to a timing phase error detector 31 which, via a loop filter 32, controls a numerically controlled oscillator (NC).
O) 34 coupled to the control input. Timing phase error detector 31 and loop filter 32 operate in the manner normally used in a second order phase locked loop system.

[0031] NCO34 is operated such that the average period is equal to _{T i.} If the NCO register is recirculated, the NCO register
(See FIG. 2), using the currently existing signal samples, indicates that a new interpolation term should be calculated.

The block 37 labeled "Calculate gaps between missing parts" operates in the manner described by Gardner, for example, to adjust interpolator 26 to properly sample the signal. Block 37, which operates in a manner similar to Gardner, operates by drawing samples from a circular buffer, which stores, for example, 1024 samples. For each incoming event, 64 samples are each drawn out of the buffer. Each sample is 16 bits. However, according to Gardner, the sampling need not be a conditioned word, which may be a stripped portion. That is, it can start anywhere in the middle of a word. Therefore, the first index (rpt data) indexes words and rpt coef simply supplies the stripped part.

As shown in FIG. 2, the interpolator 26 stores the aforementioned circular buffer register 36 for storing and supplying data samples, and (for the illustrated 64-tap interpolator filter C ₀ -C _63). And a register file 38 for storing the interpolation circuit filter coefficients and the filter coefficients (C ₀ -C ₆₃ ) for the data signals (d ₀ -d ₆₃ ).
₆₃₎ and by suitably combining the vector multiply circuit 40 for generating a data signal _(z 0 _{to z 63),} a combination of multiplied signal _(z 0 _{to z 63),} their control of the counter 46 To the "data output" (y (n)) line and logic module 44 to provide the necessary control functions. Note that in FIG. data is the read pointer for data (adjusted word) from the circular buffer, rpt
coef is a read pointer for the coefficient (offset of the lost part), wpt data is a write pointer for the data (adjusted word), w
pt coef is a write pointer for the coefficient (the broken part in the word). These pointers are the same as the starting addresses for the search values in the interpolator 26 and register file 38. Since the data and coefficients are stored in the register file 38 and the circular buffer and need to be retrieved by the interpolator, a starting address is needed for each set of data and coefficients. Also,
The over / underflow flag is provided merely to detect an over or underflow condition in the circular buffer.

The system further includes a master clock 2
From the output of 2, with 1 / T as the nominal symbol transmission rate , 1 / T
It also includes a clock divider 48 for generating a clock at a rate of T, 2 / T, 4 / T. The output of clock divider 48 is selected by controller 24 to correspond to a particular type of received signal.

A read only memory (ROM) 50 is coupled to the controller 24 and stores appropriate data, such as filter coefficients, loop constant parameters, and loop gain parameters as needed.

The controller 24 also initializes, tests, and re-boots various parts of the system.
ting) and interface with some external control device (not shown).

In high-speed digital data services,
The data transmission rates can be quite different depending on the application. For example, a digital broadcasting satellite service (I
TUDVB-S) is from 20.3MHz to 42.2MHz
Adopts a data transmission rate that fluctuates between
Only 6MHz for U.S. ground station / cable broadcasting service
(ATSC Digital Television Standards Document A / 53, 1995).

In certain applications, conventional timing recovery circuits can be designed to provide synchronized samples of the input signal for digital demodulation in the receiver. Generally, they cannot be reused for other uses. Unlike conventional timing recovery circuits, the variable speed timing recovery system according to the present invention requires different data transmission rates with maximum hardware utilization (i.e., minimal unused hardware). Can be easily reconfigured to meet. In addition, it can be reconfigured to accommodate different modulation schemes such as, for example, 64/256 QAM, QPSK, 8-PSK.

Although the present invention has been described with reference to preferred embodiments, it is to be understood that the above description is merely illustrative and is not restrictive and is provided by way of example only. It will be clear to you. Modifications and other embodiments are possible for those skilled in the art, and are within the scope of the invention, which is limited only by the appended claims and equivalents thereof.

[0040]

An adaptive and variable rate symbol timing recovery system with asynchronous sampling for a digital signal receiver according to the present invention comprises an A / D (analog / digital) having an analog signal input terminal and a digital data signal output terminal. ) A signal converter is provided. A selectable, substantially fixed rate data sampling clock signal source is provided for sampling at a predetermined, substantially fixed clock rate depending on the data transmission rate and modulation characteristics of the received signal. It is coupled to a signal converter. Digital signal processing loop means is coupled to the digital data signal output terminal to adjustably generate an interdependent signal synchronously with the data at the output terminal which is asynchronous to the fixed speed clock signal. ing. Controller means are provided for selectively configuring a data sampling clock signal source and a digital signal processing loop according to the data transmission rate and modulation characteristics of the received signal. Thus, the reconfigurable symbol timing recovery system of the present invention, which is program (software) controlled by asynchronous sampling, can be used to process signals with different data transmission rates and different modulation schemes.

[Brief description of the drawings]

FIG. 1 is a block diagram of an adaptive, variable rate symbol timing recovery system with asynchronous sampling for a digital signal receiver that can reconfigure the system according to one embodiment of the invention for different signal modulation schemes.

FIG. 2 is a configuration diagram showing details of an interpolation circuit portion of the system of FIG. 1;

[Explanation of symbols]

20 A / D converter, 22 master clock circuit,
24 controller, 26 interpolation circuit, 28 pre-filter, 30 high-pass filter, 31 timing phase error detector, 32 loop filter, 34 number control oscillator, 36 circulating buffer register section, 38
Register file, 40 vector multiplication circuit, 42
Adder circuit, 44 logic module, 46 counter,
48 clock divider, 50 ROM.

──────────────────────────────────────────────────続 き Continuation of the front page (73) Patent owner 597067574 201 BROADWAY, CAMBR IDGE, MASSACHUSETT S 02139, U.S.A. S. A. (72) Inventor Tommy Sea Poon Marie Hill Boulevard, New Jersey, USA 75 (56) References JP-A-3-207148 (JP, A) JP-A-9-130444 (JP) , A) JP-A-10-200594 (JP, A) JP 9-501279 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 27/00-27/38

Claims (14)

(57) [Claims] An A / D converter having an analog signal input terminal and a digital data signal output terminal; and a signal coupled to the A / D converter and receiving a signal received at the input terminal. A selectable, substantially fixed rate data sampling clock signal source for sampling at a predetermined, substantially fixed clock rate depending on modulation characteristics; and the digital data signal output terminal. And a digital signal for adjustably generating an interpolation signal synchronously with data at the output terminal which is asynchronous with respect to the clock signal at the substantially fixed clock rate.
Interpolating loop means , variably changing the data sampling clock signal source and the digital signal interpolating loop means according to the data transmission rate and modulation characteristics of the received signal.
Digital signal adaptable by asynchronous sampling receiver, variable speed symbol timing recovery system, characterized by comprising a controller means for configuring the. 2. The digital signal interpolation processing loop means
But includes an interpolation means for generating the interpolation signal by interpolating between the asynchronous data signal to the data sampling clock signal, the interpolation signal has a timing interval between adjacent interpolated signal 2. The digital signal receiver of claim 1 wherein said timing interval is adjusted by said loop means to provide a strobe substantially synchronized with data symbols of said digital data signal. Adaptive, variable rate symbol timing recovery system with asynchronous sampling. 3. The digital signal interpolation loop means is coupled to the digital data signal output terminal of the A / D converter by selectively configurable coupling means, the configuration of which comprises the receiving means. 3. The adaptive and variable rate symbol timing recovery system with asynchronous sampling for a digital signal receiver according to claim 2, wherein said controller means is selected by said controller means according to the data transmission rate and modulation characteristics of the signal. 4. The apparatus according to claim 3, wherein said selectively configurable coupling means comprises at least one low-pass filter pre-filter. Adaptive, variable speed symbol timing recovery system. 5. The adaptive, variable speed, asynchronous sampling by digital sampling receiver of claim 4, wherein said selectively configurable coupling means further comprises an alternative direct signal path. Symbol timing recovery system. 6. The digital signal interpolation processing loop means is further coupled in a feedback control path of the processing loop means, and includes a high pass filter for extracting timing information from the digital data signal. A timing phase error detector for providing a feedback correction signal based on the timing information, and a controlled oscillator for supplying an adjustable reference signal to the interpolation means in response to the feedback correction signal; 4. The adaptive and variable rate symbol timing recovery system with asynchronous sampling for a digital signal receiver according to claim 3, further comprising: 7. The digital signal of claim 6, wherein said interpolating means further comprises a circular buffer register for storing and circulating data signal samples in response to said controller means. Adaptive, variable rate symbol timing recovery system with asynchronous sampling for receivers. 8. The controlled oscillator fixes a plurality of selectable internal clock signals for the processing loop means at a plurality of multiples of the data sampling clock signal and with controllable phase adjustment. 7. An adaptive, variable rate symbol with asynchronous sampling for a digital signal receiver according to claim 6, further comprising a numerically controlled oscillator for providing a rate data sampling clock signal regardless of the source. Timing recovery system. 9. The adaptive, variable speed, asynchronous sampling with asynchronous sampling for digital signal receiver of claim 8, wherein said number controlled oscillator supplies an internal clock signal at a multiple selected by said controller. Symbol timing recovery system. 10. A digital signal interpolation processing loop.
9. The adaptive variable-speed symbol with asynchronous sampling according to claim 8, wherein the stage further comprises register file means for storing filter coefficients for said interpolation means. Timing recovery system. 11. The digital signal interpolation processing loop
11. The adaptive, variable rate, asynchronous sampling, asynchronous sampling for digital signal receiver according to claim 10, wherein the stage further comprises a vector multiplication circuit for combining data signal samples with each of the filter coefficients. Symbol timing recovery system. 12. A digital signal interpolation processing loop.
The adaptive sampling with asynchronous sampling for digital signal receiver according to claim 11, wherein the stage further comprises a summing circuit for combining a plurality of combinations of the data signal samples and filter coefficients. Shift symbol timing recovery system. 13. An A / D converter for receiving an analog signal.
And analog signals are sampled to generate digital signals
To generate a clock signal for the A / D converter.
Data sampling clock signal source
The clock speed of the clock signal is
According to the data rate and modulation characteristics of the analog signal
And generating a symbol from the sampled analog signal.
Interpolation means, depending on the data rate and modulation characteristics of the received signal.
Set the clock signal speed and frequency of occurrence of the above symbols
Controller means for a digital signal receiver, comprising:
Adaptive, variable-speed symbol timing with synchronous sampling
Recovery system . 14. An analog signal is converted by an A / D converter.
Receiving and adjusting the data rate and modulation characteristics of the received analog signal.
Selecting the speed of the clock signal, and receiving at the rate of the clock signal in the A / D converter.
Generates digital signal by sampling analog signal
And the rate according to the data rate and modulation characteristics of the received signal.
Process of generating symbols by interpolating digital symbols with
And a digital signal receiver characterized by comprising:
Of receiving symbols having variable timing.