JP3185670B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic random access memory, and more particularly to a technique used to prevent a deterioration of a sensing operation due to a fluctuation of a power supply voltage.

[0002]

2. Description of the Related Art Recent semiconductor memory devices, in particular, dynamic random access memories (hereinafter referred to as "DRAMs")
16M (mega) DRAMs and 64M DRAMs have been increased in capacity, and accordingly, circuit elements and wiring have been miniaturized. As a result, the inside of the device is, for example, 3.3 V
It operates at such a low voltage.

[0003] In addition, the demand for DRAMs is increasing year by year, and how to increase the production quantity is becoming an issue.

An obstacle to this is an increase in device test time due to an increase in the capacity of the DRAM.
Since it is inevitable that a variety of tests must be performed as compared with the related art, there is a limit to the test time that can be reduced.

[0005] Therefore, reduction of the PR (photoresist) process, which takes an enormous amount of time as compared with the device test time, is being studied and is currently being practiced. If circuit elements and wiring can be patterned on a silicon substrate with a small number of PRs, not only the time required for PRs but also the cost can be reduced, which greatly contributes to improvement in productivity.

Due to recent advances in process technology, the same
Even with 6MDRAM, patterning can be realized with a smaller number of PRs than before. Among the PR processes in which the reduction has actually been performed, there is a process called a capacitance arsenic PR.

When a MOS transistor functions as a capacitor, the MOS transistor is of a depletion type and must be made conductive even when no voltage is applied between its gate and source (or drain). In order to achieve this state, it is necessary to perform the above PR after forming an enhancement-type MOS transistor that becomes conductive when a voltage higher than the threshold voltage is applied between the gate and source (or drain). . That is, the depletion type requires more PR than the enhancement type.

Actually, the enhancement type MOS transistor is overwhelmingly used as a circuit element (active element) more than the depletion type MOS transistor, and the depletion type MOS transistor is used only as a capacitor. If the voltage applied between the gate and source (or drain) of the transistor used as the transistor is always equal to or higher than the threshold voltage, even if it is an enhancement type, it will function as a capacitor similarly to the depletion type. PR can be reduced.

In a sense operation at the time of reading of a DRAM, a method is adopted in which a memory cell of interest is started after slightly lowering the potential of a "paired" digit line from the potential at the time of precharging. Is realized by capacitive coupling.

The capacitance (referred to as "dummy cell") used for the capacitive coupling is formed of a MOS transistor.
The transistor is changed from a depletion type to an enhancement type.

Incidentally, since the sense operation is indispensable for the DRAM, there is a concern that the operation may be affected by the enhancement of the capacity as described above.

FIG. 6 is a diagram showing a configuration in a memory cell array of a DRAM. In FIG. 6, Q40 and Q41 correspond to dummy cells. The sense operation when the dummy cell changes from the depletion type to the enhancement type due to the deletion of the PR will be described below together with the operation of the dummy word.

In FIG. 6, Q00 to Q60 are MOS transistors, of which Q10 and Q11 are P-channel MOS transistors (referred to as "Pch transistors"), and the others are N-channel transistors (referred to as "Nch transistors"). C00 and C01 are capacitances constituting a memory cell of the DRAM. SAP / SAN is a power supply supplied to a sense amplifier composed of Nch transistors Q10, Q20, Q11, Q21.

YSW is an Nch transistor Q00, Q01 constituting a Y switch, TG is an Nch transistor Q30,
This signal controls conduction / non-conduction of the transfer gate of Q31.

WL0 and WL1 are word lines, each of which has N
The charges are input to the gates of the channel transistors Q51 and Q50, and the charges of the capacitors C01 and C00 are transmitted to the digit lines DB and D, respectively.

PDL connects digit line D / DB to HV
It is used for precharging using a constant potential of 1/2 of a power supply voltage called CD (referred to as “HVCC potential”).
HVCD is input to the digit line and the opposite electrode of C00 and C01.

DWL0 and DWL1 are dummy words.
It is input to the gates of Q41 and Q40 of the dummy cell. The sources and drains of the transistors Q40 and Q41 are short-circuited to each other and connected to digit lines D and DB, respectively.
The transistors Q40 and Q41 are not transistors but exist as capacitance between the dummy word and the digit line.

There are two dummy words, one for each digit line. In FIG. 6, the digit line corresponding to D corresponds to DWL0, and the digit line corresponding to DB corresponds to DWL1.

FIG. 7 shows a timing waveform of each signal. The sensing operation in the DRAM shown in FIG. 6 will be described with reference to FIG. Hereinafter, the “H” level indicates the power supply potential VC.
C and the “L” level mean the GND potential.

When a row address is fetched, a PDL corresponding to the address is selected, and the PDL changes from "H" level to "L" level. Then, in FIG. 6, the transistor Q60 changes from the conductive state (ON) to the non-conductive state (OFF).
And the digit line D / DB is disconnected from the HVCD,
Floating state at HVCC potential.

Next, the signal φ for activating the word and sense amplifier power supply changes from "L" to "H", the selected word line changes from "L" to "H", and the sense amplifier power supply SAP / SAN starts to change to VCC / GND level, respectively.

Here, it is assumed that word line WL1 is selected and memory cell C00 stores "H" data (VCC potential).

The signal φ causes the word line WL1 to rise from the "L" level to the "H" level, but before that, the dummy word DWL0 falls from the power supply potential VCC to the HVCC potential.

The dummy words DWL0 and DWL1 are shown in FIG.
The operation of this circuit is described as follows.
First, a description will be given.

In FIG. 8, signal X0 is the least significant bit of the row address, and is input to the first CMOS inverter consisting of Pch transistor QP0 and Nch transistor QN0 via AND gate AND1 which receives X0 and signal φ. , X0B (complementary (inverted) value of X0) and a signal AND, and a second CMO including a Pch transistor QP1 and an Nch transistor QN1 via an AND gate AND2.
It is input to the S inverter and the first and second inverters output dummy words DWL0 and DWL1. In addition,
In the first and second inverters, the sources of the Pch transistors QP0 and QP1 are connected to the power supply potential VCC, and the sources of the Nch transistors QN0 and QN0 are connected to the HVCD potential.

In FIG. 6, the correspondence between DWL0 and DWL1 and X0 and X0B is such that if word line WL1 is selected when row address least significant bit signal X0 is "H", then X0 is "H". , DWL0 and X0B are “H”.
At this time, DWL1 is selected.

Therefore, in FIG.
Are combined so that DWL1 is selected by X0B.

The row address is fetched, and X0, X0B
Changes from “L” to “H” and φ changes from “L” to “H”, so that X0 becomes “H”.
DWL0 when the complementary signal X0B of X0 is "H", and DWL1 when the complementary signal X0B is "H".
Descent to D.

That is, when the word line WL1 is selected, the potential of the digit line DB which is "paired" with the digit line D connected to the transistor Q50 which is turned on by WL1 is higher than the power supply potential VCC from HVC.
As much as it drops to D, it drops due to capacitive coupling with the dummy cell capacity Q41.

The operation of the dummy word is for lowering the potential of the digit line that forms a "pair" with the digit line to which data is transmitted from the memory cell by capacitive coupling with the capacity of the dummy cell. "H" due to α-rays from the resin when assembled into a product
An object of the present invention is to prevent the data sensing operation from deteriorating or falling into a state where data cannot be sensed.

The capacity of the dummy cell and the amount of drop of the dummy word are optimally set in consideration of variations in the sensing operation and manufacturing conditions. Usually, the dummy word is configured to drop from the power supply voltage to the ground potential or from the power supply voltage to the HVCC potential.

The HVCC potential is a potential obtained from a 1/2 VCC generation circuit which is currently widely used.
Since it is always stable, it can be used not only for precharging the digit lines but also for determining the amount of drop of the dummy word in order to improve the sensing operation.

As described above, immediately before the word line WL1 changes from "L" to "H", the potential of the digit line D becomes HVC.
Although the potential is C, the pair of digit lines DB has a potential slightly lower than the HVCC potential, and in FIG.
The amount indicated by is the amount, which is the amount dropped by capacitive coupling.

Referring again to FIG. 6, when word line WL1 changes from "L" to "H" in this state, transistor Q50 is turned on, and "H" data is transmitted from memory cell C00 to digit line D. , Digit line D is HVC
It rises from the C potential.

At this time, the control signal TG is at the "H" level, the transfer gates Q30 and Q31 are turned on, and the potential of the digit line D / DB is set as the difference potential.
After passing through Q30 and Q31, it propagates to the sense amplifier.

If a difference potential is applied to the sense amplifier, the memory cell side appears as a "load" to the sense amplifier from the transfer gates Q30 and Q31. Through T
G changes from “H” to “L”.

Thereafter, the sense amplifier power supply SAP / SAN
Respectively start to change from the HVCC potential to VCC / GND, the amplification operation of the sense amplifier is started.

The digit line pair D / DB follows the sense amplifier power supply SAP / SAN and eventually becomes almost VCC / GN.
D, the TG gradually changes from "L" to "H" again, and the potential of the digit line pair D / DB propagates to the memory cell side by the transfer gates Q30 and Q31, and is stored again in the memory cell C00. Can be

Thus, the "H" data sensing operation of the memory cell C00 is completed, and the column selection line YSW is set to "L".
From “H” to “H”, and the switching transistor Q0
0 and Q01 are turned on, the digit line D / DB and the IO bus are conducted, and the read / write operation is enabled thereafter.

Next, when the "H" data actually comes out of the memory cell C00, the digit line D is determined by the difference potential between the digit line pair D / DB and the dummy word DWL0.
Consider the drop in the potential of B.

The difference potential of the digit line D / DB due to "H" data transmitted from the memory cell capacitance C00 is .DELTA.VS, the variation of the digit line due to the dummy word DWL0 is .DELTA.VDW, and the capacitance of the memory cell C00 is CS. Assuming that the capacity of the dummy cell Q40 is CDW, the wiring capacity of the digit line D / DB is CD, and HVCC is 1/2 VCC, ΔVS and ΔVDW are given by the following equations (1) and (2).

[0042]

(Equation 1)

VDW = VCC- (1/2) VCC = (1 /
2) Since it is VCC, the above equation (2) can be expressed as the following equation (3).

[0044]

(Equation 2)

Normally, CS ≒ (1/10) × CD, CDW <<
Each capacitance value is set so that ΔVDW <ΔVS, but if ΔVS can be made very large, even if the digit line is not lowered by the dummy word,
The difference potential transmitted to the sense amplifier is sufficiently ensured. This is to reduce CD / CS as much as possible and to increase the capacitance value CS of the memory cell in the above equation (1) for determining ΔVS. Is the limit to satisfy the relationship between CD and CS.

From the above equations (1) and (2), the difference potential propagating to the sense amplifier is ΔVS + ΔVDW when “H” data is stored in the memory cell and when the “L” data is stored in the memory cell. .DELTA.VS-.DELTA.VDW, and the amount of .DELTA.VDW is added to the difference potential when "H" data is amplified, so that the "H" data sensing operation is more advantageous when there is no dummy word.

This advantage prevents the above-described deterioration of the "H" data sensing operation.

FIG. 9 is a graph showing how the drop amount of the dummy word and the drop amount of the digit line at this time change with respect to the power supply voltage. In FIG. 9, the horizontal axis indicates the power supply voltage VCC, and the vertical axis indicates the digit line drop amount.

Referring to FIG. 9, for example, when the power supply voltage is V1
In this case, the dummy word DWL0 drops by the amount indicated by the symbol ↓, and the amount of the digit line drop at that time is a1 + b1.

Even when the power supply voltage is V2, the dummy word drops by the amount indicated by the symbol ↓, and the amount of drop of the digit line at that time is a2 + b2.

However, the above-mentioned amount of drop of the digit line is obtained when the dummy cells Q40 and Q41 are of the depletion type, and in the case of the enhancement type, they cannot be obtained as much as the above-mentioned amount of drop.

While the depletion type transistor is always on, the enhancement type transistor is turned on only when the voltage between the gate and the source (or drain) becomes higher than the threshold voltage VTN. , Q41 function as capacity
This is when the potential of the dummy word is higher than the threshold voltage VTN with respect to the potential of the digit line.

For this reason, the dummy word has the power supply potential VC.
The range from C to HVCC + VTN, which is a potential higher by VTN than the potential HVCC of the digit line, is a dummy cell Q40 composed of an enhancement transistor.
Q41 is a range that functions as a capacitor.

The drop from HVCC + VTN to HVCC does not contribute to the drop of the digit line since Q40 and Q41 are turned off.

This means that even if the final drop potential of the dummy word is lower than the HVCC potential, the drop amount of the digit line does not change, and the connection of Q40 and Q41 to the dummy word and digit line is shown in FIG. 6, the falling start potential of the dummy word is HVCC +
It must be above VTN.

In other words, the fact that the dummy cell is of the enhancement type means that the dummy word drop starting potential and the final falling potential and the connection of the dummy cell to the dummy word and the digit line are set so that the dummy capacitance is turned on. You have to configure.

The connection of the dummy cell shown in FIG.
The method of supplying a potential to the inverter constituted by the transistors QP0 and QN0 shown in FIG.

When the dummy cells Q40 and Q41 are of the enhancement type, the digit line drop amount is given by the above equation (2).
Thus, it is given by the following equation (4). Here, VTN is the threshold voltage of the transistor.

[0059]

(Equation 3)

The digit line drop amounts ΔVDW1 and ΔVDW2 for the power supply voltages V1 and V2 are expressed by the following equations (5) and (6), respectively.

[0061]

(Equation 4)

In FIG. 9, the amounts are a1,
a2.

The capacity of the dummy word drop amount as Q
ΔVDW is also reduced by the amount by which VTN is capable of functioning by 40 and Q41 by VTN, and the reduced amount corresponds to b1 and b2 shown in FIG. 9 when VCC is V1 and V2.

[0064]

When the arsenic PR process is reduced, the transistors forming the dummy cells are changed from the depletion type to the enhancement type. As described above, the amount of drop of the digit line by the dummy word is determined by the threshold value. Referring to FIG. 9, when the power supply voltage VCC is at V1, the ratio of the decrease to the originally expected drop of the digit line is represented by b1 /
In the case of (a1 + b1) and V2, the ratio becomes b2 / (a2 + b2), and the lower the power supply voltage VCC, the higher the ratio. As is clear from FIG. 9, the power supply voltage VC
If C is lowered to a certain value, the digit line will not drop at all even if the dummy word drops.

Therefore, the lower the power supply voltage VCC becomes, the smaller the difference potential VS + ΔVDW propagated to the sense amplifier at the time of sensing the “H” data from the memory cell becomes.

Therefore, the sensing operation is deteriorated by the fluctuation of the power supply voltage VCC or the α-ray from the resin, which is prevented by the dummy word, and the state that the sense cannot be performed easily occurs when the power supply voltage VCC is low, and the stability is reduced. Memory operation cannot be guaranteed.

Considering that the inside of the device is operated at a low voltage of, for example, 3.3 V, the decrease of the digit line drop due to the threshold voltage VTN is equal to the originally expected digit line drop amount. It looks big against.

When the capacity of the dummy cell is increased, the drop amount of the digit line is increased according to the above equation (4).
When the power supply voltage VCC is low, there is no problem. However, when the power supply voltage VCC is high, the difference potential transmitted to the sense amplifier at the time of sensing "L" data from the memory cell cannot be sufficiently obtained. That is, ΔVDW increases and VS−ΔVDW decreases.

Therefore, the present invention has been made in view of the above circumstances, and an object of the present invention is to prevent the dynamic random access memory from deteriorating the operation of sensing high data when the power supply voltage is low, for example. An object of the present invention is to provide a semiconductor memory device for preventing such a situation.

[0070]

In order to achieve the above object, a semiconductor memory device according to the present invention comprises a dummy line which is paired with a digit line to which a memory cell is connected before starting a sensing operation. A semiconductor memory device having function means for lowering a word from one potential to another potential and thereby lowering the potential of the digit line by an amount corresponding to a drop amount of the dummy word by capacitive coupling, comprising: When the power supply voltage is high, the drop amount of the dummy word is set to be small, and when the power supply voltage is low, the drop amount of the digit line is set to be large.

According to the present invention, when the power supply voltage VCC is high, the amount of drop of the dummy word is set small, and the amount of drop of the digit line when the power supply voltage is low can be increased.

According to the present invention, there are provided first and second potential generating circuits having characteristics different from each other with respect to a power supply voltage, wherein the first potential generating circuit generates a first potential corresponding to a half of the power supply voltage. And a second potential generation circuit that generates a second potential having a characteristic that is more dependent on the power supply voltage than the first potential, and generates the second potential and the second potential. A comparison circuit that detects a potential difference between the potentials and outputs one of the first potential and the second potential.

Further, in the dummy word generating circuit conventionally used, the dummy word is generated with the potential output from the comparing circuit as the final drop potential and the power supply voltage as the drop starting potential.

Further, it is possible to control the dependency of the second potential on the power supply voltage and the power supply voltage at which the first potential and the second potential are equal to each other by the first resistor and the second resistor. I do.

[0075]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of the first embodiment of the present invention, and shows a process until a dummy word is generated.

In FIG. 1, first potential generation circuit 101
Consists of a 1/2 VCC generation circuit which is widely used at present, and outputs a first potential (HVCD) which is an HVCC potential. The second potential generating circuit 102 has a voltage of 1/2 VCC
The second potential (H
VVT0).

The comparison circuit 103 supplies the first potential (HVC
D) and the second potential (HVVT0),
One of T0 and HVCD is output as HVVT. The comparison circuit 103 is configured to output the second potential (HVVT0) as the HVVT when the power supply voltage VCC is higher than a predetermined value, and output the first potential (HVCD) when the power supply voltage VCC is lower than the predetermined value.

Dummy word generating circuit 104 generates dummy words DWL0 and DWL1 based on the power supply voltage and HVVT output from comparison circuit 103.

FIG. 2 is a diagram showing a circuit configuration of the dummy word generating circuit 104 according to the embodiment of the present invention. Referring to FIG. 2, the configuration of dummy word generating circuit 104 is as follows.
The configuration is basically the same as that of the prior art shown in FIG. 8, and the output HVVT of the comparison circuit 103 shown in FIG. 1 is replaced with the N-channel MO of the inverter instead of the HVCD in FIG.
S transistor (Nch transistor) QNO, Q
The only difference is that an input is made to the source of N1. The operation principle of generating the dummy words DWL0 and DWL1 is the same as that of the above-described prior art.

The drop start potential of the dummy word is the power supply voltage,
Assuming that the final drop potential is HVVT, the dummy word falls in a range of a potential equal to or higher than HVCC which is the precharge potential of the digit line.

Since the operation of the dummy word is the same as that of the prior art, the method of connecting the dummy cell to the dummy word and the digit line is the same as that shown in FIG. That is, the configuration of the sense amplifier and the memory cell can be exactly the same as that of the prior art shown in FIG.

Referring to FIG. 2, dummy words DWL0,
Since DWL1 drops from the power supply voltage VCC to HVVT, the amount of the drop is VCC-HVVT. Less than,
The relationship with the digit line drop amount will be described.

FIG. 5 shows the power supply voltage and the dummy word drop amount,
And the relationship between the amount of drop of the digit line. In FIG. 5, the one-dot chain line indicates the characteristic of the first potential HVCD output from the first potential generating circuit 101, and the two-dot chain line indicates the characteristic of the second potential HVVT0 output from the second potential generating circuit 102. Is shown. HVVT is an output of the comparison circuit 103. As shown by a bold line in the figure, when the power supply voltage VCC is higher than a certain voltage value, it becomes the same potential as the second potential HVVT0, and when lower, the first potential HVCD. And the same potential.

That is, the first potential HVCD and the second potential HVVT0 are equal to each other when the power supply voltage VCC is equal to VREF, and when the power supply voltage VCC is equal to or higher than VREF, the comparison circuit 103
Output HVVT becomes HVVT0, and becomes HVCD when the power supply voltage VCC is lower than VREF.
Therefore, the amount of drop of the dummy word is VCC-HVVT0 (7) when the power supply voltage VCC is equal to or higher than VREF and VCC-HVCD (8) when the power supply voltage VCC is equal to or lower than VREF.

As in the prior art described above, the power supply voltage VC
Assuming that the voltage at which C is higher than VREF is V1 and the voltage at which the level is lower than VREF is V2, the respective dummy word drops at V1 and V2 are V1-HVVT0 (9) V2-HVCD = 1 / 2 × V2 (∵HVCD = １ ／ × V2) (10), which corresponds to the size indicated by the symbol ↓ in FIG.

When the power supply voltage VCC is V2, the amount of dummy word drop is the same as that of the prior art, but V1
In the above prior art, VCC-H
Since the drop amount is the VCD, the drop amount is reduced by the amount of HVVT0-HVCD (11) as compared with the above-described conventional technology.

Since the drop amount of the dummy word, which can actually function as the capacitive coupling, decreases by the VTN of the transistor which is a dummy cell,
VCC-HVVT-VTN, and when the power supply voltage VCC is V1, V1-HVVT0-VTN (12) When the power supply voltage VCC is V2, it becomes 1 / 2V2-VTN (13).

Accordingly, the actual digit line drop amount is:
When the power supply voltage VCC is V1, ΔVDW1 ′ is obtained, and when the power supply voltage V2 is ΔVDW2 ′, the following equation (14) is obtained from the above equation (4).
Given by (15).

[0090]

(Equation 5)

In FIG. 5, the value of the above equation (15) is a2
And the value of the digit line drop is equivalent to that of the prior art, but the value of the above equation (14) corresponds to a1 ', which is smaller than the value of the conventional digit line drop a1.

For this reason, when the power supply voltage VCC is equal to or lower than VREF, the same digit line drop amount as that of the above-described prior art can be obtained with the same dummy word drop amount as that of the above-mentioned prior art, but the power supply voltage VCC becomes lower. When the voltage is equal to or more than VREF, the amount of dummy word drop is smaller than that of the above-described related art, so that the amount of digit line drop is smaller than that of the above related art.

Therefore, if the amount of drop of the digit line when the power supply voltage VCC is high is made equal to that of the prior art by increasing the capacitance value of the dummy cell capacitance, for example, the drop of the digit line when the power supply voltage VCC is low is obtained. The amount is larger than that of the above-mentioned prior art by an amount corresponding to the increase in the capacitance value. Since the capacity of the dummy cell is determined by the size of the transistor, it is possible to increase the capacity of the dummy cell by increasing the channel width.

Next, as an embodiment for specifically explaining the present invention, a specific example of preparing an HVVT having characteristics as shown in FIG. 5 will be described.

FIG. 3 shows a second embodiment of the present invention.
1 shows an example of the circuit configuration of the potential generation circuit 102 of FIG. FIG. 4 shows an example of a circuit configuration of the comparison circuit 103.

Referring to FIG. 3, second potential generating circuit 1
Reference numeral 02 denotes a 1/2 VCC generating circuit 31, a diode-connected transistor Q70 and a resistor R1 inserted between the 1/2 VCC level generating circuit 31 and the power supply terminal VCC, and a ground terminal GND and the 1/2 VCC generating circuit 31. And a resistor R2 is connected between them. In this configuration, instead of using the generally used 1/2 VCC generating circuit 31 to supply the power supply voltage VCC directly as the power supply potential, the transistor Q70 is clamped (threshold) via the transistor Q70 and the resistor R1. Value voltage) VTN and resistance R1
And a potential VCH obtained by subtracting the voltage drop from the power supply voltage VCC. On the ground voltage (GND) side, a potential VCL corresponding to a voltage increase by the resistor R2 is applied from GND via the resistor R2.

Since HVVT0 is used as a potential for determining the amount of drop of the dummy word, it is necessary to always generate a constant potential like HVCD. Therefore, 1 /
Based on the 1/2 VCC generation circuit 31, which is used to always stably supply the potential of 2 VCC, the above-described configuration is used to obtain desired characteristics.

First, the transistor Q70 has the gate short-circuited to the drain VCC, thereby lowering the power supply input to the 発 生 potential generation circuit 31 from the power supply voltage VCC by the clamp VTN, and outputting the voltage. HV
Make it lower than CD. In addition, this corresponds to making the power supply voltage VCC at which HVVT0 is equal to or higher than the GND level equal to or higher than VTN, and in FIG.
This is equivalent to translating by VTN in the direction in which C is positive. This operation is called “offset”.

If two or three transistors are stacked vertically instead of one transistor and clamped, the offset can be doubled and tripled.

Next, the resistor R2 is indispensable for increasing the dependency of HVVT0 on the power supply voltage VCC, and corresponds to making the slope of HVVT0 larger than HVCD in FIG.

The reason why the slope becomes larger than HVCD is that HVCD is always output with reference to "ground potential", whereas HVVT0 is output with reference to "potential rise due to resistor R2". by. That is, when the power supply voltage VCC increases, the “reference” VCL
Is also increased.

The resistance R1 is equal to the power supply voltage V of the supplied power supply.
It may be used to control CC dependency,
It is a necessary condition that the resistance value is small with respect to the resistance R2.

If the resistance value of the resistor R1 is larger than that of the resistor R2, the dependency of the voltage drop on the power supply voltage VCC becomes small, and as a result, the dependency of the HVVT0 on the VCC rather than the HVCD becomes small. The degree becomes small. It is the resistor R2 that controls the power supply voltage VCC dependency, and the resistor R1 is complementary.

From the offset amount and the magnitude of the inclination, HVV
T0 is the power supply voltage V, as shown in FIG.
At a certain value of CC, the same potential as HVCD, that is, 1
/ 2VCC potential. The value of the power supply voltage VCC is VREF shown in FIG. 5, and is the intersection of HVVT0 and HVCD. When the power supply voltage VCC is equal to or higher than VREF and HVVT
0 has a higher potential than HVCD.

Here, the output HVVT0 is connected to the resistors R1, R
2 and the threshold voltage VTH of the transistor Q70.

The output HVVT0 is 1 as shown in FIG.
Since these are the outputs of the power supplies VCH and VCL supplied to the / 2VCC generation circuit 31, they are given by the following equation (16). HVVT0 = (VCH + VCL) / 2 (16)

The characteristic that HVVT0 has the characteristic according to the above equation (16) is accompanied by the condition that VCC ≧ VTH (17) because at least the transistor Q70 must be turned on. This corresponds to the offset.

Assuming that the resistance of the 1/2 VCC generating circuit 31 is R, the current I flowing into the 1/2 VCC generating circuit is given by the following equation (18).

VCH and VCL are as follows: VCH = VCC−VTH−R1 × I (19) VCL = R2 × I (20) The above equation (18) is substituted into the following equation (21). ,
(22) is derived.

[0110]

(Equation 6)

By substituting the above equations (21) and (22) into the above equation (16), HVVT0 is expressed by the following equation (23).

[0112]

(Equation 7)

In order to make the dependency of HVVT0 on the power supply voltage VCC larger than HVCD, the above equation (2)
Since the VCC coefficients of 1) and (22) need only be larger than 1/2, it is sufficient to set R1 <R2 (24).

In this manner, the necessary condition between the resistors R1 and R2 is obtained as a mathematical expression.

In order for HVCD and HVVT0 to have the same potential at the power supply voltage VCC = VREF, the above equation (2)
If the left side of 3) is 1 / VREF and the right side VCC is VREF, the following equation (25) is derived.

[0116]

(Equation 8)

Since VREF must have a positive value,
A condition similar to the above equation (24) is required between the resistors R1 and R2.

From this equation, it can be said that the clamp of the transistor Q70 is necessary for HVVT0 and HVCD to have an intersection at a certain power supply voltage.

From the above equations (23) and (25), the equation (2)
If the resistors R1 and R2 satisfy the condition of 4), H
Dependence of VVT0 on the power supply voltage VCC, that is, HVVT0
And VREF, which is at the same potential as HVCD, is connected to a resistor R1,
The optimum value can be controlled by R2.

For example, when it is necessary to increase the VREF value and the VCC dependency, the resistance value of the resistor R2 may be made much larger than that of the resistor R1.

When the power supply voltage VCC is equal to or lower than VREF in the above equation (25), the first potential HVC
D is HVVT which is the second potential when it is equal to or higher than VREF.
FIG. 4 shows a circuit configuration of the comparison circuit 103 which selects and outputs 0. As described above, the function of the comparison circuit 103 is as follows.
When the power supply voltage VCC is higher than VREF, HVVT0
HVCD is output when it is low.

For this reason, first, the magnitude relationship between HVCD and HVVT0 is compared, and based on the comparison result, HVCD or HVT0 is compared.
What is necessary is just to output one of VVT0.

Referring to FIG. 4, comparison circuit 103 includes an HV
An Nch transistor QN1 having CD as a gate input;
Nch transistor QN2 having VVT0 as a gate input
A current mirror circuit (comprising Pch transistors QP1 and QP2) having an input terminal connected to the drain of QN1 and an output terminal connected to the drain of QN2,
Nch transfer gate Q80 connected between HVCD and output terminal HVVT, HVVT0 and output terminal HVVT
And an Nch transfer gate Q81 connected between the transfer gates Q80 and Q81.
The output of the comparator (the connection point VF between the transistor QN2 and the output terminal of the current mirror circuit) and the signal inverted by the inverter are connected.

The potential difference between HVVT0 and HVCD is detected by the current mirror circuit, and the output is a signal indicating the magnitude relationship between the two. That is, HVCD is HVVT0
When the potential is higher than the node VF, the node VF is at the "H" level, and when the HVCD is at a potential lower than the HVVT0, the node VF is at the "L" level.

Using this VF, HVVT0, HVCD
Transistors Q80 and Q81 are transfer gates and their drains are HVC
D, HVVT0 and each gate has a contact VF
From HV, each source is HV
VT configuration.

Since the magnitude relationship between the power supply voltages of HVVT0 and HVCD is as described above, the power supply VCC is set to VREF.
In the following cases, HVCD is higher than HVVT0, so that the transistor Q80 is turned on and Q81 is turned off.
Is lower than HVVT0, the logic configuration may be such that the transistor Q80 is off and the transistor Q81 is on.

Accordingly, as shown in FIG. 4, if the potential obtained by inputting VF directly to the gate of the transistor Q80 and VF to the gate of the transistor Q81 is applied to the inverter, the power supply voltage VCC becomes lower than VREF. At this time, the transistor Q80 is turned on by the comparison result signal VF of "H", HVCD is output as HVVT, and the power supply voltage VC
When C is equal to or higher than VREF, the transistor Q81 is turned on by VF which becomes "L", and HVVT0 is output as HVVT.

With this configuration, the intersection of HVVT0 and HVCD, that is, the VCC where the power supply voltage VCC = VREF in FIG. 5 becomes the power supply voltage value at which the potential of the node VF changes. HVC
Transistors QP1, QN1, QP so that D switches
2, QN2 is set to increase the sensitivity of the current mirror, or the waveform of the comparison result signal VF is shaped via an inverter so that the intermediate potential is increased by transistors Q80 and Q80.
It is only necessary to take measures as necessary to prevent the situation from being given to 81.

The potentials of HVCD and HVVT0 are
The size of the transistors Q80 and Q81 acting as transfer gates may be increased as necessary so that the voltage is sufficiently supplied to the HVVT.

Assuming that HVVT is the final drop potential of the dummy word as shown in FIG. 2, the drop amount of the dummy word is lower than VCC-HVVT0 (25) VREF when VCC is higher than VREF. In this case, it is possible to set VCC-HVCD = １ ／ VCC (26).

[0131]

As described above, according to the present invention,
Since the amount of dummy word drop when the power supply voltage is high can be made smaller than that of the conventional example without changing the amount of dummy word drop when the power supply voltage is low, the amount of digit line drop when the power supply voltage is high When the power supply voltage is low, the amount of drop of the digit line becomes larger by the increase.

For example, if the increased amount is realized by increasing the capacitance value of the dummy cell capacitance, it will be larger than the conventional case by the increased capacitance value of the dummy cell capacitance. Therefore, even if the dummy capacitance is formed by an enhancement type transistor, the decrease in the amount of drop of the digit line due to the threshold voltage can be compensated for by the above increase, and the capacitance is formed by the depletion type transistor. As a result, the same digit line drop amount can be obtained. As a result, when the power supply voltage is low, the sensing operation when "H" data is stored in the memory cell is improved as compared with the conventional case.

In the present invention, it is possible to control the power supply voltage for switching the magnitude of the drop amount of the dummy word and the dependence of the dummy word drop amount on the power supply voltage when the power supply voltage is high by the resistance value. Therefore, there is an advantage that it is possible to obtain the required amount of the digit line drop with high accuracy.

[Brief description of the drawings]

FIG. 1 is a diagram for describing an embodiment of the present invention, and is a block diagram of a circuit that generates a dummy word.

FIG. 2 is a diagram showing a circuit configuration of a dummy word generation circuit according to the embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a second potential generating circuit according to an embodiment of the present invention, which generates a potential different from VCC depending on a 1/2 VCC generating circuit.

FIG. 4 shows a first potential and a second potential according to the embodiment of the present invention.
FIG. 3 is a diagram illustrating a circuit configuration of a comparison circuit that compares and outputs the potentials of FIG.

FIG. 5 is a diagram showing a dummy word drop amount and a digit line drop amount with respect to a power supply voltage in the embodiment of the present invention.

FIG. 6 is a diagram showing a configuration of a sense amplifier, a memory cell, and a dummy cell.

FIG. 7 is a signal waveform diagram illustrating a sensing operation.

FIG. 8 is a diagram showing a configuration of a conventional dummy word generation circuit.

FIG. 9 is a diagram showing a conventional dummy word drop amount and a digit line drop amount with respect to a power supply voltage.

[Explanation of symbols]

Reference Signs List 101 First potential generation circuit 102 Second potential generation circuit 103 Comparison circuit 104 Dummy word generation circuit Q00 to Q80, Q01 to Q81, QN0, QN1 N-channel MO
S-transistor Q10, Q11, QP0, QP1 P-channel MOS transistor C00, C01 Memory cell R1, R2 Resistance D, DB Digit line pair VCC Power supply voltage GND Ground voltage VTN Threshold voltage of N-channel MOS transistor

Claims (8)

(57) [Claims] In a digit line paired with a digit line to which a memory cell is connected, a dummy word is dropped from a power supply potential to a final drop potential before starting a sensing operation, so that the dummy word is capacitively coupled. What is claimed is: 1. A semiconductor memory device comprising: a function unit for lowering the potential of said digit line by an amount corresponding to a word drop amount, wherein a first potential for generating a first potential corresponding to approximately 1/2 of a power supply voltage is provided. Generating means, a second potential generating means for generating a second potential by a circuit for generating a half voltage by using a voltage lower by a predetermined clamp voltage than the power supply voltage as a high potential side power supply, 1 compares the magnitude of potential and the second potential, and comparison means for outputting one of the first potential or the second potential based on the comparison result, selects a predetermined address signal It said of the dummy word that is most
The final falling potential is determined by the first or the second output from the comparing means.
And a means for setting a second potential . 2. The semiconductor memory device according to claim 1, wherein said clamp voltage is determined by a threshold voltage of a transistor. 3. In a digit line paired with a digit line connected to a memory cell, a dummy word is dropped from a drop start potential to a final drop potential before a sensing operation is started, so that the capacitive coupling is performed. A semiconductor memory device having function means for lowering the potential of said digit line by an amount corresponding to a drop amount of a dummy word, wherein said semiconductor memory device generates a first potential corresponding to approximately 電源 of a power supply voltage.
1 potential generating means, and the dependency on the power supply voltage is greater than the first potential.
Potential generating means for generating a second potential having a characteristic
And the first and second potential generating means output from the first and second potential generating means.
Comparing the first and second potentials, and based on the comparison result,
A comparing means for outputting the first potential or the second potential, and a descent start potential of the dummy word as a power supply potential,
The final drop potential of the dummy word is determined by the output potential of the comparing means.
And a dummy word generating means . 4. A digit line to which a memory cell is connected.
In the digit line paired with
Before starting, set the dummy word from the power supply potential to the final drop potential.
The dummy word is
The potential of the digit line is lowered by an amount corresponding to the amount of drop.
The power supply voltage is high, and
When the power supply voltage is low,
Do not increase the amount of digit line drop
Semiconductor memory device , comprising first and second potential generating circuits having characteristics different from each other with respect to a power supply voltage, wherein the first potential generating circuit has a first potential corresponding to approximately 略 of the power supply voltage. A circuit for generating a potential, wherein the second potential generating circuit generates a second potential having a characteristic that is more dependent on the power supply voltage than the first potential, and wherein the first potential and the second potential are generated. 2 by comparing the magnitudes of the potentials.
A comparison circuit that outputs one of the first potential and the second potential based on the comparison result. The comparison circuit outputs the potential output from the comparison circuit
A semiconductor storage device , wherein the final drop potential of the word is the final drop potential . 5. The power supply voltage of the first potential generation circuit is clamped by at least one MOS transistor based on the first potential generation circuit. A voltage stepped down by the first resistor is used as a high-side power supply, and a voltage obtained by boosting the ground potential with respect to the ground voltage by a second resistor having a larger resistance value than the first resistor is used as a low-side power supply. 5. The semiconductor memory device according to claim 4 , wherein: 6. The second potential generation circuit has a predetermined power supply voltage value (Vref) such that the second potential and the first potential are equal to each other, and is dependent on the power supply voltage. 6. The semiconductor memory device according to claim 5, wherein a temperature and said predetermined power supply voltage value are controlled by said first resistance and said second resistance. 7. The circuit according to claim 1, wherein the comparing circuit is configured to control the first potential and the
Comparing the magnitude of the second potential, outputting the first potential when the power supply voltage is lower than the predetermined power supply voltage value, and outputting the first potential when the power supply voltage is higher than the predetermined power supply voltage value. 7. The semiconductor memory device according to claim 6, wherein the second potential is output. 8. The method according to claim 1, wherein the potential at which the dummy word starts to fall is a power supply voltage,
8. The semiconductor memory device according to claim 7, wherein a dummy word is generated by using a final drop potential as a potential output from said comparison circuit.