JP3185401B2 - Variable gain circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable gain circuit for generating a burst signal used in a high frequency circuit for digital communication.

[0002]

2. Description of the Related Art In recent years, digital communications that are excellent in secrecy, user accommodating capacity, cost, miniaturization of mobile devices, and support for various services have been adopted in mobile communications. In digital communication, a variable gain circuit is used to control the output power when the burst signal rises and falls, and to monitor the output power and fine-tune the output power to the set power. Hereinafter, a conventional gain variable circuit will be described with reference to the drawings.

FIG. 3 is a block diagram showing a conventional variable gain circuit. In FIG. 3, 1 is an input terminal, 2 is an output terminal, 3 is a dual gate field effect transistor,
4 and 5 are matching circuits, 6 is a burst waveform generating circuit, 9 is a drain power supply, 10 is a first gate terminal (G1), 11 is a second gate terminal (G2), 12 is a drain terminal (D), and 13 is a source. Terminal (S),
14 is a gate bias power supply.

The operation of the variable gain circuit configured as described above will be described below.

The signal input to the input terminal 1 passes through the matching circuit 4 and is input to the first gate terminal (G1) 10 of the dual gate field effect transistor 3. This signal is amplified by the dual gate field effect transistor 3 and the drain terminal
From (D) 12, the signal is output from the output terminal 2 through the matching circuit 5. A constant bias voltage is applied to a first gate terminal (G1) 10 of the dual gate field effect transistor 3 from a gate bias power supply 14, and a burst waveform generation circuit is applied to a second gate terminal (G2) 11 of the dual gate field effect transistor 3. 6
The gain can be varied by controlling the bias voltage according to the more necessary gain.

FIG. 4 shows a characteristic of a gain change when the first gate bias voltage of the variable gain circuit of FIG. 3 is kept constant and the second gate bias voltage is changed. From FIG. 4, the first gate terminal (G1) of the dual gate field effect transistor 3
10 bias voltage (Vg1) fixed, 2nd gate terminal (G2) 1
The gain is changed by changing the 1 bias voltage (Vg2). In the case of performing burst transmission in digital communication, unless the output power is raised or lowered at a fixed rate, the spectrum spreads and an adjacent channel is disturbed. For this purpose, a dual-gate field-effect transistor 3 is used to perform voltage control in which the second gate bias voltage is gradually increased in accordance with the rise time.

Further, in order to vary the transmission output power, the output power is varied by changing the variable width of the second gate voltage. That is, when the output power is large, a large gain A point is obtained by increasing the second gate bias voltage (Vg2) to 3.0 V, and the output power is increased. When the output power is small, set the second gate bias voltage (Vg2) to 2.5
V, 2.0 V, and the output power is reduced by controlling the gain up to the points B and C. Thus, according to the output power,
A voltage is applied to the second gate terminal (G2) 11 from the burst waveform generation circuit 6 which stores all rising and falling data in the ROM and performs DA conversion.

[0008]

However, in the above configuration, the control voltage of the second gate for controlling the gain needs to have different waveform change patterns in accordance with the output level of the burst signal. Therefore, there is a problem that the storage capacity of the control voltage data is increased.

SUMMARY OF THE INVENTION In view of the above problems, the present invention provides a circuit for generating a burst signal output level setting voltage and a circuit for generating a burst signal waveform change pattern having a fixed output level by using separate gates to vary the gain. An object of the present invention is to provide a variable gain circuit having a small storage capacity for control voltage data because control can always be performed with the same storage data regardless of output power.

[0010]

In order to solve the above problems, a variable gain circuit according to the present invention is connected to a first gate terminal of a dual gate field effect transistor and generates an output level setting voltage of a burst signal. An output level setting circuit, and a second gate of the dual gate field effect transistor
A burst waveform generating circuit connected to the gate terminal for generating a control voltage pattern for a change in the waveform of the burst signal; a fixed output level control voltage pattern generated by the burst waveform generating circuit; and an output level of the output level setting circuit The configuration is such that the waveform of a burst signal having an arbitrary output level is controlled by a combination of set voltages.

[0011]

According to the present invention, a burst signal output level setting voltage is generated at the first gate of the dual gate field effect transistor by the first gate of the dual gate field effect transistor, and the output level is fixed at the second gate of the dual gate field effect transistor. By generating one type of voltage change pattern from the change pattern and controlling the waveform of the burst signal of an arbitrary output level, control can always be performed with the same stored data.
The variable gain operation is facilitated, and a variable gain circuit with a small data storage capacity can be realized.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a variable gain circuit according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a variable gain circuit according to one embodiment of the present invention. In FIG. 1, 7 is a gate voltage setting circuit, and 8 is an output level setting circuit. In addition, the same components as those in FIG. 3 are denoted by the same reference numerals.

The operation of the variable gain circuit configured as described above will be described below.

The signal input to the input terminal 1 passes through the matching circuit 4 and is input to the first gate terminal (G1) 10 of the dual gate field effect transistor 3. This signal is amplified by the dual gate field effect transistor 3 and the drain terminal
From (D) 12, the signal is output from the output terminal 2 through the matching circuit 5. The gate voltage is set by the gate voltage setting circuit 7 according to the output level set by the output level setting circuit 8, and the first gate terminal (G1) of the dual gate field effect transistor 3 is set.
Voltage is applied to 10. Further, a burst waveform generating circuit 6 for generating a time-varying control voltage having a constant maximum voltage change width is provided with a dual gate field effect transistor 3.
To the second gate terminal (G2) 11 to vary the second gate voltage.

FIG. 2 shows a characteristic of a gain change when the gain is changed by the second gate bias voltage of the gain variable circuit and the variable width of the gain is changed by the first gate bias voltage. FIG.
Therefore, the variable gain control voltage is changed at a constant width by the bias voltage (Vg2) of the second gate terminal (G2) 11, and the first gate terminal
(G1) The output power value is varied by fixing and switching the value of the bias voltage (Vg1) of 10. That is, when the output power is large, the first gate bias voltage (Vg1) is set to 1.0
By switching to V (curve (A)), a large gain A point is obtained, and the output power is increased. When the output power is small, the first gate bias voltage (Vg1) should be 1.5V, 2.0V (curve
By switching to (a) and (c)), the gain can be controlled from point B to point C, and the output power is reduced.

As described above, by varying the control voltage of the variable gain within a certain range irrespective of the output power, the burst waveform at the time of rising and falling of the burst signal is always controlled by the same waveform, and the burst waveform is generated by the burst waveform generating circuit. A voltage is applied to the second gate terminal.

[0017]

As described above, in the variable gain circuit according to the present invention, the set voltage of the burst signal output level is generated at the first gate of the dual gate field effect transistor, and the output level is set at the second gate of the dual gate field effect transistor. By generating one type of voltage change pattern from the fixed burst signal waveform change pattern and controlling the burst signal waveform of an arbitrary output level, the variable gain operation can be easily performed, and the variable gain with small data storage capacity can be achieved. A circuit can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram of a variable gain circuit according to an embodiment of the present invention.

FIG. 2 is a characteristic diagram of a variable gain circuit for explaining the operation of FIG. 1;

FIG. 3 is a block diagram of a conventional gain variable circuit.

FIG. 4 is a characteristic diagram of the variable gain circuit of FIG. 3;

[Explanation of symbols]

3 ... Dual gate field effect transistor 6 ... Burst waveform generation circuit 7 ... Gate voltage setting circuit 8 ...
Output level setting circuit, 10: first gate terminal, 11: second
Gate terminal, 12 ... drain terminal, 13 ... source terminal.

────────────────────────────────────────────────── ─── Continuation of the front page (72) Yoshimo Yoshikawa, Inventor 1006 Kazuma Kadoma, Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References JP-A-4-95424 (JP, A) JP-A-1 JP-A-105609 (JP, A) JP-A-63-76607 (JP, A) JP-A-62-278812 (JP, A) JP-A-2-206212 (JP, A) JP-A-49-25386 (JP, B1) (58) Fields surveyed (Int. Cl. ⁷ , DB name) H03G 1/00-3/18

Claims (1)

(57) [Claims] An output level setting circuit connected to a first gate terminal of the dual gate field effect transistor for generating an output level setting voltage of a burst signal; and a burst signal connected to a second gate terminal of the dual gate field effect transistor. A burst waveform generating circuit that generates a control voltage pattern of the waveform change of the above, and a combination of a control voltage pattern having a fixed output level generated by the burst waveform generating circuit and an output level setting voltage of the output level setting circuit. A gain control circuit for controlling the waveform of the burst signal having the output level of (i).