JP3184616B2 - Image processing method and apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing method and apparatus, and more particularly to an image processing method and apparatus capable of improving the resolution of binary image data, for example, an image output apparatus such as a digital printer and a digital facsimile. The present invention relates to an image processing method and apparatus suitable for processing.

[0002]

2. Description of the Related Art Image output apparatuses, such as digital printers and digital facsimile machines, have two points of view in terms of economy and stability.
Value output (ie, "black" or "white" output) devices are most common. In order to output an image having a gradation (gray level) with such a binary output device, pseudo halftone processing (Pseudo-halfton) described below is required.
e processing is required.

[0003] The most representative method that has been used in the past is the dither method (Dither Method). In this dither method, an m × n (m, n is a natural number) dither matrix is prepared, and a multiplied matrix is input. Value data (Multiv
value is compared with a threshold value in a corresponding matrix element to perform a binary measurement to form an m × n binarized block, thereby reproducing a halftone image in a pseudo manner. is there.

However, in the dither method, the number of gradations that can be expressed is limited to (m × n + 1), and the resolution is not good.

On the other hand, in 1975, Floyd and S
"AnAdaptive A" by terinberg
lgorithm for Special Gray
scale ", 1975 SID International
online Symposium Digest of
An error diffusion method (Error Diffusion) proposed in a paper called Technical papers.
Method) is a method that is superior to the dither method in both resolution and gradation, and is a method that has recently received special attention.

In the error diffusion method, binarization is performed using a fixed threshold value, and a diffusion error (Di)
The difference between the corrected density obtained by adding the FUSION ERROR and the binarized density (for example, “white” = 0 and “black” = 255 when the density is represented by 8 bits) is a new error. It diffuses forward.

[0007]

However, in a reproduced image obtained by a pseudo halftone processing method such as the above-mentioned error diffusion method, the granularity of a low density region (highlight portion) which the human eye is most sensitive to. (Graininess)
However, it is annoying and hinders improvement in image quality.

Although the granularity decreases as the resolution of the output device increases, the page memory increases in a page printer or the like having a page memory for one page due to the improvement in resolution, and the cost increases.

For example, if the resolution in the main scanning direction is doubled, a double page memory is required, and if the resolution is double in the main scanning and sub-scanning directions, a quadruple page memory is required.

[0010]

SUMMARY OF THE INVENTION The object of the present invention is to eliminate the above-mentioned drawbacks of the prior art. In a reproduced image by the pseudo halftone processing method, a low density range (high level) which the human eye is most sensitive to. It is an object of the present invention to provide an image processing method and apparatus for preventing a write portion from becoming grainy and obtaining a high-quality reproduced image with less graininess without increasing the page memory.

That is, according to the present invention, there is provided an image processing method for inputting multi-valued image data and reproducing and outputting an image having shading, comprising: an inputting step of inputting multi-valued image data; A binarizing step of binarizing the multi-valued image data input by the error diffusion method, and a detecting step of detecting a pixel serving as an isolated point in the binary image data binarized by the binarizing step. A conversion step of dividing the information of the pixel at the isolated point detected by the detection step into a plurality of pixels and outputting the divided pixels; and an output step of outputting a grayscale image based on the output of the conversion step.

This makes it possible to obtain a high-quality binary image with less graininess.

Further, according to the present invention, it is possible to obtain a high-quality reproduced image with reduced granularity in a low density region (highlight portion) without increasing the page memory.

Further, according to the present invention, there is provided an image processing apparatus for inputting multi-valued image data and reproducing and outputting an image having shading, comprising: input means for inputting multi-valued image data; Binarizing means for binarizing the multi-valued image data input by means of the error diffusion method, and detecting means for detecting a pixel which becomes an isolated point in the binary image data binarized by the binarizing means. A conversion unit that divides the information of the pixel at the isolated point detected by the detection unit into a plurality of pixels and outputs the divided information; and an output unit that outputs a grayscale image based on the output of the conversion unit.

Further, according to the present invention, the page memory is increased by detecting the low density area of the binarized image and dividing the dots existing in the low density area into higher resolution dots and outputting them. There is an effect that a high-quality reproduced image with less graininess can be obtained without any graininess.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [Explanation of Common Embodiment (FIGS. 1 to 15)] Here, the structure of a binarizing device commonly used in the following five embodiments will be described. This binarization device is a device that binarizes multivalued image information capable of expressing halftone of one page of an output image, and prints out a grayscale image capable of reproducing gradation. When printing dot data in the print output of this apparatus, the scanning direction of a printer head or a laser beam is defined as a main scanning direction, and the transport direction of a print sheet is defined as a sub-scanning direction.

In each of the five embodiments, only components characteristic of each embodiment in the binarizing device will be described.

<Schematic Description of Overall Configuration of Binarization Apparatus (FIG. 1)> FIG. 1 is a block diagram showing a configuration of a binarization apparatus which is a typical embodiment of the present invention.

In FIG. 1, reference numeral 100 denotes a page memory of the controller section, which stores image information for one page of an output image. 160 is a data line having 8 bits (256 gradations)
Is transmitted. Reference numeral 200 denotes an input unit for temporarily storing data sent from the page memory 100. Thereafter, the data is sequentially read out in synchronization with a read clock, and transferred to a subsequent processing unit for processing. As described above, even if data is transferred from the page memory 100 asynchronously with the processing unit, the data is output and processed in synchronization with the clock of the processing unit.

Reference numeral 260 denotes a data line from which multivalued data is output in synchronization with the clock of the subsequent processing unit. The data represents 8-bit density information in the same manner as digital data transmitted through the data line 160. Reference numeral 300 denotes a binarization circuit which performs a binarization process based on information from the data lines 260 and 370, and outputs binary data (ie, "1").
(Black) ”or“ 0 (white) ”) to the data line 360.

Reference numeral 400 denotes a binary data monitoring unit, which is a signal (signal line 360) output from the binarization circuit 300 and a monitoring area (window area) of a binarized pixel around a pixel of interest.
, It is determined whether or not there is a black (“1”) dot therein, and the determination result is transmitted to the signal line 37.
The signal is output to 0 and fed back to the binarization circuit 300. On the other hand, the binary data monitoring unit 400 refers to the monitoring area of the binarized pixel around the pixel of interest (a window area different from the above), and includes a dot that is black (“1”) therein. Is determined, and the determination result is output to a signal line 460.

Reference numeral 500 denotes a resolution conversion circuit,
Based on the data transmitted through 60, data referenced in advance from a table prepared as a quadruple data amount is converted into two bits serially during one clock of a synchronous clock of a preceding processing unit such as the binarization circuit 300. Output. As a result, the resolution of the output data in the main scanning direction at the output unit 600 is doubled.

An output unit 600 actually prints out data on the signal line 560.

Next, a detailed configuration of each part of the binarizing device having the above configuration will be described with reference to the drawings.

<Description of Binarization Circuit 300 (FIGS. 2 to 9)> FIG. 2 is a block diagram showing a detailed configuration of the binarization circuit 300 shown in FIG. In FIG. 2, reference numeral 310 denotes an error diffusion unit which distributes an error component generated by binarization. An adder 320 receives the density signal of the target pixel from the signal line 260, and outputs the sum of the errors distributed to the target pixel position from the error diffusion unit 310 to the signal line 390. Is output to the signal line 395. A comparison unit 330 compares the target pixel density with a fixed threshold value group to determine a range, and outputs a determination signal to a signal line 336. Reference numeral 340 denotes an AND / OR circuit, which outputs a signal line 3 from the comparison unit 330.
Based on the data output to the signal 36 and the data output to the signal line 370 from the binary data monitoring unit 400, a binarized “black” dot inhibition signal is output to the signal line 346.

Reference numeral 350 denotes a binarizing unit which compares the density signal from the signal line 395 with a fixed threshold. However, the signal line 34
The binarization is performed in consideration of the binarization dot prohibition signal from No. 6. The binarized signal has one bit (ie, “1”).
(Black) or “0” (white) signal is output to the signal line 360. The error component generated due to the binarization is output to the signal line 380 and fed back to the error diffusion unit 310.

FIG. 3 is a block diagram showing a detailed configuration of the error diffusion unit 310 of FIG. In FIG. 3, reference numeral 311 denotes an error distribution control circuit, 312 denotes a line memory (FIFO memory) for delaying one line, 313a to 313e denote flip-flops for latching data, and 314a to 314e.
Is an adder.

In this circuit, the error component is
0 is input to the error distribution control circuit 311, and the error component corresponding to the weight coefficient shown in FIG. 4 is input to each adder. That is,
The signal line 381 outputs the 1/8 amount of the error component to the adder 314e.
, The signal line 382 outputs the amount of 1/8 of the error component to the adder 314d, the signal line 383 outputs the amount of 2/8 of the error component to the adder 314c, and the signal line 384 outputs 1/8 of the error component. To the flip-flop 313c, the signal line 385 supplies the amount of 1/8 of the error component to the adder 314a, and the signal line 386
Inputs the amount of 2/8 of the error component to the adder 314b.

The line memory 312 outputs the sum of the errors distributed to the target pixel position in the processing up to the previous time, and inputs the sum to the adder 314a. The addition is performed sequentially, and the sum of the errors accumulated at the target pixel “position” is input to the flip-flop 313 b, and the result is output to the signal line 390.

FIG. 5 is a block diagram showing a detailed configuration of comparison section 330 shown in FIG. In FIG. 5, 331a
331 d are level comparators, and 332 is an AND circuit. The density value of the target pixel is input from the signal line 260, and the (-) terminals of the comparators 331a and 331c,
The signals are input to the (+) terminals of 331b and 331d, respectively. The fixed thresholds “1” and “11” are input to the (+) terminals 331a and 331c, and the fixed thresholds “10” and “20” are input to the (−) terminals 331b and 331d, respectively. And each threshold are compared.

That is, as shown in FIG. 6, when the density value of the target pixel is "0", the comparators 331a and 331c output "1", and the outputs 331b and 331d output "0". If the density value of the target pixel is in the range of “1” to “10”, for example, “5”, only the comparator 331c is “1”.
And the other comparators output “0”. If the density value of the target pixel is in the range of “11” to “20”, for example, “15”, only the comparator 331b is “1”.
And the other comparators output “0”. Finally, if the density value of the target pixel is “21” or more, the comparators 331b and 331d output “1”, and the other comparators output “0”.

Next, the AND circuit 332 is a decoder for the density signal. For example, when the density is "0", the output of the signal line 336a is "1" and the outputs of the signal lines 336b to 336d are "0". Take the value of In the case of another density, a signal as shown in the truth table of FIG. 6 is obtained.

FIG. 7 shows the AND / OR circuit 34 shown in FIG.
FIG. 2 is a block diagram showing a detailed configuration of the 0 ’. FIG. 8 is a truth table corresponding to the output of each signal line of the AND / OR circuit 340 shown in FIG. In FIG. 7, 341a-3
41c is an AND circuit, 342a to 342b are OR circuits,
343 is an inverter. Signal lines 370a, 370b
Is an output from the binary data monitoring unit 400 described later,
From this output signal and the outputs of the comparators 331a to 331d, a binarized dot inhibition signal is generated.

When the data on the signal line 336a is "1", that is, when the density value of the target pixel is "0", the binarized dot is forcibly set to "0" (white). Therefore, OR signal
"1" is output to the signal line 346 through the circuit 342a.

When the density value of the pixel of interest is at a level of "1" to "10", that is, when the data of the signal line 336b is "1",
The window area is monitored to a large size, and if a black dot ("1") already exists, the binarized black dot is forcibly prohibited. That is, when the data of the signal line 370a is "1", the AND circuit 341b is satisfied, and the signal 34 is output via the OR circuit 342a as a binarized dot inhibition signal.
“1” is output to 6. Also, when the data on the signal line 370a is "0" and the data on the signal line 370b is "1", "1" is output via the AND circuit 341c, and similarly "1" is output from the AND circuit 341b. Is done. As described above, the OR circuit 342 is used as the binarized dot inhibition signal.
“1” is output to the signal line 346 via “a”.

When the density value of the pixel of interest is at a level of "11" to "20", that is, when the data of the signal line 336c is "1", the window area is monitored with a small size, and a black dot ("1") has already been obtained. If there is, binarized dots are forcibly prohibited. That is, if the data of the signal line 370a is "1", the AND circuit 341a is satisfied, and the AND circuit 341a is satisfied.
Outputs “1”, and outputs the signal line 3 via the OR circuit 342a.
At step 46, "1" is output as a binarized black dot inhibition signal.

FIG. 9 is a block diagram showing a detailed configuration of the binarizing section 350 shown in FIG. In FIG.
Is a comparator, 353 is a subtractor, 354 is a selector, 355
Is an inverter, and 356 is an AND circuit.

The sum of the density value of the target pixel and the sum of the error signals distributed to the target pixel position is output from the signal line 395 to the comparator 3.
51, and a fixed threshold (“1
27 ″) is also input, and a comparison result between the fixed threshold value and the density value + distribution error of the target pixel is output.

That is, if the density value + distribution error of the target pixel is larger, “1” (black) is output, and if it is smaller, “0” (white) is output and input to one of the AND circuits 356. If the data on the signal line 346 from the AND / OR circuit 340 is “1”, that is, if binarization is prohibited, “0” is input to the AND circuit 356 via the inverter 355. Therefore, the AND circuit 356 is not satisfied, and “0” is output to the signal line 360. On the other hand, the density of the pixel of interest + the distribution error is larger than the fixed threshold value.
If the data of 46 is "0", that is, if the binarization is not prohibited, "1" is output to the signal line 360. Also, the subtractor 35
From 3, the result obtained by subtracting “255” from the data on the signal line 395 is input to the selector 354. The data on the signal line 395 is input to the other input of the selector 354.

As a result of the binarization, the signal line 36
When “1” is output to 0, the output value of the subtractor 353 input to the selector 354 is selected and output to the signal line 380. If “0” is output to the signal line 360,
The data on the signal line 395 is selected from the selector 354 and output to the signal line 380.

<Description of Binary Data Monitoring Unit 400 (FIG. 10)
FIG. 10 shows the binary data monitoring unit 40 shown in FIG.
FIG. 2 is a block diagram showing a detailed configuration of the 0 ’. In FIG. 10, reference numeral 410 denotes a 3-bit input / output FIFO memory capable of storing binary results for three lines, and 420a to 420g.
Is a flip-flop for latching data, and 430 and 440 are OR circuit units. From the memory 410, the binarized data is sequentially input to the flip-flop 420g in synchronization with the clock. Thereafter, data is sequentially shifted to flip-flops 420f to 420a every clock.

On the other hand, as a result of processing by the binarization circuit 300, "1" or "0" is flip-flopped from the signal line 360.
It is input to the MSB side of the flop 420f. Therefore, the output of the flip-flops and flops 420f to 420a is 4 bits.

The flip flop 420a has the structure shown in FIG.
3. _{2 of} (b ₁ ′, b ₂ ′, b ₃ ′, b ₄ ′) shown in FIG.
The digitization results are latched in order from the lower order.

Similarly, four bits (a ₁ ′, a ₂ ′, a ₃ ′, b ₅ ′) shown in FIG. 13 are stored in the flip-flop 420 b, and (b ₁ , b ₇ ,
b ₈ , b ₉ ) are flip-flop 420d
Has 4 bits of (b ₂ , a ₁ , a ₆ , a ₁₁ ), and flip-flop 420e has 4 bits of (b ₃ , a ₂ , a ₇ , a ₁₂ ).
The bit is placed in the flip-flop 420f (b ₄ ,
a ₃ , a ₈ , a ₁₃ ) are the flip-flop 4
In 20g, three bits (b ₅ , a ₄ , a ₉ ) are latched, and three bits (b ₆ , a ₅ , a ₁₀ ) are output from the memory 410.

The OR circuit unit 430 receives 4, 4, 4, 4, and 3 bits from the flip-flops 420c to 420g and 3 bits from the memory 410, respectively. O
The flip-flops 420 a to 42 are provided in the R circuit section 440.
4, 4, 4, 4, 4, and 4 bits are input from 0f.

FIG. 11 is a block diagram showing a detailed configuration of OR circuit section 430 shown in FIG. In FIG.
431 and 432 are OR circuits, respectively.

The OR circuit 431 has a flip-flop 4
3 bits (a ₁ , a ₆ ,
a ₁₁ ) is also 3 bits (a ₂ , a ₇ , a ₁₂ ) of the signal 421 e from the flip flop 420 e and 3 bits (a ₃ , a ₈ , a) of the signal 421 f from the flip flop 420 f ₁₃ ), two bits (a ₄ , a ₉ ) of the signal 421 g from the flip flop 420 g and two bits (a ₅ , a ₁₀ ) of the signal 421 h from the memory 410 are input. And the OR circuit 431
Detects whether there is "1" (black dot) in any one of these inputs.

The OR circuit 432 has four bits (b ₁ , b ₇ , b) of the signal 421c from the flip-flop 420c.
₈ , b ₉ ), the signal 42 from the flip-flop 420d
1 bit (b ₂ ) of 1d, flip-flop 42
1 bit (b ₃ ) of the signal 421 e from 0e, 1 bit (b ₄ ) of the signal 421 f from the flip flop 420 f, 1 bit (b ₅ ) of the signal 421 g from the flip flop 420 g, and the memory 410 Of one bit (b ₆ ) of the signal 421h from the input terminal and the output signal 370a of the OR circuit 431. And O
The R circuit 432 detects whether any one of these inputs has “1” (black dot).

As described above, the OR circuit section 430 detects whether "1" (black dot) exists in the two large and small window areas, and outputs the result to the signal lines 370a and 370b.

FIG. 12 is a block diagram showing a detailed configuration of OR circuit section 440 shown in FIG. In FIG.
441 and 442 are OR circuits, respectively. A ₁ shown in FIG. 12 is a signal 42 from the flip-flop 420d.
This is one bit of 1d, and is output as a signal line 460a. This is also the binary result of the pixel of interest in the binary data monitoring window for resolution conversion.

The OR circuit 441 has 3 bits (a ₁ ′, a ₁ ′) of the signal 421 b from the flip-flop 420 b.
_{a 2 ', a 3')} , 3 bits (b ₁ of the signal 421c from the flip-flop _{420c, b 7, b 8)} , 2 bits of the signal 421d from the flip-flop 420d (b _2, a ₆ ), Three bits (b ₃ , a ₂ , a ₇ ) of the signal 421 e from the flip flop 420 e and three bits (b ₄ , a ₃ , a ₈ ) of the signal 421 f from the flip flop 420 f are input. You. Then, the OR circuit 441 outputs “1” for any one of these inputs.
(Black dot) is detected.

The OR circuit 442 has four bits (b ₁ ', 4b) of the signal 421a from the flip-flop 420a.
b ₂ ', b ₃ ', b ₄ '), flip flop 420b
One bit (b ₅ ′) of the signal 421b from the flip-flop 420c, and one bit of the signal 421c from the flip-flop 420c.
Bit (b ₉ ), one bit (a ₁₁ ) of the signal 421 d from the flip-flop 420 d, and one bit (a) of the signal 421 e from the flip-flop 420 e
₁₂ ), the signal 421f from the flip-flop 420f
And one bit of the (a _13), the output signal 460b from the OR circuit 441 is input. Then, the OR circuit 442 detects whether any one of these inputs has “1” (black dot).

As described above, the OR circuit section 440 detects whether there is a "1" (black dot) in the two large and small window areas of the binary result of the target pixel, and outputs the result to the signal lines 460a to 460a.
60c.

FIG. 15 is a diagram for explaining details of the memory 410 and the flip-flops 420a to 420g in FIG.

With the above configuration, when a series of processes such as binarization and error diffusion are sequentially completed, the pixel of interest is shifted by one to update the data in the window, and the above process is repeated again. At this time, after the processing is completed, flip flop 4
Upper 3 bits (b ₂ ′, b ₃ ′, b
₄ ') is fed back to the three-line buffer 410 and stored for use in the processing of the next line. Therefore, the upper three bits (b ₂ ′, b ₃ ′,...) Of the signal line 421a from the flip-flop 420a
b ₄ ′) is stored in the memory 410. At the same time, the signal line 360 resulting from the binarization is input to the MSB side of the flip-flop 420f and latched.

As described above, the data in the flip-flop is sequentially shifted in synchronization with the clock, and the data in the processed flip-flop is stored in the memory for three lines.

The first to fifth embodiments will be described below. The five embodiments are binarizing devices having the configuration shown in FIG. Although the common parts of the five embodiments are as already described, each embodiment has a feature in the configuration and operation of the resolution conversion circuit 500. Therefore, in the description of each embodiment, the configuration of the resolution conversion circuit 500 and its operation will be described. This will be mainly described.

[First Embodiment (FIGS. 6 to 22)] In this embodiment, the binarized image is subjected to twice the resolution conversion in the main scanning direction and the sub-scanning direction, and the dots are divided. The case of outputting will be described.

FIG. 16 shows the resolution conversion circuit 500 shown in FIG.
FIG. 3 is a block diagram showing a detailed configuration of FIG. In FIG. 16, reference numeral 510 denotes a look-up table (hereinafter, LUT)
520-523 are OR circuits, and 530-533
Are flip-flops for latching data, 540 to 5
Reference numeral 42 stores binary results for two lines, a FIFO memory for inputting / outputting 2 bits, 2 bits and 8 bits, respectively, 550 a controller for controlling memory access, and 570 for converting parallel data to serial data. It is a shift register.

FIG. 17 is a diagram in which a black dot (*) in a small window area is divided into smaller dots with higher resolution. FIG. 18 is a diagram in which a black dot (*) in a larger window area is divided into smaller dots with higher resolution. FIG. As can be seen from FIGS. 17 and 18, dots are dispersed near in the small window region, and dots are dispersed far in the large window region.

FIG. 19 is a diagram showing the detailed contents of the LUT 510 shown in FIG. In FIG. 19, LUT 510
Signal lines 516a, 516b, 516c output from
From 516d and 516e, patterns of the a-th column, the b-th column, the c-th column, the d-th column, and the e-th column are generated, respectively.

In FIG. 16, a binary data monitoring section 400
Is "0", that is, when the pixel of interest is white, the signal line 460b from another window area
And 460c regardless of the data content,
Two dots of “0” are output in the sub-scanning direction. Therefore, as shown in FIG. 19, from the LUT 510, the signal line 516a in the a-th column, the signal line 516b in the b-th column, the signal line 516c in the c-th column having the target pixel, and the signal line 516 in the d-th column
The signal lines 516e in the d-th and e-th columns all output “0” for all 12 bits of LSB to MSB, and the OR circuits 520 to 5
23 and the flip-flop 533, respectively.

Signal line 46 from binary data monitoring section 400
If the data of 0a is "1", that is, the target pixel is a black dot, and if there is no "1" (black dot) in the large window area, that is, if the outputs of the signal lines 460b and 460c are both "0". For example, as shown in FIG. 18, "1" (black dot) is diffused far from the pixel of interest (the pixel indicated by * in FIG. 18). Therefore, from the LUT 510, FIG.
As shown in FIG. 7, "0001000000001" is sequentially output from the signal line 516a from the LSB as the data of the a-th column, and L is output from the signal line 516b as the data of the b-th column.
“000000000000” is output in order from the SB, and LSB is output from the signal line 516 c as data of the c-th column.
"00000000000000" is output in order from
As the data in the column, “0001000000001” is output from the signal line 516d in order from the LSB, and
“00000000000000” is output from the signal line 516e in order from the LSB as the data in the e-th column, and the OR
The signals are input to the circuits 520 to 523 and the flip-flop 533, respectively.

Signal line 46 from binary data monitoring section 400
0a is "1", that is, the target pixel is a black dot,
When there is no "1" in the small window area and only in the window area outside the small window area, that is, when the signal line 46
If the outputs of 0b and 460c are "0" and "1", respectively, "1" (black dot) is diffused near the target pixel (the pixel indicated by * in FIG. 17) as shown in FIG. . Therefore, from the LUT 510, as shown in FIG.
“000000000000” is output from the signal line 516a in order from the LSB as data in the a-th column, “001000001000” is output from the signal line 516b in order from the LSB as data in the b-th column, and signal line is output as data from the c-th column. From “516c”, “00” is sequentially executed from LSB.
00000000 "is output, and as data in the d-th column," 00100
0001000 "is output, and as data of the e-th column," 00000000 "is sequentially output from the signal line 516e, starting from the LSB.
0000 "is output to the OR circuits 520 to 523 and the flip-flop 533.

Signal line 46 from binary data monitoring section 400
0a is "1", that is, the target pixel is a black dot,
If "1" is also present in the small window area, that is, if the outputs of the signal lines 460b and 460c are both "1",
Simply add “1” (black dot) in both the main scanning and sub-scanning directions next to the pixel of interest. Therefore, LUT 510
19, "00000000000000" is sequentially output from the signal lines 516a and 516b in order from the LSB as the data of the a-th column and the b-th column, as shown in FIG. As data in the c-th column, “0000011110000” is output from the signal line 516c in order from the LSB. Signal lines 516d and 516e are used as d-th and e-th data.
From "LSB" in the order from LSB
0 "is output. In this way, the output data is output to the OR circuits 520 to 523 and the flip-flop 5
33 respectively.

Next, an OR circuit 520, memories 540-5
The processing in the a-th column composed of 42 will be described. Here, the contents of the LUT 510 shown in FIG. 19 correspond to the bits shown in FIG.

The OR circuit 520 has 12-bit data output from the signal line 516a from the LUT 510, and 12-bit data from the output signal line 536b of the flip-flop 530 in which the processing results of one column up to the previous time are stored. And the 8-bit data from the memory 542 in which the processing results of the second and subsequent lines are stored.
c.

That is, as shown in FIG.
The LSB of data output from a, the LSB of data output from the signal line 536b, and the LSB of data output from the signal line 546c are input to the LSB side of the OR circuit 520 and output as processing on the LSB side. , Memory 5
Forty LSBs are input and stored. Signal line 516a
, The second bit of the output data from the signal line 536b, and the second bit of the output data from the signal line 546c are input to the second bit of the OR circuit 521, and the second bit of the It is output as a process and is input to the MSB of the memory 540 and stored.

The third and fourth bits of the output data from the signal line 516a, the third and fourth bits of the output data from the signal line 536b, and the third and fourth bits of the output data from the signal line 546c. Bit OR is the OR circuit 52
0 is input to the third and fourth bits, and the third bit,
Output as the processing of the fourth bit, the LS
B and MSB are input and stored.

Further, the fifth to eighth bits of the output data from the signal line 516a, the fifth to eighth bits of the output data from the signal line 536b, and the five bits of the output data from the signal line 546c. MSB from eyes
Are input from the fifth bit to the eighth bit of the OR circuit 520, output as the processing from the fifth bit to the eighth bit, and input and stored from the LSB to the fourth bit of the memory 542.

The OR circuit 5 outputs the ninth bit to the MSB of the output data from the signal line 516a and the ninth bit to the MSB of the output data from the signal line 536b.
20 is input from the ninth bit to the MSB, output as the processing from the ninth bit to the MSB, and stored in the memory 542.
Are input and stored from the fifth bit to the MSB.

Next, the processing of the b-th column composed of the OR circuit 521 and the flip-flop 530 will be described.

The OR circuit 521 stores the 12-bit data output from the signal line 516b from the LUT 510 and the flip-flop 5 storing the processing results up to the previous time.
The 12-bit data output from the output signal line 536c is input and processed corresponding to the LSB to MSB, respectively, and the output is the L level of the flip-flop 530.
The data is input and stored from SB to MSB.

Thereafter, the processes in the c-th and d-th columns are performed in the same manner as described above. Then, as the processing in the e-th column, the LUT 51
Data output from the signal line 516e from 0 is directly input to the flip-flop 533 and stored.

FIG. 21 shows the controller unit 55 shown in FIG.
FIG. 2 is a block diagram showing a detailed configuration of the 0 ’. In FIG. 21, reference numeral 551 denotes a counter which counts the number of pixels for one line in the main scanning direction. 552 is a JK type flip
The flop. 553a and 553b are AND gates, and 553c is an inverter.

The binary result from the binarizing section 350 is output to the signal line 3
The counter 551 performs a count operation in synchronism with the output. That is, a signal synchronized with the transfer of the binary result is input to the clock of the counter 51. The counter 551 counts the number of pixels for one line. As shown in the timing chart of FIG. 22, the counter 551 counts the number of pixels for one line to １ ／ and then outputs “1” from the signal line 557a. Is output. Further, when the remaining half of the number of pixels for one line is counted, the carrier signal "1" is output from the signal line 557b. That is, if the counter 551 counts the number of pixels of ラ イ ン of one line, “1” is output from the signal line 557a,
When the number of pixels for one line is counted, "1" is output from the signal line 557b.

First, when the number of pixels for one line is counted, "1" from the signal line 557b, which is a carrier signal, is counted.
The output is input to the J terminal of the flip-flop 552. Therefore, the flip flop 552 is set,
From the Q terminal output of the flip-flop 552, the signal line 5
"1" is output through 58b. The signal line 558b is input to one side of the AND gates 553a and 553b.

During the counting of the number of pixels of the next one line, "0" is output from the signal line 557a while the number of pixels of the first half of the line is being counted.
This signal is supplied to the AND gate 5 via the inverter 553c.
Since it is input to 53a, "1" is output from AND gate 553a. Therefore, "1" is output to the output signal line 556a from the AND gate 553a, and FIG.
The memory 540 shown in FIG. 6 is enabled, and the stored contents can be read.

Subsequently, while counting the number of remaining 画素 pixels for one line, “1” is output from the signal line 557a.
Is output. This signal is input to the AND gate 553b, and the AND gate 553b is satisfied.
"1" is output to 56b. By outputting “1” from the signal line 556b, the memory 5 shown in FIG.
41 is enabled and its stored contents are read.

Reading from the memory 540 or 541 is performed at twice the writing speed. That is, the first one
While “の” is output from the signal line 556a during the transfer of の pixels of the line, the memory 54
0 is enabled and read at double speed, and signal line 5
Two bits 46a are input to the shift register 570, converted from parallel data to serial data, and serially output as a signal line 560 at twice the speed.

Next, while the remaining 画素 pixel of one line is being transferred, “1” is output from the signal line 556 b to enable the memory 541 and enable the signal line 546.
The same operation as described above is performed by the output from b.

Finally, when all the operations are completed, an end signal is input to the K terminal of the flip-flop 552 to be reset, and "0" is output from the Q terminal to stop.

As described above, according to the present embodiment, 2
Detects the low-density region of the binarized image, divides the dots present in the low-density region into higher-resolution dots, and outputs them, thereby reducing the graininess without increasing the page memory. Can be obtained.

[Second Embodiment (FIGS. 23 to 27)] The present invention is not limited to the resolution conversion described in the first embodiment. Included in the scope of the invention. In the present embodiment, a case will be described where the resolution conversion is performed by dividing the dots by four times in the main scanning direction and twice in the sub-scanning direction.

Here, the procedure for dividing the resolution conversion circuit 500 into small dots centering on the resolution conversion circuit 500 and the LU
The contents of T will be described with reference to the drawings. Note that the configuration of the common part of the device will be referred to by the device reference number already described, and description thereof will be omitted.

FIG. 23 shows a resolution conversion circuit 5 according to this embodiment.
It is a block diagram which shows the detailed structure of 00. In FIG. 23, the basic configuration is the same as that of FIG.
Is substantially the same as the resolution conversion circuit 500 shown in FIG. The only difference is the bit configuration of each circuit. Therefore, the reference numerals of the respective circuits are the same as those in FIG. 16, and the description of the respective circuit configurations is omitted. In FIG. 23, reference numerals 540 to 542 denote FIFO memories which can store binary results for two lines and input / output 4-bit, 4-bit and 16-bit data, respectively.

FIG. 24 is a diagram showing an example in which a black dot (*) in a small window area is divided into small dots having higher resolution according to the present embodiment. FIG. 25 shows a black dot in a large window area according to the present embodiment. It is a figure showing an example which divides a dot (*) into small dots with higher resolution. 24 to 25
As can be seen from FIG. 7, the black dots (*) are dispersed near in the small window area, and the black dots (*) are dispersed far in the large window area.

FIG. 26 shows the contents of LUT 510 shown in FIG. In FIG. 26, signal lines 516a,
From 16b, 516c, 516d, and 516e, patterns in the first, second, third, fourth, and fifth columns are generated, respectively.

When the data of the signal line 460a from the binary data monitoring unit 400 is "0", that is, when the pixel of interest is white, the signal lines 460b and 46 from other window areas
Regardless of the data content of 0c, two dots each of "0" are output in the main scanning direction and the sub-scanning direction. Therefore, FIG.
As shown in FIG. 6, from the LUT 510, the signal line 5 in the first column
16a, the signal line 516b in the second column, the signal line 516c in the third column having the pixel of interest, the signal line 516d in the fourth column, and the signal line 516e in the fifth column are all "0" in the 12 bits of LSB to MSB. Is output, and the output is output from OR circuits 520-5
23 and the flip-flop 533, respectively.

When the data on the signal line 460a from the binary data monitoring unit 400 is "1", that is, when the target pixel is a black dot, and there is no "1" (black dot) in the large window area, That is, the signal lines 460b and 460
If both outputs of c are “0”, “1” (black dot) is dispersed far from the pixel of interest (the pixel indicated by * in FIG. 25) as shown in FIG. Therefore, the LUT 51
From 0, as shown in FIG. 26, the data of the first column is “00000001” from the signal line 516a in order from the LSB.
0000000000000001 "is output.
As data of the column, “000000000000000000000000” in order from the LSB from the signal line 516b.
1 "is output. The signal line 516 is used as data of the third column.
From c, "0000000100000" in order from LSB
000000000001. As data of the fourth column, "000" is sequentially output from the signal line 516d, starting from the LSB.
000010000000000000001 "is output from the signal line 516e as data of the fifth column.
"0000000000000000000" in order from SB
000000 ". These outputs are output to the OR circuits 520 to 523 and the flip-flop 533.
Respectively.

Furthermore, this is the case where the signal line 460a from the binary data monitoring unit 400 is "1", that is, the target pixel is a black dot, and there is no "1" in the small window area, but only in the window area outside the small window area. If there is a “1”, that is, if the outputs of the signal lines 460b and 460c are “0” and “1”, respectively, as shown in FIG.
In step (1), “1” (black dot) is dispersed near the pixel indicated by *. Therefore, from the LUT 510, FIG.
As shown in FIG. 5, as the data of the first column, "0000000000000000000" is sequentially transmitted from the signal line 516a to the LSB.
0000000000. As the data of the second column, “000000” is sequentially output from the signal line 516b, starting from the LSB.
10000000000000000000000 ". LSB is output from the signal line 516c as data of the third column.
"000010010000000001001
0000. The data of the fourth column is “00000000100” from the signal line 516d in order from the LSB.
"0000010010000000". As data of the fifth column, "000000000000000000000000" is sequentially sent from the signal line 516e to the LSB.
0 ". These outputs are output to the OR circuit 5
20 to 523 and the flip flop 533, respectively.

Finally, the case where the signal line 460a from the binary data monitoring unit 400 is "1", that is, the target pixel is a black dot, and the case where "1" is also in the small window area, that is, the signal line 460b and If both outputs of 460c are "1", "1" (black dot) is simply added in both the main scanning and sub-scanning directions next to the target pixel. Therefore, LUT5
10, as shown in FIG. 26, both the LSBs from the signal lines 516 a and 516 b are used as data in the first and second columns.
"000000000000000000000000
0000. The data of the third column is “00000000” in order from the LSB from the signal line 516c.
11111111110000000 "is output.
Signal lines 516d and 516 are used as data in the fifth and fifth columns.
From e, "000000000000" in order from LSB
0000000000000 ". The data thus output is input to the OR circuits 520 to 523 and the flip-flop 533, respectively.

The processing in the first column composed of the OR circuit 520 and the memories 540 to 542 will be described. here,
The contents of the LUT shown in FIG. 26 correspond to the bits shown in FIG.

In the OR circuit 520, the 24-bit data output from the signal line 516a from the LUT 510 and the flip-flop 53 storing the processing results up to the previous time are stored.
The 24-bit data output from the output signal line 536b of 0 and the 16-bit data from the memory 542 in which the processing results of the second and subsequent lines are stored are transferred to the signal line 546.
c. That is, as shown in FIG. 27, the data from the LSB of the signal line 516a to the 4th bit, the data from the LSB of the signal line 536b to the 4th bit, and the data from the LSB of the signal line 546c to the 4th bit are O.
Input from the LSB of the R circuit 520 to the fourth bit,
The data is output as a process from LSB to 4 bits, and is input to and stored in 4 bits from LSB to MSB of the memory 540.

Next, data from the 5th bit to the 8th bit of the signal line 516a, data from the 5th bit to the 8th bit of the output signal line 536b, and data from the 5th bit to the MSB of the signal line 546c are The fifth to eighth bits of the OR circuit 520 are input, output as the fifth to eighth bit processing, and stored in the memory 541.
Are input and stored in 4 bits from the LSB to the MSB.

Also, 1 from the ninth bit of the signal line 516a.
The data up to the 6th bit, the data up to the 9th to 16th bits of the output signal line 536b, and the signal line 546
The data from the ninth bit to the MSB of c is OR circuit 52
The ninth through sixteenth bits of 0 are input, output as the ninth through sixteenth bit processing, and input into eight bits from the LSB to eight bits of the memory 542 and stored.

Finally, the data from the 17th bit of the signal line 516a to the MSB and the 17th bit of the output signal line 536b are output.
The data from the bit to the MSB is 1 in the OR circuit 520.
The data is input from the 7th bit to the MSB, output as the processing from the 17th bit to the MSB,
It is input and stored from the bit to the MSB.

Next, the processing of the second column including the OR circuit 521 and the flip-flop 530 will be described. In FIG. 23, an OR circuit 521 includes an LUT 51
24-bit data from the signal line 516b from 0, and 24-bit data are input through the output signal line 536c from the flip-flop 531 in which the processing result up to the previous time is stored, and correspond to the LSB to the MSB, respectively. The processed data is input and stored corresponding to the MSB from the LSB of the flip-flop 530.

Thereafter, the processing in the third and fourth columns is performed in the same manner as described above. Then, as the processing of the fifth column, the LUT 51
Data from the 0 signal line 516e is directly input to the flip-flop 533 and stored.

The controller 550 shown in FIG.
The same operation as in the embodiment is performed. However, since the bit length of the memories 540 and 540 is 4 bits, the 4-bit output from the signal line 546a or 546b is output from the shift register 570.
And is converted from parallel data to serial data,
Further, it is serially output as a signal line 560 at four times the speed.

Finally, after the transfer of all binary results is completed, reading from the memory is completed and stopped by an end signal (not shown).

As described above, according to the present embodiment, it is apparent that resolution conversion of an arbitrary integral multiple can be easily realized independently in the main scanning and sub-scanning directions. Further, resolution conversion of an arbitrary integral multiple only in the main scanning direction or only in the sub-scanning direction can be easily performed.

As described above, according to this embodiment, there is an effect that a high-quality reproduced image with less graininess can be obtained without further increasing the page memory.

[Third Embodiment (FIGS. 28 to 30)] In this embodiment, a case will be described in which the binarized image data is doubled in resolution in the main scanning direction.

FIG. 28 shows a resolution conversion circuit 5 according to this embodiment.
It is a block diagram which shows the example of a detailed structure of 00. In FIG. 28, 510 is an LUT, 520 is an OR circuit, 530 is a flip-flop (F / F) for latching data, and 5
Reference numeral 70 denotes a shift register (SR) for converting parallel data into serial data. Resolution conversion circuit 500 of the present embodiment
As compared with the resolution conversion circuits according to the first and second embodiments (FIGS. 16 and 23), the components are basically the same, so the same device reference numbers are used.

FIG. 29A is a diagram in which a black dot (*) in a small window area is divided into small dots having a higher resolution. FIG. 29B is a diagram in which a black dot (*) in a large window area is divided into smaller dots having a higher resolution. The figure which divides into dots is shown. FIG.
As can be seen from A and FIG. 29B, black dots are dispersed near the pixel of interest (*) in the small window area, and black dots are dispersed far from the pixel of interest (*) in the large window area.

FIG. 30 is a diagram showing the contents of the LUT 510.

When the data on the signal line 460a from the binary data monitoring unit 400 is "0", that is, when the pixel of interest is white, the signal lines 460b and 460 from other window areas are used.
“0” is 2 in the main scanning direction regardless of the value of the data of c.
The output unit 600 sets “0” to 2
Output for pixels. Therefore, as shown in FIG.
From 510, all 12 bits of LSB to MSB are “0”
Is output and input to one of the OR circuits 520. Also, 10 bits from the MSB side of the flip-flop 530 are fed back to the other side of the OR circuit 520 and input. As a result, the 12-bit data is again input to the flip-flop 530 from the OR circuit 520 and rewritten. Further, 12 of data rewritten and output from flip-flop 530 is output.
The bits are input to the shift register 540, and two bits are output one by one from the LSB side.

On the other hand, when the target pixel is “1” (black dot) and there is no “1” in the large window area, that is, when the outputs of the signal lines 460b and 460c are both “0”, FIG. "1" far from the pixel of interest as shown in
(Black dots). Therefore, as shown in FIG. 30, the LUT 510 outputs “000100” in order from the LSB.
000100 "is output and input to one of the OR circuits 520.

Further, the pixel of interest is "1" (black dot)
In the case where there is no “1” in the small window area and “1” only in the area outside the small window area, that is, when the signal line 460b,
When the output of 460c is "0" and "1" respectively,
As shown in FIG. 29A, “1” (black dot) is dispersed near the target pixel. Therefore, from LUT 510, FIG.
As shown in FIG.
"0" is output and input to one of the OR circuits 520.

Finally, the pixel of interest is "1" (black dot)
When "1" is present in the small window area, that is, when both the signal lines 460b and 460c are "1", "1" (black dot) is simply added next to the pixel of interest. Therefore, “00000110000” is output from the LUT 510 sequentially from the LSB side as shown in FIG.
The signal is input to one of the circuits 520.

As described above, the pattern generated from the LUT 510 and the flip pattern in which the previous pattern is stored are stored.
The result of the flop 530 is fed to the OR circuit 520.
It is backed up and corrected by the OR circuit 520. That is,
The LSB of the output data from the LUT 510 and the third bit of the output from the flip-flop 530 are OR circuits 52
0 is input and output as LSB. Also, LUT
The second bit of the output from 510 and the fourth bit of the output from flip-flop 530 are input to OR circuit 520 and output as the second bit.

Similarly, 1 of the output from LUT 510
0th bit and M of output from flip-flop 530
SB is input to the OR circuit 520 and output as the 10th bit.

Next, from the LUT 510, 11
The bit and the MSB are directly output from the OR circuit 520 as data of the 11th bit and the MSB.

The above results are input to the shift register 540, and are sequentially output from the LSB side two bits at a time.

As described above, according to the present embodiment, 2
Detects the low-density area of the binarized image and divides the dots that exist in the low-density area into higher-resolution dots and hits them, thereby increasing the page memory and reducing the granularity. Can be obtained.

[Fourth Embodiment (FIGS. 31 to 38)] In this embodiment, a case will be described in which binarized image data is subjected to twice the resolution conversion in the sub-scanning direction to obtain a high-quality reproduced image. . In this embodiment, the common configuration described above is compared with 2
Since the configuration of the value data monitoring unit 400 is partially different, in the following description, the binary data monitoring unit 400
The configuration and the resolution conversion circuit 500 will be mainly described with reference to the drawings.

<Description of Binary Data Monitoring Unit 400 (FIG. 31)
FIG. 31 is a block diagram showing a detailed configuration of the binary data monitoring section 400 according to the present embodiment. In FIG. 31, reference numeral 410 denotes a value which can store binary results for 5 lines.
FIFO memory for inputting / outputting bit data, 420a
420e is a flip-flop for latching data,
430 and 440 are OR circuit units. Note that the circuit configuration shown in FIG. 31 has substantially the same configuration as the binary data monitoring unit shown in FIG.
The different parts are the number of flip-flop circuits and the number of bits of data output from the circuits.

Now, the binarized data (5 bits) is sequentially read from the memory 410 in synchronization with the clock, and is input to the flip-flop 420e. Thereafter, the flip-flops 420d to 420d are synchronized with the clock.
The data is sequentially shifted to a. On the other hand, “1” is output from the signal line 360 as a result of the processing performed by the binarization circuit 300.
Or, the binary data of “0” is flip-flop 420
d is input to the MSB. Therefore, the output of the flip-flops 420d to 420a is 6 bits.

The flip flop 420a has the structure shown in FIG.
35 (b ₁ ′, b ₃ ′, b ₄ ′, b ₅ ′,
The binarization results of b ₆ ′ and b ₇ ′) are latched in order from the lower bit. Similarly, the flip-flop 420b has 6 (b ₂ ′, a ₁ ′, a ₂ ′, a ₃ ′, a ₄ ′, a ₅ ′).
Bits and flip-flops 420c have (b ₁ , b ₅ ,
The 6 bits of b ₆ , b ₇ , b ₈ , b ₉ ) and the flip-flop 420 d have 6 bits of (b ₂ , a ₁ , a ₄ , a ₇ , a ₉ , a ₁₃ ).
The bit and flip-flop 420e have (b ₃ , a ₂ ,
a ₅ , a ₈ , a ₁₁ ) are latched and the memory 41
From 0, five bits (b ₄ , a ₃ , a ₆ , a ₉ , a ₁₂ ) are output.

The OR circuit section 430 receives the bits 6, 6, and 5 from the flip-flops 420c to 420e, and the five bits from the memory 410.

The OR circuit section 440 receives 6, 6, 6, and 6 bits from the flip-flops 420a to 420d.

FIG. 32 is a circuit diagram showing the OR circuit section 430 shown in FIG.
FIG. 3 is a block diagram showing a detailed configuration of FIG. In FIG. 32, 431 and 432 are OR circuits.

The OR circuit 431 has five bits (a ₁ , a ₄ , a ₇ , a ₁₀ , a ₁₃ ) of the data output to the output signal line 421 d from the flip-flop 420 d,
Four bits (a ₂ , a ₅ , a ₈ , a ₁₁ ) of the signal from the flip-flop 420 e and four bits (a ₃ , a ₆ , a ₉ , a ₁₂ ) of the signal 420 f from the memory 410. Are respectively input. Then, the OR circuit 431 detects whether any one of these inputs has "1" (black bit).

The OR circuit 432 has 6 bits (b ₁ , b ₅ , b ₆ , b ₇ , b ₈ , b ₉ ) of the data output from the flip-flop 420 c to the output signal line 421 c.
And the output signal line 42 from the flip-flop 420d
1 bit (b ₂ ) of data output to 1d, 1 bit (b ₃ ) of data output to output signal line 421e from flip-flop 420e, and memory 4
One bit (b ₄ ) of the data output to the output signal line 421f from 10 is input. And
The OR circuit 432 detects whether any one of these inputs has "1" (black dot).

As described above, the binary data monitoring section 400 according to the present embodiment detects whether "1" (black dot) exists in the large and small window areas, and outputs the signal lines 370a and 370.
b, and outputs the detection result.

FIG. 33 is a circuit diagram showing the OR circuit section 440 shown in FIG.
FIG. 3 is a block diagram showing a detailed configuration of FIG. In FIG. 33, reference numerals 441 and 442 denote OR circuits.

[0128] b ₇ shown in FIG. 33, in one bit of the data outputted to the output signal line 421c from the flip-flop 420c, it is output to the signal line 460a. This is the binary result of the pixel of interest in the binary data monitoring window for resolution conversion.

The OR circuit 441 has 5 bits (a ₁ ′, a ₂ ′, a ₃ ′, a ₄ ′, a ₅ ′) of the data output to the output 421 b from the flip-flop 420 b.
And the output signal line 42 from the flip-flop 420c
4c (b ₅ , b ₆ ,
b ₈ , b ₉ ) and 5 bits (a ₁ , a ₄ , a ₇ , a ₁₀ , a ₁₃ ) of the data output to the output signal line 421 d from the flip-flop 420 d. Then, the OR circuit 441 detects whether or not any one of these inputs has "1" (black dot).

The OR circuit 442 has 6 bits (b ₁ ′, b ₃ ′, b ₄ ′, b ₅ ′, b ₆ ′,...) Of data output from the flip-flop 420 a to the output signal line 421 a.
b ₇ ′) and one bit (b) of the data output to the output signal line 421b from the flip-flop 420b.
₂ '), one bit (b ₁ ) of the data output to the output signal line 421c from the flip-flop 420c, and one bit of the data output to the output signal line 421d from the flip-flop 420d. Bit (b
₂ ) and the output signal 460b of the OR circuit 441 is input. Then, the OR circuit 442 detects whether any one of these inputs has "1" (black dot).

As described above, the binary result of the target pixel,
It is detected whether or not "1" (black dot) exists in one window area, and the result is output to signal lines 460a to 460c.

FIG. 36 is a diagram showing a detailed data flow of the memory 410 and flip-flops 420a to 420e shown in FIG.

After a series of processing is completed, the data in the window is updated by shifting the pixel of interest by one, and the above processing is repeated again. At this time, after processing is completed,
The upper 5 bits (b ₃ ′, b ₄ ′, b ₅ ′, b ₆ ′, b ₇ ′) of the contents of the flop 420 a are used in the processing of the next line, so that the memory 4 of the 5-line buffer is used.
The information is fed back to and stored in 10. Accordingly, the upper 5 bits (b ₃ ′, b ₄ ′, b) of the data output to the output signal line 421 a from the flip-flop 420 a
₅ ′, b ₆ ′, b ₇ ′) are stored by feedback from the memory 410.

At the same time, the binarized result is input to the MSB side of the flip-flop 420d through the signal line 360 and latched.

As described above, the data in the flip-flop is sequentially shifted in synchronism with the clock, and the data in the processed flip-flop is stored in the memory for five lines.

<Description of Resolution Conversion Circuit 500 (FIG. 37,
FIG. 38)> FIG. 38 shows a resolution conversion circuit 5 according to the present embodiment.
It is a block diagram which shows the detailed structure of 00. In FIG. 38, 510 is an LUT, 520 is an OR circuit, 530 is a flip-flop that latches data, and 540 is a FIFO memory that can store binary results for 11 lines and inputs and outputs 11-bit data. The contents of the LUT 510 are the same as the contents of the LUT shown in FIG.

FIG. 37A shows a diagram in which a black dot (*) in a small window area is divided into smaller dots having a higher resolution. FIG. 37B shows a case in which a black dot (*) in a larger window area is divided into smaller dots having a higher resolution. The figure which divides into dots is shown. FIG.
As can be seen from FIG. 37A and FIG. 37B, the dots are diffused near the black dot (*) as the target pixel in the small window region, and farther than the black dot (*) as the target pixel in the large window region.

When the data on the signal line 460a from the binary data monitoring unit 400 is "0", that is, when the pixel of interest is white, the signal lines 460b and 460 from other window areas
Regardless of the data value of c, "0" is output for two pixels in the sub-scanning direction. Therefore, as shown in FIG.
From 510, all 12 bits of LSB to MSB are output as “0” and input to one of the OR circuits 520. Further, to the other input of the OR circuit 520, all the 11 bits of output data of the memory 540 in which the results up to the previous time are stored are fed back from the LSB side and input. As a result, the output from the memory 540 is input to the flip-flop 530 again and rewritten.

On the other hand, when the target pixel is “1” (black dot),
If there is no “1” in the large window area, that is, if the outputs of the signal lines 400b and 460c are both “0”, as shown in FIG. 37B, “1” is far from the pixel of interest.
(Black dots). Therefore, from the LUT 510, as shown in the LUT of FIG.
0100000100 ″ is output and input to one of the OR circuits 520.

Furthermore, the pixel of interest is "1" (black dot)
In the case where there is no "1" in the small window area and only "1" in the area outside the small window area, that is, when the signal line 460b,
If the output of 460c is "0" and "1" respectively,
As shown in FIG. 37A, “1” (black dot) is diffused near the target pixel. Therefore, from LUT 510, FIG.
0, as shown in the LUT, “00001” in order from the LSB side.
0001000 "is output and input to one of the OR circuits 520.

Finally, when the pixel of interest is "1" and there is also "1" in the small window area, that is, the signal line 460
If both b and 460c are “1”, “1” (black dot) is simply added next to the pixel of interest (sub-scan direction). Therefore, “00000110000” is sequentially output from the LSB from the LUT 510 as shown in the LUT of FIG. 30, and is input to one of the OR circuits 520.

As described above, the pattern generated from the LUT 510 is used as one input of the OR circuit 520, and the 11 bits that are fed back from the memory 540 in which the previous pattern is stored are sent to the other of the OR circuit 520 from the LSB side. The input is ORed bit by bit, and the resulting bit is input to flip flop 530.

That is, the LSB of the output from LUT 510
And the LSB output from the memory 550 are both input to the OR circuit 520 and output as the LSB. Also, L
The second bit of the output from the UT 510 and the second bit of the output from the memory 550 are input to the OR circuit 520 and output as the second bit. Hereinafter, the same output is performed, and the 11th bit of the output from the LUT 510 and the memory 5
The MSB of the output from the node 50 is input to the OR circuit 520 and output as the 11th bit data. And
The MSB of the output from the LUT 510 is output directly from the OR circuit 520 as the MSB.

The LSB output from the flip-flop 530 is output not to the memory 550 but to the signal line 560 to become an output signal.

Therefore, according to this embodiment, the resolution conversion of the binarized image can be performed in the sub-scanning direction, and the resolution can be doubled and output.

[Fifth Embodiment (FIGS. 39 to 42)] In this embodiment, a case will be described in which resolution conversion for a binarized image is executed in a direction oblique to the main scanning direction to divide dots. Here, the division of the dots into small dots and the contents of the LUT will be described with reference to the drawings, focusing on the description of the resolution conversion circuit 500 which is a feature of the present embodiment.

FIG. 39 shows a resolution conversion circuit 5 according to this embodiment.
It is a block diagram which shows the detailed structure of 00. 39, 510 is an LUT, 520 to 522 are OR circuits,
Numerals 30 to 532 denote flip-flops for latching data, 550 and 551 each store a binary result for one line, and a FIFO memory for inputting / outputting 2-bit data.
A shift register (SR) 40 converts parallel data into serial data.

FIG. 40A is a diagram in which a black dot (*) in a small window area is divided into small dots having a higher resolution. FIG. 40B is a diagram in which a black dot (*) in a large window area is divided into a small dot having a higher resolution. FIG. FIG.
As can be seen from FIG. 40A and FIG. 40B, also in this embodiment, the dots are diffused near the black dots (*) in the small window region, and are diffused far from the black dots (*) in the large window region.

FIG. 41 is a diagram showing the contents of the LUT 510 shown in FIG. Signal lines 516a, 516b, 516c
, Patterns of the first, second, and third lines are generated.

When the data on the signal line 460a from the binary data monitoring section 400 is "0", that is, when the pixel of interest is white, the signal lines 460b and 460b from other window areas are used.
“0” in the main scanning direction regardless of the data content of 60c
Is output for two pixels. Therefore, as shown in FIG. 41, the LUT 510 outputs the signal line 516 of the first line.
a, “0” is output to all 12 bits of the LSB to MSB of the second signal line 516 b and the third signal line 516 c having the target pixel, and the output is OR circuit 5.
20 to 522.

Next, the processing of the line executed using the OR circuit 520, flip-flop 530, and shift register 540 will be described.

The OR circuit 520 has 12-bit data output to the signal line 516a from the LUT 510 and the flip-flop 53 storing the processing result up to the previous time.
10 bits from the MSB side of 12 bits of output data of 0
The bit and the 2-bit data from the memory 550 in which the processing results of the second and subsequent lines are stored are represented by a signal line 556a.
Is entered through

That is, as shown in FIG.
a, the third bit of the data output to the signal line 536a, and the LSB of the data output to the signal line 556a are input to the LSB side of the OR circuit 520, and the processing of the LSB side is performed. And is input to the LSB of the flip-flop 530. The second bit of the data output to the signal line 516a, the signal line 53
4th bit of data output to 6a, and signal line 55
The second bit of the data output to 6a is the OR circuit 52
0 is input to the second bit, output as the second bit process, and input to the second bit of the flip-flop 530. Further, the third bit of the data output to the signal line 516a and the fourth bit of the data output to the signal line 536a
The bit is input to the third bit of the OR circuit 520,
Output as bit-th processing, flip-flop 5
It is input to the 30th third bit.

Similarly, the 10th bit of the data output to the signal line 516a and the MSB of the data output to the signal line 536a are input to the 10th bit of the OR circuit 520 and output as the 10th bit processing. Then, it is input to the 10th bit of the flip-flop 530.

Then, the eleventh bit and the MSB of the data output to the signal line 516a are directly input to the eleventh bit and the MSB of the flip-flop 530, respectively. LSB of data output from flip-flop 530
And the second bit are input to the shift register 540 and output as 2-bit serial.

Next, the processing of the second line including the pixel of interest, which is performed using the OR circuit 521, the flip-flop 531 and the memory 550, will be described.

The operation of the second line is the same as that of the first line, and the signal line 556a from the memory 550 is provided.
Signal 55 from the memory 551 instead of the data passing through
Data passing through 6b is input. Therefore, the signal line 516
b, the 3rd and 4th bits of the data output to the signal line 536b from the flip-flop 531 and the memory 55
The LSB and the second bit of the data output to the signal line 556b from 1 are input to the LSB and the second bit of the OR circuit 521, and the processing result is input to the LSB and the second bit of the flip-flop 531. Is done. Further, the third bit to the third bit of the data output to the signal line 516b are output.
The 10th bit and the 5th to MSB of the output data from the flip-flop 531 are OR circuits 52, respectively.
The third to tenth bits of 1 are input, and the processing result is input to the third to tenth bits of the flip-flop 531. Further, the 11th bit and the MSB of the data output to the signal line 516b are directly input to the 11th bit and the MSB of the flip-flop 531. Then, the LSB and the second bit of the output data from the flip-flop 531 are written to the LSB and the second bit of the memory 550.

Finally, the processing of the third line executed using the OR circuit 522, the flip-flop 532, and the memory 551 will be described.

The operation of the third line is the same as that described above, but the third line is different from the first and second lines in that there is no feedback from the memory. That is, the LSB of the data output to the signal line 516c
The 10th to 10th bits and the 3rd to Mth bits of the data output to the signal line 536c from the flip-flop 532
SB are respectively input to the LSB to the 10th bit of the OR circuit 522, and the processing result is output to the flip-flop 53
It is input to the 2nd LSB to the 10th bit. Further, the 11th bit of the data output to the signal line 516c and the MSB
Is directly input to the eleventh bit and the MSB of the flip-flop 532. And flip flop 5
The LSB and the second bit of the output data from 32 are written to the LSB and the second bit of the memory 551.

In the above configuration, for example, when the target pixel is "1" (black dot) and there is no "1" in the large window area, that is, when the outputs of the signal lines 460b and 460c are both "0". In FIG. 40B, “1” (black dot) is diffused far and diagonally from the target pixel as shown in FIG. 40B. Therefore, as shown in the LUT of FIG.
From the UT 510, the signal line 5 is used as the first line data.
From 16a, “000000000000” in order from LSB
0 "is output and the signal line 51
From 6b, "0000000000010" in order from LSB
0 "is output and the signal line 51
From 6c, "00010000000" in order from LSB
0 "is output.

Thereafter, the operation is the same as that described above.
Only the contents of 16a, 516b and 516c change.

Furthermore, the pixel of interest is "1" (black dot)
In the case where there is no "1" in the small window area and only "1" in the outside window area, that is, the signal line 4
The outputs of 60b and 460c are "0" and "1" respectively.
In the case of (1), as shown in FIG. 40A, "1" (black dot) is diffused near and obliquely to the target pixel. Therefore, as shown in FIG. 41, "000000001000" is output from the LUT 510 in order from the LSB from the signal line 516a as data of the first line. As data of the second line, “00000000000000” is output from the signal line 516b in order from the LSB. As the data of the third line, “000010000000” is output from the signal line 516c in order from the LSB.

Thereafter, the operation is the same as that described above.
Only the contents of 16a, 516b and 516c change.

Finally, when the target pixel is "1" and "1" is also present in the small window area, that is, when the signal line 460b
If 460c and 460c are both "1", "1" (black dot) is simply added next to the pixel of interest. Therefore, LUT5
As shown in FIG. 41, as the data of the first line, the data of the first line is "00000" from the signal line 516a in order from the LSB.
00000000 ", and as data of the second line," 000000 "is sequentially output from the signal line 516b in order from the LSB.
110000 "is output, and as data of the third line," 00000000 "is sequentially output from the signal line 516c starting from the LSB.
00000 "is output.

Thereafter, the operation is the same as that described above.
Only the contents of 16a, 516b and 516c change.

Therefore, according to the present embodiment, when performing resolution conversion on a binarized image, dots are divided in a direction oblique to the main scanning direction, and the resolution is doubled before being output.

In each of the embodiments described above, monochrome image data is used.
(Yellow), M (magenta). C (cyan), BK
(Black) color image processing system,
The present invention can be similarly applied to the respective data of Y, M, C, and BK. In this case, substantially the same operation and effect as those of the above embodiment can be obtained.

In the five embodiments described above, the error diffusion method is used as the binarization method. However, the present invention is not limited to this, and another binarization method may be used.

[0169]

As described above, according to the present invention, in the reproduced image by the pseudo halftone processing method, the granularity can be reduced in the low density region (highlight portion) where the human eye is most sensitive. In addition, a high-quality reproduced image can be obtained without increasing the page memory for storing image data.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a binarizing device as a typical embodiment of the present invention.

FIG. 2 is a block diagram showing a detailed configuration of a binarization circuit 300 shown in FIG.

FIG. 3 is a circuit diagram showing a detailed configuration of an error diffusion unit 310 shown in FIG.

4 is a diagram showing a diffusion coefficient of error diffusion of an error diffusion unit 310 shown in FIG.

FIG. 5 is a block diagram showing a detailed configuration of a comparison unit 330 shown in FIG.

FIG. 6 is a diagram showing input / output characteristics of a comparison unit 330 shown in FIG. 2;

7 is a diagram showing a detailed circuit configuration of an AND / OR circuit 340 shown in FIG.

8 is a diagram showing a truth table (truth table) of the AND / OR circuit 340 shown in FIG. 2;

FIG. 9 is a block diagram illustrating a detailed configuration of a binarizing unit 350 illustrated in FIG. 2;

FIG. 10 is a block diagram showing a detailed configuration of a binary data monitoring unit 400 shown in FIG.

11 is a detailed circuit diagram of the OR circuit 430 shown in FIG.

12 is a detailed circuit diagram of an OR circuit 440 shown in FIG.

FIG. 13 is a diagram showing an example of a window of the binary data monitoring unit 400 shown in FIG.

FIG. 14 is a diagram illustrating an example of a window of the binary data monitoring unit 400 illustrated in FIG. 1;

FIG. 15 is a connection diagram between the memory unit 410 and the flip-flop shown in FIG.

FIG. 16 is a block diagram showing a detailed configuration of a resolution conversion circuit 500 shown in FIG.

FIG. 17 is a diagram showing pixel data to be diffused according to the first embodiment.

FIG. 18 is a diagram showing pixel data to be diffused according to the first embodiment.

FIG. 19 is a diagram showing the contents of the LUT shown in FIG.

20 is an operation diagram of the OR circuit 520 shown in FIG.

21 is a diagram showing a circuit configuration of a controller 550 shown in FIG.

FIG. 22 is a time chart of various signals handled by the controller 550 shown in FIG. 21.

FIG. 23 is a diagram showing a detailed configuration of a resolution conversion circuit 500 according to the second embodiment.

FIG. 24 is a diagram showing pixel data to be diffused according to the second embodiment.

FIG. 25 is a diagram showing pixel data to be diffused according to the second embodiment.

FIG. 26 is a diagram showing the contents of the LUT shown in FIGS. 24 and 25.

FIG. 27 is a calculation diagram of the OR circuit 520 shown in FIGS. 24 and 25;

FIG. 28 is a block diagram showing a detailed configuration of a resolution conversion circuit 500 according to the third embodiment.

FIG. 29 is a diagram for explaining pixel data to be diffused according to the third embodiment.

30 is a diagram showing the contents of the LUT shown in FIG. 28.

FIG. 31 is a block diagram showing a detailed configuration of a binary monitoring unit 400 according to a fourth embodiment.

32 is a detailed circuit diagram of the OR circuit 430 shown in FIG.

FIG. 33 is a detailed circuit diagram of an OR circuit 440 shown in FIG. 31;

FIG. 34 is a diagram showing a window of the binary data monitoring unit 400 according to the fourth embodiment.

FIG. 35 is a diagram showing a window of the binary data monitoring unit 400 according to the fourth embodiment.

FIG. 36 is a connection diagram of the memory unit 410 and the flip-flop shown in FIG. 31.

FIG. 37 is a diagram for explaining pixel data to be diffused according to the fourth embodiment.

FIG. 38 is a block diagram showing a detailed configuration of a resolution conversion circuit 500 according to the fourth embodiment.

FIG. 39 is a block diagram showing a detailed configuration of a resolution conversion circuit 500 according to a fifth embodiment.

FIG. 40 is a diagram for explaining pixel data to be diffused according to the fifth embodiment.

FIG. 41 is a diagram showing the contents of the LUT shown in FIG. 39.

FIG. 42 is a diagram illustrating an operation of the resolution conversion circuit 500 shown in FIG. 39.

[Explanation of symbols]

 100 page memory 200 input unit 260 binarization circuit 400 binary data monitoring unit 500 resolution conversion circuit 600 output unit

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-4-240969 (JP, A) JP-A-4-88748 (JP, A) JP-A-4-13371 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H04N 1/405 B41J 2/52 G06T 5/00 H04N 1/387-1/393

Claims (16)

(57) [Claims] 1. An image processing method for inputting multi-valued image data and reproducing and outputting an image having shading, comprising the steps of: inputting multi-valued image data; A binarization step of binarizing the image data by an error diffusion method, a detection step of detecting a pixel to be an isolated point in the binary image data binarized by the binarization step, An image processing method, comprising: a conversion step of dividing information of a pixel at a detected isolated point into a plurality of pixels and outputting the divided information; and an output step of outputting a grayscale image based on an output of the conversion step. . 2. An image processing apparatus which receives multi-valued image data and reproduces and outputs an image having shading, comprising: input means for inputting multi-valued image data; A binarizing unit for binarizing the image data by an error diffusion method, a detecting unit for detecting a pixel to be an isolated point in the binary image data binarized by the binarizing unit, An image processing apparatus comprising: a conversion unit that divides information of a pixel at a detected isolated point into a plurality of pixels and outputs the divided information; and an output unit that outputs a grayscale image based on an output of the conversion unit. . 3. The multi-valued image storage means for storing multi-valued image data corresponding to a one-page grayscale image output by the output means, and the multi-valued image data from the multi-valued image storage means. 3. The image processing apparatus according to claim 2, further comprising buffer means for buffering image data input and output of the multi-valued image data to the binarization means. 4. The image processing apparatus according to claim 2, wherein the multi-valued image data is data in which one pixel is represented by 8 bits and gradation can be represented in 256 steps. 5. A search means for searching for pixels surrounding the pixel for each pixel of the binarized image data to detect the isolated point, and a search result by the search means. 3. The image processing apparatus according to claim 2, further comprising a feedback unit that feeds back to the binarizing unit. 6. The search unit according to claim 5, wherein the search unit includes a search range control unit that controls a search range of a peripheral pixel of the pixel to be determined according to a value of the multi-valued image data. Image processing device. 7. The search means includes a narrow area search means for searching for peripheral pixels relatively close to the pixel, and a wide area search means for searching for peripheral pixels relatively far from the pixel. The image processing apparatus according to claim 5, wherein: 8. The image processing apparatus according to claim 7, wherein the area searched by said narrow area search means and said wide area search means is a rectangular area. 9. The method according to claim 7, wherein the narrow area search means detects whether or not the peripheral pixel includes a pixel having a pixel value of “1” by searching for the peripheral pixel.
An image processing apparatus according to claim 1. 10. The image according to claim 7, wherein the wide area search means detects whether or not there is a pixel whose pixel value is “1” in the peripheral pixel by searching for the peripheral pixel. Processing equipment. 11. A conversion unit comprising: a determination unit configured to determine whether there is a pixel whose pixel value is “1” in a binarized image around a pixel at an isolated point detected by the detection unit; If there is a pixel whose pixel value is “1” relatively close to the pixel of the isolated point based on the result of the determination by the determination unit, the pixel value of the isolated point is diffused near the isolated point. Based on the result of the discrimination by the first diffusion means and the discrimination means, when there is a pixel whose pixel value is “1” relatively far from the pixel of the isolated point, the value of the pixel of the isolated point is changed to A second diffusion unit for diffusing the isolated point far from the pixel; and a pixel having a value of “1” relatively far from and near the pixel of the isolated point based on a result of the determination by the determination unit. Diffusing the value of the pixel at the isolated point to pixels adjacent to the isolated point A third diffusion unit; and a control unit that controls the resolution of the grayscale image output from the output unit to an arbitrary integral multiple in a vertical direction and / or a horizontal direction, or an oblique direction. The image processing device according to claim 2. 12. The conversion means according to claim 1, wherein said conversion means converts predetermined binary image data, which is spread by said first spreading means, said second spreading means and said third spreading means, and whose resolution is increased by said control means, 12. The image processing apparatus according to claim 11, further comprising a binary image storage unit for storing lines. 13. The first suppressor, wherein when the value of the pixel at the isolated point is “0”, the first diffusion unit suppresses the value of the pixel at the isolated point so as not to diffuse from the isolated point. The image processing apparatus according to claim 11, further comprising: a lookup table (LUT) having position information for diffusing the pixel value of the isolated point, the lookup table corresponding to the resolution conversion magnification. apparatus. 14. The second suppressor, wherein when the value of the pixel at the isolated point is “0”, the second suppressor suppresses the value of the pixel at the isolated point so as not to diffuse from the isolated point. The image processing apparatus according to claim 11, further comprising: a lookup table (LUT) having position information for diffusing the pixel value of the isolated point, the lookup table corresponding to the resolution conversion magnification. apparatus. 15. The third inhibiting means, when the value of the pixel at the isolated point is “0”, inhibits the value of the pixel at the isolated point from being diffused from the isolated point. The image processing apparatus according to claim 11, further comprising: a lookup table (LUT) having position information for diffusing the pixel value of the isolated point, the lookup table corresponding to the resolution conversion magnification. apparatus. 16. The image processing apparatus according to claim 2, wherein said output means includes a digital facsimile or a digital printer.