JP3182066B2 - Signal transmission circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal transmission circuit for transmitting a given multi-bit binary signal to a corresponding number of signal lines.

[0002]

2. Description of the Related Art Buffers having high input impedance and low output impedance are well known.
For example, in a microprocessor system, an output buffer for transmitting a given N-bit binary signal to a bus including N signal lines is frequently used. Where N
Is an integer of 3 or more, for example, N = 8, 16, 32, 6
4th magnitude.

FIG. 9 shows a configuration of a conventional multi-bit three-state output buffer. The output buffer 5 of FIG. 9 includes N inverting buffers 6 each having a CMOS inverter. DI1 to DIN are given N-bit input binary signals, EN is an enable signal,
7.1-7. N denotes N signal lines constituting a bus, DO
1 to DON indicate N-bit output binary signals, respectively. When the logic level of the enable signal EN is “H”, one inversion buffer 6 has an N-bit input 2.
A binary signal D obtained by inverting the logical level of the corresponding one-bit binary signal DI1 among the value signals DI1 to DIN
O1 is connected to N signal lines 7.1 to 7. Driving said signal line 7.1 to output to the corresponding signal line 7.1 of N;
When the logic level of the enable signal EN is "L", the output to the corresponding signal line 7.1 is set to a high impedance state. The functions of the other N-1 inversion buffers 6 are the same. The N signal lines 7.1 to 7.1
7. N each has a stray capacitance C.

According to the output buffer 5 of FIG. 9, when the logic level of the enable signal EN is "H", each of the N inversion buffers 6 has N signal lines 7.1 to 7.. N
Drive one corresponding signal line. At this time, when the logical level of the applied 1-bit input binary signal transitions from “L” to “H”, each inversion buffer 6 outputs
The electric charge stored in the capacitor C flows to the ground power supply V _ss so that the logic level of the value signal changes from “H” to “L”. When the logical level of a given 1-bit input binary signal changes from “H” to “L”, each inverting buffer 6 changes the logical level of the output binary signal from “L” to “H”. The charging current is supplied from the positive power supply _Vdd to the capacitor C so as to cause the charging. That is, N-bit input binary signals DI1 to D1
When the logical level of the n-bit (n ≦ N) binary signal of IN transitions from “H” to “L”, the terminal voltage of each of the n capacitors C changes to the initial voltage V _c (V _c = 0V)
To rise to "H" level voltage V _dd from the positive supply V _dd, the total E _t of the energy of the formula (1) is supplied. That is, _{E t = E r + E c} -E c0 ... (1). Here, E _r is the energy dissipated by a Joule heat by the resistance of the wiring, E _c is "H" level voltage V
n pieces of capacitor energy C has with _dd, E _c0 is an energy with n number of capacitor C with an initial voltage _{V c, E r = nC (} V dd -V c) 2/2 E c = ^{_{nCV dd 2/2 E c0 =}} nCV c 2/2 ... is (2). From equation (1) and (2), it is _{E t = nCV dd (V dd} -V c) ... (3). Since in the above example is V _c = 0V, the energy consumption E _t of the positive power supply V _dd is ^{_{E t = nCV dd 2 ... (}} 4).

[0005]

According to the above prior art, as can be seen from equation (4), the energy consumption of the positive power supply _Vdd increases in proportion to the number of bits n and the stray capacitance C. The energy consumption of the positive power supply _Vdd per unit time, that is, power consumption, increases in proportion to the operating frequency f of the circuit.

In a system composed of a plurality of LSIs (large-scale integrated circuits), the stray capacitance C of each of N long signal lines constituting a bus between the LSIs is 10 to 20 pF.
Also reach. In addition, the bus width N and the operating frequency f tend to increase as the performance of the system increases. Therefore, according to the above-described conventional technique, power consumption in the output buffer becomes a problem. The same applies to signal transmission between circuit blocks via an internal bus in each LSI.

An object of the present invention is to reduce power consumption in a signal transmission circuit.

[0008]

In order to achieve the above object, a signal transmission circuit according to the present invention provides a signal transmission circuit in which a logical level of N signal lines (N is an integer of 3 or more) is changed from "L" to "H". All of the n signal lines about to transition to "L" and the m signal lines about to transition from "H" to "L" are connected to one common line via switches. Thus, the voltage of the n signal lines whose logic level is about to transition from “L” to “H” is raised to the intermediate voltage V _c (0 <V _c <V _dd ) without power consumption. in which it was decided to implement in each buffer supply of energy for further raising the voltage of the signal line from the intermediate voltage V _c to the "H" level of the voltage V _dd.

According to the signal transmission circuit of the present invention, by effectively utilizing the charge stored in the floating capacitance of each of the m signal lines whose logic level is about to transition from “H” to “L”, logic level voltages of the n signal lines from "L" trying to transition to "H" is pulled without power consumption to an intermediate voltage V _c. Power occurs only when pulling up the voltage of the n signal lines from the intermediate voltage V _c to the "H" level of the voltage V _dd. This power consumption is clearly smaller than the power consumption required to raise the voltage of the n signal lines from the “L” level voltage, that is, 0 V, to the “H” level voltage _Vdd .

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A specific example of a signal transmission circuit according to the present invention will be described below with reference to the drawings.

FIG. 1 shows a configuration example of a microprocessor system. The system in FIG. 1 has one LSI
, And one LSI each
And two memories 20 configured as In FIG. 1, N is connected so that these three LSIs are connected to each other.
A data bus 30 composed of the signal lines is shown. Here, N is an integer of 3 or more, for example, N = 8,
16, 32, 64, etc. The illustration of the address bus and the control bus is omitted.

The processor 10 has an MPU core 11 as a core part thereof, an input buffer 12 for transmitting an N-bit binary signal provided from the data bus 30 to the MPU core 11, and a processor provided from the MPU core 11. And an output buffer 13 for transmitting the N-bit binary signal to the data bus 30. The input buffer 12 and the output buffer 13 constitute one bidirectional bus buffer, and the output buffer 13 is a three-state buffer.

Each memory 20 has a memory core 21 as a core portion thereof, an input buffer 22 for transmitting an N-bit binary signal provided from a data bus 30 to the memory core 21, and a memory core 21 provided from the memory core 21. And an output buffer 23 for transmitting the received N-bit binary signal to the data bus 30. The input buffer 22 and the output buffer 23 constitute one bidirectional bus buffer, and the output buffer 23 is a three-state buffer.

FIG. 2 shows an example of the internal configuration of the output buffer 13 included in the processor 10 in FIG. 2, DI1 to DIN are N-bit input binary signals supplied from the MPU core 11, EN is an enable signal supplied to the output buffer 13, and CLK is an output buffer 1
3. The clock signal given to 3. N denotes N signal lines constituting the data bus 30 and DO1 to D
ON indicates an N-bit output binary signal.
N signal lines 30.1 to 30. N each has a stray capacitance C. The output buffer 13 of FIG.
Unit circuits 40.1 to 40. N and one common line 44
And one clock generator 45 for generating a first clock signal XCLK, a second clock signal ICLK, and a third clock signal YCLK from the applied clock signal CLK, and a third clock signal YCLK. A single NMOS transistor 46 for responsively grounding the common line 44.

[0015] N unit circuits 40.1 to 40. N includes an inversion buffer 41, a switch 42, and a control circuit 4
3 is provided. The first unit circuit 40.1 will be described. The inversion buffer 41 controls the first control signal CT1
When the logic level of “a” is “H”, the binary signal DO1 obtained by inverting the logic level of the corresponding 1-bit binary signal DI1 among the N-bit input binary signals DI1 to DIN. To N signal lines 30.1 to 30. N so as to output to the corresponding one of the signal lines 30.1.
1 is driven, and when the logic level of the first control signal CT1a is "L", the output to the corresponding signal line 30.1 is set to a high impedance state. The switch 42 is interposed between the signal line 30.1 and the common line 44 and is closed when the logic level of the second control signal CT1b is “H”, and the logic level of the second control signal CT1b is “H”. L "is opened. The control circuit 43
The first and second control signals CT1a and CT1b are generated from the input binary signal DI1, the enable signal EN, the first clock signal XCLK, the second clock signal ICLK, and the third clock signal YCLK. Second to Nth unit circuits 40.2 to 40. The same applies to the internal configuration of each of N. In FIG. 2, CT2a and CT2b are the second
The first and second control signals in the unit circuit 40.2.
CTNa and CTNb are the Nth unit circuits 40. N shows first and second control signals, respectively.

FIG. 3 shows the internal configuration of the clock generator 45 in FIG. The clock generator 45 in FIG.
Inverters 51 and 52, one delay circuit 53,
It is composed of one OR gate 54. One inverter 51 generates the first clock signal XCLK by inverting the logic level of the clock signal CLK supplied to the clock generator 45. The other one of the inverters 52 inverts the logic level of the first clock signal XCLK to thereby generate the second clock signal ICL.
Generate K. The second clock signal ICLK has the same phase as the clock signal CLK supplied to the clock generator 45. The delay circuit 53 converts the delayed clock signal obtained by delaying the second clock signal ICLK by a certain time
This is supplied to the R gate 54. OR gate 54
Generates a third clock signal YCLK from the first clock signal XCLK and the delayed clock signal supplied from the delay circuit 53.

FIG. 4 shows the first unit circuit 40.1 in FIG.
2 shows the internal configuration of the control circuit 43. The control circuit 43 of FIG. 4 includes a single latch 6 composed of a master flip-flop 61 and a slave flip-flop 62.
3 and one exclusive NOR gate 64 and 1
There are provided two OR gates 65, one inverter 66, and two AND gates 67 and 68. The master flip-flop 61 includes a PMOS transistor 71 and an NMOS transistor 72 constituting a first CMOS switch, two inverters 73 and 74, and a second CM.
It is composed of a PMOS transistor 75 and an NMOS transistor 76 constituting an OS switch. The slave flip-flop 62 includes a PMOS transistor 81 and an NMOS transistor 82 forming a third CMOS switch, two inverters 83 and 84, and a PMOS transistor 85 forming a fourth CMOS switch.
And an NMOS transistor 86. The gate of each of the PMOS transistor 71 of the first CMOS switch, the NMOS transistor 76 of the second CMOS switch, the NMOS transistor 82 of the third CMOS switch, and the PMOS transistor 85 of the fourth CMOS switch has a first clock. The signal XCLK is supplied. The gate of each of the NMOS transistor 72 of the first CMOS switch, the PMOS transistor 75 of the second CMOS switch, the PMOS transistor 81 of the third CMOS switch, and the NMOS transistor 86 of the fourth CMOS switch is connected to the second gate. Clock signal ICLK is supplied.

In FIG. 4, a given 1-bit input binary signal DI1 is supplied to a PMOS transistor 71 and an NM
The signal is supplied to the input (node N1) of the inverter 73 via the first CMOS switch constituted by the OS transistor 72. The output (node N2) of the inverter 73 is connected to the inverter 74, the PMOS transistor 75 and the NMO
The signal is fed back to the input (node N1) of the inverter 73 via the second CMOS switch constituted by the S transistor 76. The output (node N2) of the inverter 73 is connected to the PMOS transistor 81 and NM
The signal is supplied to the input (node N3) of the inverter 83 via the third CMOS switch constituted by the OS transistor 82. The output of the inverter 83 (node N4) is
Inverter 84, PMOS transistor 85 and NM
The input of the inverter 83 (the node N3) via the fourth CMOS switch constituted by the OS transistor 86
Is fed back to

The exclusive NOR gate 64 has the logic level of the input (node N1) of the inverter 73 in the master flip-flop 61 and the logic level of the output (node N4) of the inverter 83 in the slave flip-flop 62. An OR gate 65 outputs a match signal CNC1 having a logic level of "H" when they match, and a match signal CNC1 having a logic level of "L" when they do not match.
To be supplied to The OR gate 65 generates a basic control signal CNT1 from the third clock signal YCLK and the coincidence signal CNC1. The basic control signal CNT1 is supplied to one AND gate 67 as it is,
The signal is also supplied to another AND gate 68 via the inverter 66. The AND gate 67 generates a first control signal CT1a from the enable signal EN and the basic control signal CNT1. The AND gate 68 generates a second control signal CT1b from the enable signal EN and an inverted signal of the basic control signal CNT1.

The second to Nth unit circuits 40.2 to 40.2 in FIG.
40. N also shows the internal configuration of the control circuit 43 in each of FIG.
The configuration is the same as that described above.

FIG. 5 shows the first unit circuit 40.1 in FIG.
2 shows the internal configuration of each of the inversion buffer 41 and the switch 42. The inversion buffer 41 has two PMOs.
It is composed of S transistors 91 and 92, two NMOS transistors 93 and 94, and one inverter 95. The two PMOS transistors 91 and 92 are interposed between the positive power supply _Vdd and the signal line 30.1, and are connected in series with each other. Two NMOS transistors 9
3, 94 are interposed between the signal line 30.1 and the ground power supply V _ss and are connected in series with each other. Given 1
The bit input binary signal DI1 is composed of a PMOS transistor 92 and an NMOS which constitute one CMOS inverter.
The signal is supplied to each gate of the transistor 93. The first control signal CT1a is supplied to the gate of the NMOS transistor 94 as it is, and is also supplied to the gate of the PMOS transistor 91 via the inverter 95. The switch 42 is a PMO constituting one CMOS switch interposed between the signal line 30.1 and the common line 44.
S transistor 101 and NMOS transistor 102
And one inverter 103. The second control signal CT1b is supplied to the gate of the NMOS transistor 102 as it is, and is also supplied to the gate of the PMOS transistor 101 via the inverter 103.

The second to Nth unit circuits 40.2 to 40.2 in FIG.
40. N and inverting buffer 41 and switch 4 in each of N
2 has the same internal configuration as that of FIG.

FIG. 6 shows the operation of the first unit circuit 40.1 in the output buffer 13 of FIG. Assume that the rising time of the second clock signal ICLK is t _n−1 (not shown), t _n and t _{n + 1} . Assuming that the delay time in the delay circuit 53 in FIG. 3 is T, the third clock signal YC
LK falls at times t _n-1 (not shown), t _n , and t _{n + 1} , and rises after a lapse of time T from the time of the fall. The logic level of the input binary signal DI1 shown in FIG. 6 changes from “L” to “H” between time t _n−1 (not shown) and time t _n, and the time t _n and time t _{n The state} transits from “H” to “L” between _{n + 1} . At this time, the master flip-flop 61 in FIG. 4 synchronizes with the rising transition of the second clock signal ICLK and according to the logical level of the input binary signal DI1, inputs and outputs the inverter 73 (nodes N1 and N1). N2) is updated. Also, the slave flip-flop 62
The logic levels of the input and output (nodes N3 and N4) of the inverter 83 are updated in synchronization with the falling transition of the second clock signal ICLK and according to the logic level of the output (node N2) of the inverter 73. . Therefore, the exclusive NOR gate 64 outputs the input (node N1) of the inverter 73 in the master flip-flop 61 and the output (node N4) of the inverter 83 in the slave flip-flop 62 as shown in FIG. A match signal CNC1 is generated. The coincidence signal CNC1 holds the "H" level "L" level period of the second clock signal ICLK starting at time t _n, the second clock signal IC beginning further from the time t _{n + 1}
The “L” level is maintained during the “H” level of LK. As a result, the basic control signal CNT1 changes at time t
_It falls at _n , rises after a certain time T has elapsed, falls further at time t _{n + 1} , and rises after a certain time T has elapsed. As described above, the transition of the logic level of the input binary signal DI1 from “L” to “H” appears during the “L” level period T of the basic control signal CNT1 starting from the time t _n , and "H" to "L" of the binary signal DI1
The transition of the logical level to appears as a period T of the “L” level of the basic control signal CNT1 starting from the time t _{n + 1} .

The logic level of the enable signal EN is "H"
, The first control signal CT1a having the same waveform as the basic control signal CNT1 in FIG. 6 is supplied to the inversion buffer 41, and the second control signal CT1b having the inverted waveform of the basic control signal CNT1 is switched. 42. The inversion buffer 41 in FIG.
While the logic level of 1a is “L”, both the PMOS transistor 91 and the NMOS transistor 94 are cut off, so that the output to the signal line 30.1 is held in a high impedance state. The switch 42 is connected to the second
While the logic level of the control signal CT1b is "H",
Since both the PMOS transistor 101 and the NMOS transistor 102 are on, the signal line 30.1 and the common line 44 are short-circuited. That is, the basic control signal CNT
In a period T (see FIG. 6) in which the logical level of 1 is "L", the driving operation of the signal line 30.1 by the inversion buffer 41 is prohibited, and the switch 42 is closed. And
The logic level of the basic control signal CNT1 changes from "L" to "H".
, The logic level of the first control signal CT1a changes from “L” to “H”, and the logic level of the second control signal CT1b changes from “H” to “L”. At this time, the PMOS transistor 91 in the inversion buffer 41
And the NMOS transistor 94 are turned on. At this point, if the logic level of the input binary signal DI1 is “H”, the inversion buffer 41
The logic level of the output binary signal DO1 above 0.1 is set to “H”.
As to transition from the "L", through two NMOS transistors 93 and 94, it begins to conduct electric charge stored in the stray capacitance C to ground power supply V _ss. On the other hand, if the logic level of the input binary signal DI1 is "L" at the same time,
The inversion buffer 41 supplies the positive power supply V via two PMOS transistors 91 and 92 so that the logic level of the output binary signal DO1 on the signal line 30.1 changes from “L” to “H”. _The supply of charging current from _dd to the stray capacitance C starts. That is, the inversion buffer 41 selects the driving mode of the signal line 30.1 according to the logical level of the applied input binary signal DI1. The inversion buffer 41 has the signal line 30.1
Is driven, since the logic level of the second control signal CT1b is "L", the switch 42 is open.

FIG. 7 shows the operation of the first unit circuit 40.1 when the input binary signal DI1 has another waveform. The logic level of the input binary signal DI1 shown in FIG. 7 is "L" between time t _n-1 (not shown) and time t _n.
After that, “H” is held until after time t _{n + 1} . In this case, during the “H” level period of the second clock signal ICLK starting from the time t _{n + 1} , the logic level of the input (node N1) of the inverter 73 in the master flip-flop 61 and the logic level of the slave flip-flop 62 And the logic level of the output of the inverter 83 (node N4) matches, the logic level of the match signal CNC1 does not become “L”. Therefore, unlike the case of FIG. 6, the basic control signal CNT1 does not fall at the time t _{n + 1} . That is, the third clock signal YC
Even if the logic level of LK becomes “L” during the period T starting from time t _{n + 1} , the logic level of the basic control signal CNT1 remains “H”. Therefore, enable signal EN
Is "H", the input binary signal DI
When the logical level of 1 does not change, the driving operation of the signal line 30.1 by the inverting buffer 41 and the closing of the switch 42 are not performed, and the inverting buffer 4
1 keeps driving the signal line 30.1.

If the logic level of the enable signal EN is "L", the first and second control signals C and C are set regardless of the transition of the logic level of the input binary signal DI1.
The logic levels of T1a and CT1b are both "L". As a result, the inversion buffer 41 holds the output to the signal line 30.1 in a high impedance state, and the switch 42 is opened.

As described above, in the output buffer 13 shown in FIG.
Has been described, the operation of the other unit circuits 40.2 to 40. The same applies to the operation of N.

FIGS. 8A to 8C show the operation principle of the output buffer 13 shown in FIG. The logic level of the n-bit binary signal among the N-bit input binary signals DI1 to DIN changes from “H” to “L”, respectively, and the N-bit input binary signal DI1 to DIN has It is assumed that the logic level of the m-bit binary signal changes from "L" to "H". Correspondingly, the logical level of the n-bit binary signal of the N-bit output binary signals DO1 to DON changes from “L” to “H”, respectively, and the N-bit output binary signal DO1 M of DO1 to DON
The logical level of the binary signal of the bit transits from “H” to “L”. Here, m + n ≦ N.

FIG. 8A shows a state where m + n stray capacitances C having terminal voltages to be updated are separated from each other. The terminal voltage of each of the n capacitors out of the N stray capacitors C is 0 V, and the terminal voltage of each of the m capacitors is _Vdd . In this state, when the logical levels of the m + n-bit binary signals among the N-bit input binary signals DI1 to DIN transition, respectively, the inversion buffers in the m + n unit circuits corresponding to the m + n-bit binary signals. 4
One signal line driving operation is prohibited, and all the switches 42 in the (m + n) unit circuits are closed.

FIG. 8B shows a state in which one of the electrodes of each of the m + n capacitors C is all connected to the common line 44 when the m + n switches 42 are closed.
At this time, reallocation result from charges between via the common line 44 m + n pieces of capacitor C, m + n pieces of each of the terminal voltage V _c of the capacitor C _{is, V c = mV dd / (} m + n) ... ( 5) At this time, the terminal voltage of the n capacitors C is changed from 0V to V
_Although rising to _c, energy is not supplied from the positive power supply _Vdd .

FIG. 8C shows a state in which m + n capacitors C are separated from each other again, and m + n inverting buffers 41 are each performing a signal line driving operation. m
The charges stored in the capacitors C are supplied to the ground power supply V _ss by the m inversion buffers 41. The n inversion buffers 41 supply a charging current from the positive power supply _Vdd to the n capacitors C. In this case, n pieces of the capacitor C of each of the terminal voltage has the formula (5) from the voltage V _c expressed in "H" level voltage V _dd
From the positive power supply V _dd , the above equation (3)
In the represented energy amount E _t of it is supplied. Equation (5)
The substituted into equation _{(3), / E t =} n 2 CV dd 2 (m + n) ... (6) is obtained. Comparing Equations (4) and (6), FIG.
According to the output buffer 13 of, it can be seen that the energy consumption E _t of the positive power supply V _dd is reduced to a conventional n / (m + n) times. Here, the energy consumption ratio K = n / (m + n) takes a value between 0 and 1. However, the most probable value of the energy consumption ratio K is 0.5. That is, the power consumption of the output buffer 13 of FIG. 2 is reduced to about half of the power consumption of the output buffer 5 of FIG.

The delay time T of the delay circuit 53 in FIG.
It is desirable to make the setting variable according to the power supply voltage, the operating temperature, and the like. FIG. 2 shows a circuit composed of a differentiating circuit for detecting a voltage change of the common line 44 and a comparator.
After confirming that there is no change in the voltage of the common line 44, the basic control signal C shown in FIG.
The rise of NT1 may be automatically hastened. Also, a circuit composed of a resistor for detecting the level of the current flowing through each switch 42 and a comparator is added to the output buffer 13 in FIG. 2, and it is confirmed that the level of the current flowing through each switch 42 is reduced. Then, the rise of the basic control signal CNT1 in FIG. 6 may be automatically advanced.

The N inversion buffers 41 shown in FIG.
Can be replaced with forward buffers. The N inverting buffers 41 or the N non-inverting buffers drive the corresponding signal lines after setting all outputs to a high impedance state once regardless of the presence or absence of the transition of the logic level of the input binary signal. Is also good.

The application of the present invention to the output buffer 13 of the processor 10 for driving the data bus 30 in FIG. 1 has been described. The configuration of FIG. 2 can be used as it is for the three-state output buffer 23 of each memory 20 in FIG. In the case of a unidirectional bus buffer for transmitting a multi-bit binary signal to an address bus or a control bus, an enable signal EN shown in FIG.
The AND gates 67 and 68 may be omitted. Note that the present invention is also applicable to signal transmission between circuit blocks via an internal bus in one LSI.

[0035]

As described above, according to the present invention, by connecting all the (m + n) signal lines whose logic levels are about to transition to one common line via switches, the logic level can be changed. "L" to "H" voltage of the n signal lines trying to transition to the after pulled to an intermediate voltage V _c without power consumption, the voltage of the n signal lines from the intermediate voltage V _c "H" Since the supply of energy for further raising the voltage to the level of the voltage _Vdd is realized by each buffer, the power consumption in the signal transmission circuit is significantly reduced as compared with the conventional case.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration example of a microprocessor system using a signal transmission circuit of the present invention as an output buffer.

FIG. 2 is a block diagram illustrating an example of an internal configuration of an output buffer included in the processor in FIG. 1;

FIG. 3 is a circuit diagram showing an internal configuration of a clock generator in FIG. 2;

FIG. 4 is a circuit diagram showing an internal configuration of a control circuit in one output buffer unit circuit in FIG. 2;

FIG. 5 is a circuit diagram showing an internal configuration of each of an inversion buffer and a switch in the output buffer unit circuit.

FIG. 6 is a time chart showing the operation of the output buffer unit circuit.

FIG. 7 is a time chart showing another operation of the output buffer unit circuit.

FIGS. 8A to 8C are conceptual diagrams for explaining the operation principle of the output buffer of FIG. 2;

FIG. 9 is a block diagram showing a configuration of a conventional output buffer.

[Description of Codes] 5, 13 Output buffer 6, 41 Inversion buffer 7.1 to 7. N signal line 30 data bus 30.1-30. N signal line 40.1-40. N unit circuit 42 switch 43 control circuit 44 common line 45 clock generator 53 delay circuit 61 master flip-flop 62 slave flip-flop 63 latch 64 exclusive NOR gate C floating capacitance DI1 to DIN N-bit input binary signal DO1 to DON N-bit output binary signal

Claims (4)

(57) [Claims] 1. A signal transmission circuit for transmitting a given N-bit (N is an integer of 3 or more) binary signal to N signal lines, comprising: N unit circuits; A common line, wherein each of the N unit circuits corresponds to one of the given N-bit binary signals.
A buffer for driving a corresponding one of the N signal lines based on a binary signal of bits; and a buffer interposed between the corresponding one signal line and the common line. A switch, detecting the presence / absence of a transition of the logic level of the corresponding 1-bit binary signal, and prohibiting the signal line driving operation of the buffer when there is a transition of the logic level of the binary signal; Control means for controlling the buffer and the switch so as to open the switch and drive the corresponding one signal line to the buffer after closing the switch. Transmission circuit. 2. The signal transmission circuit according to claim 1, wherein the control unit is configured to determine whether the logical level of the binary signal has not changed.
A signal transmission circuit having a function of controlling the buffer and the switch so that the buffer drives the corresponding one signal line without closing the switch. 3. The signal transmission circuit according to claim 1, wherein the control means holds the corresponding one-bit binary signal in synchronization with a given clock signal; Means for detecting a match / mismatch of a logical level between a 1-bit binary signal and a corresponding 1-bit binary signal among newly provided N-bit binary signals. Signal transmission circuit. 4. The signal transmission circuit according to claim 1, wherein the control unit prohibits a signal line driving operation of the buffer and switches the switch when a logical level transition of the binary signal occurs. A signal transmission circuit comprising means for closing and opening the switch after a predetermined time to drive the corresponding one signal line to the buffer.