JP3181351B2 - Digital video signal processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video signal processing device used for a broadcast signal processing equipment such as a broadcasting station, and more particularly to an improvement for a high-vision system.

[0002]

2. Description of the Related Art Generally, a digital video signal processing apparatus used in a broadcasting station or the like is composed of individual dedicated processing units according to the purpose of processing a video signal. For this reason, as the number of processing items increases, the number of units also increases, and the entire apparatus becomes large. Along with this, a great deal of labor is required for construction work for realizing target processing functions such as device design, maintenance, and combination of units.

[0003] Therefore, recently, a digital video processing apparatus which can realize a target processing function by software and does not require a physical connection work has been put into practical use. This device is equipped with a plurality of processing units and a network unit. Each processing unit is provided with a program corresponding to the processing item of the video signal from the outside to realize the desired processing function. By providing a program according to the purpose of signal processing, a connection line connecting the functions obtained by the respective arithmetic processing units is realized.

On the other hand, in order to improve the quality of broadcast video,
Hi-vision systems have been developed. The Hi-Vision system requires an extremely high sampling frequency and various processing functions as compared with the conventional NTSC system or the like. Broadcasting stations and the like tend to handle both the high definition video signal and the conventional video signal. However, the conventional digital video signal processing apparatus has a low degree of freedom in arithmetic processing capability, function change, and system change, and cannot cope with the Hi-Vision system.

[0005] Against this background, there is a strong demand that the digital video signal processing apparatus using software be developed to be compatible with the high-definition system and be used in combination with the conventional system.

[0006]

As described above, the conventional digital video signal processing device has a low processing capability, a small degree of change in functions and a low degree of system change, and cannot cope with the Hi-Vision system.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and can realize high-speed and advanced arithmetic processing, and can improve the degree of freedom in changing functions and systems, thereby achieving a high-vision system. It is an object of the present invention to provide a digital video signal processing device that can also deal with the problem.

[0008]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a method for externally connecting a plurality of programmable arithmetic processing units and a connection form of each programmable arithmetic processing unit by a network unit through a host control unit. In the digital video signal processing device configured so that the video signal can be set freely, the programmable arithmetic processing unit has two input units to which the video signal is supplied, respectively, and converts the video signal input to the input unit. A plurality of operands for performing arithmetic processing according to a program and deriving the result, each input unit to which each output signal from each of the plurality of operands is supplied, and two video signals from the network unit can be supplied. An output unit and a final output respectively corresponding to each input unit and the input units of the plurality of operands A selector for deriving one of the input signals as a final output signal, the selector having: Program control means for controlling the program of the operands and selectors in accordance with instructions from the host control means, and the contents of arithmetic processing of the operands and the connection form of each operand by the selector can be freely set from the outside through the host control means. And at least one instruction has an operation speed of の of the high definition rate.

[0009]

In the digital video signal processing apparatus having the above-described configuration, the plurality of programmable arithmetic processing units each have an operation speed of 1/2 of the HDTV rate for one instruction. Therefore, real-time processing is possible even for a high-vision video signal, and it is also possible to support a conventional video signal such as NTSC.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows the overall configuration of a digital video signal processing apparatus according to the present invention.
(N) (n is arbitrary) indicates that the input channels are 16,
The output channels are 16 signal processing clusters (each channel is 16-bit parallel, and so on). Each of the clusters 1 (1) to 1 (n) is connected in cascade,
Through a (local area network) 2, the host computer 3 controls switching to a processing function and a connection line in accordance with a command input from an operator.

FIG. 2 shows the internal structure of the above-mentioned cluster (here, 1 (1) is shown as a representative). The network 4 has 16 programmable operation units (PUs) 5 (1) to 5 (1).
5 (16), a host controller 6 is provided.

The network 4 has 16 external input channels (IN1 to IN16) and 1 internal input channel.
6 (IN17 to IN32), 16 external output channels
(OUT1 to OUT16), 32 internal output channels
(OUT17 to OUT48), the host controller 6
Any input channel can be connected to any output channel in response to a control signal from.

The above-mentioned programmable operation units 5 (1) to 5 (5)
(16) is a video rate video signal processing LSI which has the same configuration and can be applied from the NTSC system to the Hi-Vision system, receives output data of two predetermined internal output channels of the network 4, and designates it by the host controller 6. The arithmetic processing is performed in accordance with a program to be executed, and the processing result is sent to a predetermined internal input channel of the network 4. Especially in video signal processing,
Various operations are performed with a cycle of 27 ns (= 1 / 37.125 MHz) and 24-bit precision.

The host controller 6 connects the host computer 3 to the network 4 and the programmable processors 5 (1) to 5 (16) through the LAN 2.

FIG. 3 shows a specific configuration of the above-described programmable operation unit (here, 5 (1) is shown as a representative). Reference numeral 7 denotes a DSP (digital signal processor) unit for performing digital signal processing. 8 is a DSP unit 7
A program memory 9 for storing a processing function and a connection line program to be supplied to the DSP 9; and a data memory 9 for appropriately storing data required in the processing of the DSP unit 7. The data memory 9 has two systems, DM-A and DM-B.
Each of them can store up to 1 Mbyte (corresponding to one field of a Hi-Vision signal) and can be used as a look-up table (LUT) in a non-linear arithmetic unit. FIG. 4 shows a specific configuration of the DSP unit 7.

In FIG. 4, the input processing units 10 (1), 1
0 (2) inputs the 16-bit data IN-A and IN-B of the two internal output channels of the network 4 and performs synchronization flag processing. The synchronization flag is used to synchronize with the preceding circuit, and is used at 8000H (-327).
68). Therefore, the data is 7FFFH
(32767) to 8001H (-32767) is in a possible range. The outputs of the input processing units 10 (1) and 10 (2) are sent to two external input channels (16 bits) of the selector 11.

The selector 11 has two external input channels, nine internal input channels, one external output channel, and fourteen internal output channels for data output. Is selectively switched to an arbitrary channel output.

The output processing section 12 takes in the output data of one channel (16 bits) of the external output channel of the selector 11, performs a synchronization flag process, and sends it out to one internal channel of the network 4. Here, as the synchronization flag processing, when the synchronization is off, the data is replaced with 8001H when the data is 8000H, and when the synchronization is on, the data is forced to 801H.
Replace with 00H.

ALU (arithmetic operation unit) 13 (1), 1
3 (2) takes in the output data of the two channels (24 bits) selected by the selector 11 and performs the arithmetic processing specified by the given program data, and outputs the processing result (24 bits) to the selector 11 To one internal input channel. As the arithmetic processing,
In addition to the usual arithmetic and logic operations, it includes functions of maximum value / minimum value and absolute value calculation often used in TV signal processing, and is processed in 24 bits. If an overflow occurs during a 24-bit operation, it is clipped to the maximum positive or negative value.

More specifically, as shown in FIG. 5, one channel input is a variable delay A1 having a maximum of three taps.
The delay is compensated so as to coincide with the other channel input timing, and is supplied to the arithmetic unit A2 together with the other channel input. Variable amount of variable delay A1 and arithmetic unit A2
Are switched according to the program data. The operation result of the operation unit A2 is supplied to the register bank A3.

The register bank A3 includes a plurality (here, six) of 24-bit operation registers. One (or two) of them is the global register A31
And the retained data becomes the ALU output,
The other four registers are used as local registers A32, and the data held by the registers is used by the arithmetic unit A2 as needed. The global register A31 functions as a pipeline register.

AU (address operation unit) 14 (1), 14
(2) is used for address calculation for accessing the data memory 9 or for waveform generation. For example, one can perform a horizontal address calculation and the other a vertical address calculation. The output address data of one channel (24 bits) selected by the selector 11 is fetched, the address operation specified by the given program data is performed, and the processing result (24 + 6 bits) is output to the internal input channel of the selector 11. Send to one system.

More specifically, it is configured as shown in FIG. 6, and has an address generation unit B1 therein. The address generator B1 includes an address calculator B11 and an address register bank B12. The address register bank B12 has six operation registers, and together with the address operation unit B11, can perform operations such as addition, subtraction, and １ ／. The operation content is set by the program data.

The address data generated by the address generator B1 is supplied to an internal selector B2 together with external input address data (internal output of the selector 11). The internal selector B2 takes in internally generated address data and external input address data, and selectively derives one of them to the comparator B3 and the address processing section B4 according to the program data.

The comparator B3 compares the input address data with a preset specified value (for example, a maximum or minimum limit value), and if it exceeds the specified value, sets a flag and sends it to the address processing unit B4.

This address processing section B4 is replaced with a replacement processing section B4.
1, a shifter section B42 and a mode processing section B43. The replacement processing unit B41 is used, for example, for clipping, and replaces the input address data with a predetermined value according to the flag from the comparator B3. The shifter section B42 is a barrel shifter capable of bit shifting in eight modes, and can arbitrarily set the decimal point position of 24-bit input address data.

The mode processing unit B43 performs through, plus 1, right 1 for the integer part shifted by the shifter unit B42.
Bit shift and LSB processing can be selected, and through and minus can be selected for the decimal part. The selection is performed by program data, and may be fixedly selected or automatically selected based on the calculated LSB of the integer part. The processed data is output after being divided into an integer part of 20 bits and a decimal part of 6 bits. The 6-bit fractional part is used for calculation of adjacent four-point interpolation at the time of reduction / enlargement in digital special effects.

With this mode processing, 4
Calculation of point interpolation can be easily realized. In particular, when sub-sampling is performed at a half of the sampling frequency as in the case of a Y signal of a high-definition television, the "automatic selection mode using the LSB of the integer part" is effective. AU14 (1), 1 by this structure
When 4 (2) is used, the data memory 9 can be accessed in parallel with the data operation.

MPY (multiplier) 15 (1), 15 (2)
Uses a macro cell of 16 × 16 = 32 bits, and can extract 24 bits from 32 bits in three modes. The output data of the two channels (16 bits) selected by the selector 11 are fetched, and both input data are multiplied in a format specified by the given program data.
The result of the operation is input to the internal input channel (1
(6 bits) Transmit to one system.

More specifically, as shown in FIG. 7, one channel input is a variable delay C1 having a maximum of three taps.
The delay is compensated so as to coincide with the other channel input timing, and is supplied to the multiplier C2 together with the other channel input. Variable amount of variable delay C1 and multiplier C2
Are switched according to the program data. The operation result of the multiplier C2 is supplied to the register bank C3.

The register bank C3 includes a plurality (here, six) of 24-bit operation registers. One (or two) of them is the global register C31
And the retained data becomes the MPY output,
The other four registers are used as local registers C32, and the held data is used for the operation of the multiplier C2 as necessary. The global register C31 functions as a pipeline register.

The variable delays 16 (1) and 16 (2) are
The output data of one channel (16 bits) selected by the selector 11 is fetched, the timing is adjusted by 16 taps, and the data is sent to one internal input channel (16 bits) of the selector 11. It is mainly used for delay modulation during multiprocessor operation. Each delay 1
If the selector 11 is assembled so that 6 (1) and 16 (2) are connected in cascade, a 32-tap delay can be realized.

Data memory I / O (interface)
Reference numeral 17 denotes output data of one channel (16 bits) selected by the selector 11 and channels (20 bits)
One line of output address data is fetched, and writing and reading of the data memory 9 are performed according to the program data. The read data and address data are stored in the selector 1
It is transmitted to one internal input channel (16 bits).

Specifically, as shown in FIG.
6 bits) and address data (20 bits) are bit-shifted by shifters D1 and D2 as necessary, and one of the bank areas of the data memory 9 is selected by the selectors D3 and D4 according to the program data to write or write. Perform reading.

Here, the data memory 9 has a two-bank configuration (DM-A, DM-B).
It has an address space of KW (1024 KB). At the time of high definition, it can correspond to data of 1/2 field in word and 1 field in byte. With this configuration, for example, a process of reading a motion vector calculated using one data memory (field memory) from the other data memory can be realized in real time, or a conversion process of image signal data can be performed as a lookup table (LUT). It is possible to realize a process of performing the processing in real time.

The selector 11, the ALU 13 (1), 1
3 (2), AU14 (1), 14 (2), MPY15
(1), 15 (2), variable delay 16 (1), 16
(2) The data memory I / Os 17 (hereinafter collectively referred to as operands) are all connected to the internal bus 18. A host I / O 19 and a sequencer 20 are further connected to the internal bus 18.

The host I / O 19 is a host controller 6
Is used to connect the operands of the host computer 3 and the DSP unit 7 to each other. It has two banks of 16 W × 16 bit register groups for transfer with the host.

One bank is suitable for the host, and the two banks are switched by operating the MSB of the 0th register. In addition, by inserting a program start address in the 0th register, a plurality of operations are written in one program memory 8, and only the start address is switched, so that the functions can be switched instantaneously. Normally, such a switching operation is performed in synchronization with vertical blanking and can be performed without affecting the validity period of a video, and the synchronization operation by a plurality of programmable arithmetic units can be easily performed. Can be.

The sequencer 20 is a central part of the control mechanism. The sequencer 20 employs a microprogram control method for performing instruction latch, decoding, branch control, operand control, and the like by using the program memory 8. It has a structure suitable for video signal processing, such as no pipeline operation and parallel operation of operands. The program is stored in an external program memory 8 and operates in a three-stage pipeline of fetch, decode, and execution in one cycle of 27 ns.

The program memory 8 is switchable between two modes of external 32KW and internal 64W, and the bit width of the microprogram is set to 48 bits. In the external mode, the internal program RAM is used as a cache when a branch instruction is generated, so that a pipe break does not occur even during a branch.

The structure of the 48-bit microinstruction includes a SEQ instruction for performing branch control, a standard configuration instruction in which an FUNC instruction for performing operation control can be independently set in one instruction, and a full-field instruction having an immediate value as an operand. There are two types. The SEQ instruction, unlike a general-purpose processor, has a three-branch structure of repeat, continue, and jump, and repeats the characteristics of image signal processing that often repeats the same processing for each pixel, and conditional branches using the same signal as the operation flag. Are reflected in the continuation and the jump.

The SEQ command includes an RST command for starting a program and a P command for a subroutine.
When handling time-division multiplexed signals such as USH, POP instructions, and standard TV component signals at a high definition rate, F for controlling all operands simultaneously.
There is an NC instruction.

Here, the program memory 8 and the sequencer 20 are conceptually configured as shown in FIG. 9 and look-up tables LUT1 to LUT for each operand.
9 is provided. Each table stores program data for each function. The sequencer 20 identifies the function index data for each table from the host instruction, reads the corresponding program data from each table, and sends out the corresponding program data to each operand through the internal bus 18. The sequencer 20 can also rewrite function-specific program data in each table according to a control signal.

As described above, by specifying one of the control tables for each operand by the index, 1
An index for a plurality of operands in an instruction is realized without increasing the instruction bit width. With this instruction, R
At the time of time axis multiplexed low-speed signal processing such as a GB signal, processing for each signal of RGB can be changed,
One DSP unit can handle this.

In the DSP unit 7, two data formats of 16 bits and 24 bits are mixed. There are two types of data format conversion during this period, the standard transfer mode and the extended transfer mode, and sufficient accuracy can be ensured.

For example, in the standard transfer mode, as shown in FIG. 10, 4-bit code extension data is added before 16-bit data, and 4-bit 0 data is added after that.
Convert to 4-bit data format. After the operation, 16-bit data is extracted by truncating the front and rear bits. In the extended transfer mode, as shown in FIG.
It is divided into bits, and a non-writable area corresponding to 16 bits is provided in the middle, and converted into a 24-bit data format. After the operation, only the 4 bits before and after are extracted and converted into 8-bit data.

Although not described in detail, the DSP unit further includes a line memory drive circuit, a program debug support circuit, and a synchronous circuit for parallel operation of a plurality of processors. Further, a variable pipeline structure which is a feature of the present invention will be described in detail.

In the conventional digital video signal processing device, a large number of arithmetic units (operands) having different functions are connected by a fixed path to form a pipeline. Such a circuit may perform only one type of signal processing. However, when a plurality of functions are realized by pressing switches according to an operation on an operation panel, circuits corresponding to the number of functions have been prepared.

In order to cope with a plurality of different functions by a single circuit by changing the connection, the connection of a plurality of arithmetic units is made to be a variable pipeline structure in which the number of pipes can be changed. As described above, the variable delays A1 and C1 are provided on one operand input line, and the register banks A3 and C3 are provided on the output line.

According to this structure, the selectors 11 can connect any of the arithmetic units. For example, the functional block of output = (input 1) + (constant) × (input 2) is as shown in FIG.
This is realized by connecting the selector 11 as shown in FIG. 12B using (1) and the MPY 15 (1). Further, the functional block of output = (input 1) × (constant 1) + (input 2) × (constant 2) is as shown in FIG. 12 (c).
Are connected as shown in FIG. 12 (d).

As can be seen from FIG. 12, two different types of arithmetic processing can be realized by a single circuit by changing the connection. That is, an arbitrary circuit can be realized by adopting the variable pipeline structure. In FIG. 12A, two pipes,
In (c), there are three pipes, and the number of pipes can be arbitrarily set. In order to absorb the path difference (difference in the cumulative number of latches) generated when this connection is changed, the input variable delay A
1, C3 works effectively.

Therefore, by employing the above-mentioned variable pipeline structure, an arbitrary circuit can be realized by a single circuit by changing the connection of the selector 11, thereby improving versatility and increasing the use efficiency of the arithmetic unit. it can.

Meanwhile, in a high-speed CPU or signal processor, there are a software method using an internal interrupt and a hardware method using an emulator as a debugging method. However, in the case of a signal processor that attaches importance to real time processing such as processing a TV digital signal, there is a possibility that a software method may not completely correspond to a state where debugging is not performed. On the other hand, a hardware method using an in-circuit emulator is not realistic in view of a multiprocessor configuration and an increase in clock frequency. As a result, conventionally, debugging has to be performed by judging from an image or analyzing the output result off-line via an image memory.

Therefore, here, hardware necessary for debugging is installed in the DSP unit 7 in advance so that the debugging operation can be easily realized. FIG. 13 shows the configuration.

In FIG. 13, reference numeral 8 denotes the aforementioned program memory, and reference numeral 20 denotes a sequencer. This sequencer 20
, An address latch F1 and an instruction latch F2 are provided. To fetch a program instruction, the sequencer 20 latches an address in the address latch F1, accesses the program memory 8 and fetches the instruction into the instruction latch F2, decodes the fetched instruction, and performs branch control using an operation flag or the like.

The address output to the address latch F1 is sent to the comparator F3 at the same time, and is compared with the preset contents of the breakpoint register F4. If a match is determined in this comparison, a match flag is set as the output of the comparator F3. When the match flag is set, the sequencer 20 stops the operation, stops all clocks, and sets the operand (A
The updating of the contents of the output register of the LU 13 (1) or the like is stopped. At that time, through the external interface F5,
The operand output register enables data to be read from outside the DSP unit 7.

In the above configuration, if the program address to be interrupted is set in advance in the breakpoint register F4, the comparator F3 compares the breakpoint address with the accessed program address. When the comparator F3 determines the coincidence, the output register of the operand reads external data through the external interface F5.

Therefore, by interrupting the processing at an arbitrary program location and checking the output register of the internal operand, it is possible to easily realize real-time debanging processing. Some applications of the digital video signal processing device having the above configuration will be described.

FIG. 14 shows a functional configuration in the case where key mixing is performed in one cluster for two digital video signals A and B of the HDTV system. The video signals A and B are respectively distributed to two systems as luminance signals Y1 and Y2 and color signals as Pr and Pb. In this case, since the cluster operation speed is 1/2 of the HDTV rate, real-time processing is performed at the HDTV rate by parallel calculation.

In FIG. 14, K is a key signal. The inside of the cluster is divided into four processings of Y1 processing, Y2 processing, Pr processing, and Pb processing.
(1) to (3) are used, and an arithmetic unit 5 is used for Y2 processing.
(4) to 5 (6) are used, and Pr (5) to 5 (7) to
5 (9) is used, and 5 (10) to 5 (1) are used for Pb processing.
2) is used.

In the Y1 processing, 5 (1) is a multiplier,
(2) is programmed to a subtractor and multiplier, and (3) is programmed to an adder. By network 4 (not shown)
5 (1) is supplied with K and A-Y1, 5 (2) is supplied with K and BY-1, and 5 (3) is the output of each of 5 (1) and 5 (2). Supplied. That is, 5
(1) derives AY1 when K = 1, and 5 (2)
When = 0, BY-1 is derived, and 5 (3) adds and synthesizes the operation outputs of 5 (1) and 5 (2). by this,
Key mixing signals of A-Y1 and BY-1 are obtained.

In the Y2 processing, 5 (4) is a multiplier, 5
(5) is programmed to a subtractor and a multiplier, and 5 (6) is programmed to an adder. By network 4 (not shown)
5 (4) is supplied with K and A-Y2, 5 (5) is supplied with K and BY-2, and 5 (6) is the output of each of 5 (4) and 5 (5). Supplied. That is, 5
(4) derives A-Y2 when K = 1, and 5 (5)
When = 0, BY2 is derived, and 5 (6) adds and synthesizes the operation outputs of 5 (4) and 5 (5). by this,
Key mixing signals of A-Y2 and BY-2 are obtained.

In the Pr processing, 5 (7) is a multiplier, 5
(8) is programmed into a subtractor and a multiplier, and (9) is programmed into an adder. By network 4 (not shown)
5 (7) is supplied with K and A-Pr, 5 (8) is supplied with K and B-Pr, and 5 (9) is the output of each of 5 (7) and 5 (8). Supplied. That is, 5
(7) derives A-Pr when K = 1, and 5 (8)
When = 0, B-Pr is derived, and 5 (9) adds and synthesizes the operation outputs of 5 (7) and 5 (8). by this,
A-Pr and B-Pr key mixing signals are obtained.

In the Pb processing, 5 (10) is a multiplier,
5 (11) is programmed to a subtractor and a multiplier, and 5 (12) is programmed to an adder. The network 4 (not shown) supplies 5 (10) with K and A-Pb,
(11) is supplied with K and B-Pb, and 5 (12) is supplied with respective operation outputs of 5 (10) and 5 (11). That is, 5 (10) derives A-Pb when K = 1, 5 (11) derives B-Pb when K = 0, and 5 (10).
(12) adds and synthesizes the operation outputs of 5 (10) and 5 (11). As a result, key mixing signals of A-Pb and B-Pb are obtained.

FIG. 15 shows a functional configuration when key mixing is performed in one cluster for two digital video signals A and B of the NTSC system. in this case,
Since the signal rate is as low as 1/4 of the cluster operation speed, the luminance signal and the chrominance signal can be collectively processed.

In FIG. 15, three programmable arithmetic units 5 (1) to 5 (3) are used in a cluster, and 5
(1) is a multiplier, (2) is a subtractor and a multiplier,
(3) is programmed into the adder. The network 4 (not shown) supplies 5 (1) with K and A, 5 (2) with K and B, and 5 (3) with 5
Each operation output of (1) and 5 (2) is supplied. That is, 5 (1) derives A when K = 1, and 5 (2)
B is derived when = 0, and 5 (3) is 5 (1) and 5 (3)
Each operation output of (2) is added and synthesized. by this,
A and B key mixing signals are obtained.

FIG. 16 shows a functional configuration in a case where a chroma key is generated by one cluster for the color signals Pr and Pb in the digital video signal of the Hi-Vision system.

In this case, three programmable operation units 5
Using (1) to (3), Pr and Pb are respectively supplied to 5 (1) and 5 (2) by a network 4 (not shown), and 5 (1) and 5 (2) are supplied to 5 (3). Are supplied.

5 (1) and 5 (2) have the same configuration.
P input by internal MPYs 15 (1) and 15 (2)
After amplifying the product by multiplying r and Pb by a coefficient, ALU13 (1)
Add the two to generate a chroma signal according to a table program stored in the data memory 9. 5 (3) is an internal ALU 13 (1) which adds the chroma signals obtained by 5 (1) and 5 (2) and generates a chroma key signal according to a table program stored in the data memory 9.

This functional configuration can also be applied to a case where a chroma key is generated by one cluster for the color signals CR and CB in the digital video signal of the NTSC system. The functional configuration diagram is omitted. FIG. 17 shows a part of a matrix function configuration for synthesizing and outputting RGB of a Hi-Vision digital video signal into three systems in one cluster.

In the high vision system, since the data rate is high, it is necessary to calculate independently for each of RGB. In this case, six programmable operation units 5 (1) to
5 (6) is used. 5 (1), 5 (3), 5 (5) is 2
The inputs are amplified by the MPYs 15 (1) and 15 (2), respectively, and further added and output by the ALU 13 (1). 5
(2), 5 (4), and 5 (6) input one input to MPY15.
Amplification is performed in (1), and the ALU 13 (1) adds and outputs the other input.

That is, R and G are added by 5 (1), and B is added by 5 (2) to obtain the first system OUT.
Sent to 1. R and G are added by 5 (3), and B is added by 5 (4) and sent to the second system OUT2. R and G are added by 5 (5), and further 5
In (6), B is added and sent to the third system OUT3. Note that the circuit of FIG. 17 performs processing at a data rate of １ ／ that of the high-vision system, and in fact, another circuit having the same configuration as the circuit of FIG. 17 is required.

On the other hand, the data rate is low in the NTSC system, so that the RGB can be processed collectively.
FIG. 18 shows the functional configuration, in which RGB signals are supplied to arithmetic units 5 (1) and 5 (2). In 5 (1), the RGB inputs are distributed to two systems, and MPY1
After amplification in 5 (1) and 15 (2), ALU13
The constants are added in (1) and 13 (2) to become the outputs of the first and second systems OUT1 and OUT2. In 5 (2), the RGB input is amplified by MPY15 (1), and
The constant is added in LU13 (1), and the third system OUT3 is added.
Output.

As is clear from the above applications, high-speed and high-level arithmetic processing of one cluster is realized, and the degree of freedom for function change and system change is improved. It can correspond to the method.

It should be noted that each of the above specific examples does not limit the present invention, and it is needless to say that various modifications can be made without departing from the scope of the present invention.

[0077]

As described above, according to the present invention, it is possible to realize high-speed and high-level arithmetic processing, and to improve the degree of freedom in changing functions and systems, thereby enabling a high-definition digital system. A video signal processing device can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration as an embodiment of a digital video signal processing device according to the present invention.

FIG. 2 is a block diagram showing a specific configuration of a cluster according to the embodiment.

FIG. 3 is a block diagram showing a specific configuration of the programmable operation unit of the embodiment.

FIG. 4 is a block diagram showing a specific configuration of the DSP unit of the embodiment.

FIG. 5 is a block diagram showing a specific configuration of the ALU of the embodiment.

FIG. 6 is a block diagram showing a specific configuration of the AU of the embodiment.

FIG. 7 is a block diagram showing a specific configuration of the MPY of the embodiment.

FIG. 8 is a block diagram showing a specific configuration of a data memory I / O of the embodiment.

FIG. 9 is a conceptual diagram showing a conceptual configuration of a program memory and a sequencer of the embodiment.

FIG. 10 is a view showing a data format in a standard transfer mode in the DPS unit of the embodiment.

FIG. 11 is a view showing a data format of an extended transfer mode in the DPS unit of the embodiment.

FIG. 12 is a functional configuration diagram for explaining a variable pipeline structure of the embodiment.

FIG. 13 is a block diagram showing a hardware configuration for performing a debugging process of the embodiment.

FIG. 14 is an exemplary block diagram showing a key mixing function configuration of a high-vision system as an application of the embodiment.

FIG. 15 shows NTSC as an application of the embodiment.
FIG. 2 is a block diagram showing a key mixing function configuration of a system.

FIG. 16 is a block diagram showing a configuration of a high-definition chroma key generation function as an application of the embodiment.

FIG. 17 is an exemplary block diagram showing a high-vision RGB matrix function configuration as an application of the embodiment;

FIG. 18 shows NTSC as an application of the embodiment.
FIG. 1 is a block diagram showing a functional configuration of an RGB matrix.

[Explanation of symbols]

1 (1) to 1 (n) ... signal processing cluster, 2 ... LAN,
3 host computer, 4 network, 5 (1)
5 to (16): Programmable arithmetic unit (PU), 6: Host controller, 7: DSP unit, 8: Program memory, 9: Data memory, 10 (1), 10 (2)
... input processing unit, 11 ... selector, 12 ... output processing unit, 1
3 (1), 13 (2)... Arithmetic logic unit (ALU), 1
4 (1), 14 (2)... Address operation unit (AU), 15
(1), 15 (2)... MPY (multiplier), 16 (1),
16 (2): variable delay, 17: data memory I /
O, 18 internal bus, 19 host I / O, 20 sequencer.

Continuing from the front page (72) Inventor Hideki Saito 1, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Inside the Toshiba Komukai Plant (72) Inventor Ryuichiro Tomita 1-Kosuka-Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Stock (72) Inventor Nobuyuki Yagi 1-1-10 Kinuta, Setagaya-ku, Tokyo Japan Broadcasting Research Institute, Japan (72) Kazuo Fukui 1-110-11 Kinuta, Setagaya-ku, Tokyo Japan Within the Broadcasting Corporation Research Institute of Broadcasting (72) Inventor Kazumasa Enami 1-10-11 Kinuta, Setagaya-ku, Tokyo Japan Broadcasting Corporation Research Institute of Broadcasting Technology (56) References JP-A-1-206777 (JP, A) JP JP-A-1-206778 (JP, A) JP-A-1-236383 (JP, A) JP-A-5-260374 (JP, A) JP-A-5-260376 (JP, A) JP-A-5-260377 (JP , A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H04N 5/262-5/275

Claims (6)

(57) [Claims] 1. A plurality of programmable arithmetic processing units each having two input units to which a video signal is supplied, performing arithmetic processing on a video signal input to the input unit according to a program, and deriving a result thereof; An input unit to which each output signal from each of the plurality of programmable arithmetic processing units is supplied; an input unit to which a plurality of video signals can be respectively supplied from the outside; and an input unit of the plurality of programmable arithmetic processing units And a plurality of output units for deriving a final output, respectively, and can supply the signals of the respective input units to the plurality of programmable arithmetic processing units in a programmable manner. A network unit for deriving a signal as a final output signal; and a program for the plurality of programmable arithmetic processing units and a network unit for external instructions. Therefore, the digital video signal processing device comprises a host control means for controlling, and is configured such that the content of the arithmetic processing of the programmable arithmetic processing unit and the connection form of each programmable arithmetic processing unit by the network unit can be freely set from the outside. The programmable arithmetic processing units each have two input units to which a video signal is supplied,
A video signal input to the input unit is subjected to arithmetic processing according to a program, and a plurality of operands for deriving the result; input units to which output signals from the plurality of operands are respectively supplied; And an output unit for deriving a final output, the output unit corresponding to the input unit of each of the plurality of operands, and one output unit for deriving a final output. A selector that can supply a signal of the unit to the plurality of operands, and derives any one of the input signals as a final output signal; and a program that controls a program of the plurality of operands and the selector according to an instruction from the host control unit. Control means, and the contents of arithmetic processing of the operand and each operation by the selector. Constructed a command of connection form so as to be set freely from the outside through the host control means, the digital video signal processing apparatus characterized by having half the operating speed of the HDTV rate for at least one instruction. 2. The digital video signal processing device according to claim 1, further comprising a parallel operation processing means for causing said programmable operation processing unit to perform a high-speed video signal divided into at least two systems in parallel operation processing. apparatus. A variable delay provided in one of the video signal input sections of the operand; and a delay amount of the variable delay adjusted by the program control means to control the other video signal input section. A variable pipeline structure comprising delay amount control means for matching input timings, and an output register provided at an output section of the operand and holding output data, wherein the selector can cascade-connect any operand. The digital video signal processing device according to claim 1, wherein: 4. A program memory for storing a plurality of programs corresponding to the plurality of operands in a table, and a program stored in a corresponding table from the program memory based on an instruction from the host control means. 2. A digital video signal processing device according to claim 1, further comprising: a sequencer for reading out the data and sending the read data to a target operand. 5. A program control means comprising: a breakpoint register in which an address value is previously stored as a breakpoint; and a comparator for comparing the address value stored in the register with an address value of the sequencer for the program memory. And debugging means for stopping the operation of the sequencer and stopping the updating of output data of each operand by stopping the operation of the sequencer when the coincidence between the two address values is detected by the comparator. The digital video signal processing device according to claim 4. 6. The digital video signal processing device according to claim 1, wherein said programmable arithmetic processing unit increases the number of bits of the input data, performs an arithmetic process, and converts and outputs the input data.