JP3180724B2 - Cash system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a cache system, and more particularly, to a replacement circuit of a cache system which performs write-back by a multi-way set associative method.

[0002]

2. Description of the Related Art In a cache replacement circuit of a conventional cache system of this kind, when data requested from a processor is not in a buffer memory and data exchange with a main memory is performed, which data block in the buffer memory is replaced. As a typical method for determining whether to replace the data, (1) LRU (Least Recently Used)
Method (method of accessing the oldest data block), (2) FIFO (First In First Out)
t) method (method of replacing the oldest data block), (3) method based on access frequency, (4) fixed priority method based on cache state, and the like.

[0003]

The above-mentioned LRU method, FI
In the FO method, at the time of replacement, entry of a state that does not need to be written back, for example, invalid (invalid)
id), shared, exclusive match (clean)
exclusion), the exclusion mismatch (d
There is a possibility that the entry of “irractive exclusive” may be replaced, so that there is a problem that the number of write-backs increases and the bus traffic increases.

In the fixed priority method based on the cache state, the order of replacement is set to invalid> shared, exclusive match> clean exclusive> dirty exclusive, and the order of replacement is gradually increased. Exclusion mismatch (dirty exc
active), and eventually the number of entries
Most entries have exclusive mismatch (dirtyexcl)
use).

[0005] For this reason, when read instructions to different addresses in the multiway are successive, the entries are replaced with each other, so that there is a problem that a miss occurs every time.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above-described problem, and has as its object to count the number of entries of a cache with a non-exclusive mismatch (dirty exclusive) and to perform cache replacement according to the count value. An object of the present invention is to provide a cache system in which the method is sequentially changed to reduce write-back and improve bus traffic.

[0007]

According to a first aspect of the present invention, there is provided a cache replacement method comprising: a plurality of entries; and a replacement circuit for determining a replacement candidate for a cache block. , Wherein the replacement circuit counts the number of exclusion mismatches registered in the cache memory, a register that sets a range of a replacement method, and comparison means that compares the counter value with the value of the register. Wherein the replacement control is changed based on the comparison result by the comparing means.

[0008]

Embodiments of the present invention will be described below. In a preferred embodiment of the cache system of the present invention, the replacement circuit of the cache system does not have an exclusive mismatch (dirty exclusive).
e) Counter for counting the number of entries (7 in FIG. 1)
And a register (setting register (A, B) 6 in FIG. 1) for determining the range of the replacement method, and a comparator (8 in FIG. 1) for comparing the counter value with the register value. The replacement control method is changed.

Exclusion mismatch of the cache (dirty e)
xclive), and while the count value is smaller than the value of the setting register A, for example, a cache replacement of a fixed priority method is performed, and the number of entries of the exclusion mismatch (dirty exclusive) increases, and the number of entries of the setting register A is increased. After exceeding the value, exclusive mismatch (d
LRU until the number of entries in (irractive exclusive) becomes smaller than the set value B.
This is performed by a method such as a method, a FIFO method, or replacement by access frequency. Exclusion mismatch (dirty exclusive)
After the number of entries in (ve) falls below the set value B, the cache replacement of the fixed priority method is performed again until the number of entries of exclusion mismatch (dirty exclusive) exceeds the set value A.

[0010]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention; FIG. 1 is a diagram showing a configuration of a cache system according to one embodiment of the present invention.

Referring to FIG. 1, in one embodiment of the present invention, a tag memory 1 employs a write-back (copy-back) system of a 4-way set associative system. First, the access address ADD from the processor
R is held in the address register 2. The address register 2 includes a tag address section and a set address section. The tag address portion is compared with the tag data from the tag memory 1 by the comparator 3, and when they match, a cache hit occurs, and the desired cache data is transferred from the data memory to the processor.

On the other hand, if the tag address portion does not match the tag data from the tag memory, a cache miss occurs, the data at that address is read from the external memory, and the data is transferred to the processor. At this time, the address is stored in the entry indicated by the replacement pointer 4, and the data is stored in the data memory.

However, the state of the entry to be replaced is exclusive exclusive (dirty exclusive;
Dirty exclusive) involves a write-back operation of writing data back to the external memory.

As described above, in the conventional LRU method or FIFO method, since the control of the replacement pointer is not provided with a circuit for judging the state of the entry, the entry (invalid) that does not need to be written back.
id, shared, clean exclusive
e) Even if a large number of e) remain, dirty exclusi
Since the entry of "ve" may be replaced, there has been a problem that the number of write-backs increases and bus traffic deteriorates.

In the fixed priority cache replacement, the priority of replacement is (invalid).
> Shared, clean exclusive> d
(irractive exclusive), the replacement results in an increase in the number of dirtyexclusive entries, and eventually, most of the entries are
Because it becomes dirty exclusive, 4
When read instructions to different addresses in a way are successive, the cache memory is missed every time because the entries are replaced with each other.

In the present embodiment, the replacement controller 5 for controlling the replacement pointer counts the number of entries of the preset setting registers (A, B) 6 and the exclusive mismatch (dirty exclusive) in the tag memory 1. The comparison with the cache state counter 7 to be performed is performed by the comparator 8 to determine a cache replacement algorithm.

Different values are set in the setting registers (A, B) 6, respectively, and an exclusive mismatch (dirty ex.
The replacement algorithm is changed when the number of entries of the “positive” reaches the value of the setting register A or B.

In one embodiment of the present invention, the changing method may be, for example, a divergence mismatch (dirty exclusive).
v) the number of entries is the value of the setting register A (setting value A)
While the value is smaller than the fixed value, cache replacement using the fixed priority method is performed, and exclusion mismatch (dirty exclusive) is performed.
After the number of entries of v) increases and exceeds the set value A,
The cache replacement method is performed by the LRU method or the FIFO method until the number of entries of the exclusive mismatch (dirty exclusive) becomes smaller than the value of the setting register B (setting value B).

Exclusion mismatch (dirty exclusive)
After the number of entries in (ve) falls below the set value B,
Until the number of entries of "dirty exclusive" does not exceed the set value A, cache replacement using the fixed priority method is performed.

The cache state counter 7 counts up or down according to the state of data sent from the external memory and the state of data before replacement. In other words, the state of the data before replacement is exclusive mismatch (dirty exclusive).
ive), an exclusion mismatch (dirty ex)
If the value is changed to “exclusive”, the count is incremented, and an exclusive mismatch (dirty exclusive) is performed.
Is changed to a value other than "dirty exclusive", the countdown is performed. At other times, neither counting up nor counting down is performed.

As described above, it is possible to realize a cache system in which the number of write-backs is smaller than that of the conventional cache replacement method (LRU method, FIFO method, fixed priority method) and bus traffic is improved.

[0022]

As described above, according to the cache system of the present invention, there is an effect that a system with less write-back and improved bus traffic is realized. The reason is that, in the present invention, by counting the number of entries of the cache that do not match each other (dirty exclusive), the cache replacement method is sequentially changed according to the count value.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a cache system according to an embodiment of the present invention.

[Explanation of symbols]

 1 Tag Memory 2 Address Register 3 Comparator A 4 Replace Pointer 5 Replace Controller 6 Setting Registers A and B 7 Cache State Counter 8 Comparator B

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-1-287759 (JP, A) JP-A-10-27133 (JP, A) JP-A-4-205041 (JP, A) JP-A-1- 102662 (JP, A) JP-A-63-16351 (JP, A) JP-A-7-182241 (JP, A) JP-A-5-303528 (JP, A) JP-A-5-274779 (JP, A) JP-A-5-216765 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 12/12

Claims (4)

(57) [Claims] 1. A multi-way set associative cache system including a plurality of entries and including a replacement circuit for determining a replacement candidate for a cache block, wherein the replacement circuit includes an exclusive mismatch (dirty exclusive) registered in a cache memory. ), A register for setting the range of the replacement method, and comparison means for comparing the count value of the counter with the value of the register, wherein the replacement is performed based on the comparison result of the comparison means. A cache system for changing control. 2. The counter counts up or down according to the state of data sent from an external memory and the state of data before replacement, and the state of data before replacement is other than the exclusive mismatch (dirty exclusive). In the case where the data is changed from the one to the exclusive non-match (dirty exclusive), the count is performed, and the exclusive mismatch (di) is performed.
rty exclusive) to exclusion mismatch (dir)
2. The cache system according to claim 1, wherein a countdown is performed when the count value is changed to a value other than (type exclusive), and otherwise, the original count value is retained. 3. A multi-way set associative cache system including a plurality of entries and having a replacement circuit for determining a replacement candidate for a cache block, wherein the replacement circuit checks a state of the cache memory and determines an exclusive mismatch (dirty). exclusive
e) a counter for counting the number of entries, a storage unit for storing and holding a preset range of the replacement method, and a comparison unit for comparing the count value of the counter unit with the value of the storage unit. Based on the comparison result by the comparing means, the replacement (replacement) of the cache is performed by the fixed priority method, the LRU method, and the FRU method.
A cache system for changing between an IFO system and an access frequency system. 4. The storage unit holds a first set value and a second set value, and when the count value of the counter means is smaller than the first set value, the cache of the fixed priority type is replaced. After the count value of the counter means exceeds the first set value, replacement is performed by any of the LRU method, the FIFO method, and the access frequency method until the count value becomes smaller than the second set value, 4. The cache system according to claim 3, wherein when the count value of said counter means falls below said second set value, the fixed priority cache is replaced again until the count value exceeds said first set value.