JP3177277B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to an improvement of a semiconductor memory device having a structure in which a plurality of memory cells each including one transistor are connected in series.

[0002]

2. Description of the Related Art There is a demand for higher integration (storage capacity) of semiconductor integrated circuits, especially semiconductor memory devices, and the miniaturization of elements is progressing.

Under such a background, "1 capacitor + 1
A semiconductor memory device has been proposed in which a memory cell having a “transistor” structure is connected in series to form a cell block, and one end of the cell block is connected to a bit line. According to such a memory device, writing and reading are performed. However, if the cell area is the same, the storage capacity can be increased as compared with a conventional memory device (for example, “Kimura, K. et al. ISSCC91, article number TAM6.2” or “Nikkei Electronics 199
March 2013, pp. 87-88).

FIG. 3 shows a partial configuration of the proposed memory device. A plurality of cell blocks 12 are connected to each bit line 10, and the cell blocks 12
A predetermined number (for example, eight) of memory cells 14 connected in series
It is composed of Here, each cell block 12 is composed of one capacitor 16 having a predetermined capacity (charge storage capacity) as a storage element, and a transfer transistor 18 as a transfer gate connected to a word line.

That is, the memory cells 14 are connected in series, and writing and reading are performed in block units and random access cannot be performed in memory cell units. On the other hand, it is necessary to connect a bit line to each memory cell. And there is an advantage that the degree of integration can be increased.

In FIG. 3, the first memory cell is:
The voltage Vp is applied to the bit line 10 by the action of the transistor 20. Also,
The bit line 10 is connected to a sense amplifier 22 that performs data read detection.

FIG. 4 is a timing chart at the time of reading of the semiconductor memory device shown in FIG.

In FIG. 4, when reading data stored in a cell block, first, the transistor 20 is turned on by φ (bar) p, and precharging is performed. Precharge completion transistor 20 is turned OFF, then the word line W ₁ is maintained high. At this time, data ("1" or "0") stored in the capacitor of the first memory cell appears on the bit line, and is detected by the sense amplifier 22. FIG. 4 shows the bit line voltage _VBL detected by the sense amplifier.

Similarly, the transistor 20 is turned on by φ (bar) p, and the bit line is precharged. Next, when the word line W ₂ is in the "H" level, since this time the word line W ₁ is simultaneously being held high, the data from the second memory cell appears on the bit line 10.

The above operation is performed up to the last N-th memory cell, all the data in the block is detected by the sense amplifier, and its output is temporarily stored in a register and then output to the outside.

In the above-mentioned reference, the semiconductor memory device having the above structure is referred to as “BORAM (block
Oriented random access memory), but the above-described serial cell structure in which one end is connected to a bit line is not necessarily limited to a RAM, and can be applied to other types.

[0012]

However, in the above-mentioned semiconductor memory device, the capacity of the capacitor and the voltage level of the opposite electrode of the capacitor in all the memory cells are the same, and the memory cells which are far away from the bit line. There is a problem that the more the output signal is, the more difficult it is to detect. Originally, in order to stabilize the reading of each data, it is necessary to make the voltage of the output signal from each memory cell to the bit line detected by the sense amplifier constant. However, with respect to the first memory cell connected to the bit line, one or a plurality of other memory cells exist before the first memory cell, and the memory cell which is originally unnecessary in the output path of the memory cell. There is a problem that the voltage detected by the sense amplifier drops due to the presence of the capacitance. In FIG. 4, the output from the first memory cell is illustrated as 101, and the outputs from the second and subsequent memory cells are illustrated as 102 to 104.

An object of the present invention is to provide a semiconductor memory device having a serial cell structure in which one end is connected to a bit line, regardless of the distance from the bit line. The purpose is to make the output from each memory cell appearing on the line substantially constant.

[0014]

In order to achieve the above object, the present invention provides a memory cell comprising a capacitor as a storage element and a transfer transistor connected to a word line.
In a semiconductor memory device in which a plurality of cell blocks connected in series are connected to a bit line,
Is connected to the bit line, and the connection point
The distance to each memory cell that makes up the cell block
The different, viewing including the capacitor voltage control means for controlling the potential of the counter electrode of the capacitors in the cell block,
The capacitor potential control means, when writing data,
The connection point of each memory cell constituting the cell block
As the distance from the memory increases, each memory
The present invention is characterized in that the fluctuating potential difference of a counter electrode of a cell capacitor is increased . Further, the present invention provides
A transfer transistor connected to a capacitor and a word line;
Cell that consists of multiple memory cells connected in series.
Lock is applied to the semiconductor memory device connected to the bit line.
And one end of the cell block is connected to the bit line.
From the connection point,
The distances to the recells are different from each other.
Each memory cell is divided into multiple groups,
The potential of the opposite electrode of the capacitor in the cell block
And a capacitor potential control means for controlling the capacitance.
The data potential control means, when writing data,
The distance between each of the groups that make up the
As it becomes smaller, each memory cell of each group
Increasing the fluctuating potential difference of the opposite electrode of the capacitor
Features.

[0015]

According to the above structure, the potential of the counter electrode of the capacitor (the electrode facing the storage node connected to the transfer transistor) in each cell block can be controlled by the capacitor potential control means, so that the following control can be performed. .

The first control method is a method of increasing the fluctuating potential difference of the counter electrode as the distance from the bit line increases during data writing. According to this method, the amount of accumulated charge increases as the distance from the bit line increases. The output level from each capacitor detected by the sense amplifier at the time of reading can be made uniform. That is, it is possible to prevent the output level from dropping due to the influence of the capacitor existing before itself. A second control method is a method in which a cell block is divided into a plurality of groups, and the farther from the bit lines, the larger the fluctuating potential difference of the common electrode of the capacitor for each group. According to this, since the potential of the counter electrode can be controlled collectively for each group, there is an advantage that design and manufacturing can be simplified while obtaining the same effects as described above.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a preferred embodiment of a semiconductor memory device according to the present invention. FIG. 1 is a circuit diagram showing a main part thereof. The basic configuration is the same as that of the conventional example shown in FIG. 3 except for the potential control of the counter electrode described later.

In FIG. 1, in this embodiment, a plurality of memory cells 14 constituting each cell block 12 are divided into M groups. In the following description, each cell block is composed of eight memory cells,
M = 2, that is, a group of four memory cells is 2
It is assumed that one is formed.

Here, the first group includes the bit line 1
This is the group closest to 0, and the level drop of the output from each capacitor detected by the sense amplifier 22 at the time of reading is small as a whole. On the other hand, the second group (illustrated as the M-th group in the figure) includes the bit line 1
The group is far from 0, and the level drop of the output from each capacitor detected by the sense amplifier 22 at the time of reading is large as a whole. That is, as described above, at the time of reading, it is affected by a large number of capacitors (mainly, capacitors of the first group) existing before itself.

Therefore, the semiconductor memory device of this embodiment is provided with a potential control unit 40 for changing the potential of the common electrode of the capacitor according to the distance from the bit line 10 when writing data.

The opposite electrode of the capacitor 16 of the first group, that is, the electrode 16a opposite to the storage node 16b connected to the transfer transistor 18 has a common potential, and more specifically, the terminal P of the potential control unit 40.
It is connected to C1. Here, the potential of PC1 is fixed, and the potential is fixed to, for example, Vcc / 2 as in the related art.

On the other hand, the opposing electrodes 16a of the capacitors of the second group have a common potential. Specifically, they are respectively connected to the terminal PC2 of the potential control unit 40, and the potential is controlled during data writing. I have.
At the time of reading, PC2 is set to the same potential as PC1. The potential control unit 40 will be described in detail below.

FIG. 2 shows a timing chart at the time of data writing. At the time of writing, first, all word line arrays are in a state where 1 to 8 are selected, that is, "H" level. In this state, “H” of φ (bar) p
The transistor 20 is turned on by the level, and the bit line is precharged to Vp. After precharge, φ
(Bar) The transistor 20 whose p becomes the “L” level is turned off. In the figure, # 8 to # 1 in the first row indicate periods in which data writing is valid, as understood from the lowermost Din.

Next, when "1" is written as data, the potential of PC2 is set to Vcc / 2-β. on the other hand,
When writing "0" as data, the potential of PC2 is set to Vcc / 2 + β. Β that determines the potential of PC1, whose potential is increased or decreased from Vcc / 2, is an arbitrary positive value. However, as will be described later, mainly the distance from the bit line 10, in other words, up to the bit line 10, It is desirable to determine according to the number of intervening memory cells.

After that, the data according to the external input is amplified by a write amplifier (not shown) and stored as a stored charge in the capacitor of the eighth memory cell via the bit line. Thereafter, the word line W8 goes to "L" level, and PC2 is returned to the original potential, that is, Vcc / 2,
The series of operations described above completes the writing of the eighth memory cell. As shown in FIG.
This is performed for the capacitors of the memory cells from the fifth to the fifth memory cells.

Next, data is written to the capacitors of the fourth to first memory cells. In this case, since PC1 is set to a fixed potential, the same writing (opposite operation) as in the prior art is performed. (Writing at a constant potential of the electrode).

As described above, at the time of data writing, the potential of the counter electrode of each capacitor of the second group apart from the bit line 10 is varied, thereby increasing the fluctuating potential difference of the counter electrode and increasing the accumulated charge. The amount can be increased.

When the data written as described above is read, the data is read by the same operation as the conventional one shown in FIG. 4. In this case, the potential of both PC1 and PC2 is fixed at Vcc / 2.

Therefore, the level of the output from each capacitor detected by the sense amplifier 22 can be made uniform for the first group and the second group. Of course, in each group, the output level of the capacitor far from the bit line 10 is lower than that of the capacitor closer to the bit line 10, but the output level can be greatly reduced as compared with the related art.

If there is a demand to strictly uniform the output level regardless of the distance from the bit line, the counter electrode may be controlled for each capacitor without being divided into groups.

The potential control section 40 controls the potential based on the signal of each word line. In this case, in the above-described example, the potential of the fifth to eighth capacitors in the second group is set only at the time of writing. You only have to control,
For example, among the address signals a _{0 to} a _7, for example, the address signal a ₂ corresponding to the second group selection is used as a selection signal. The potential level to be varied is Vcc / 2-β, Din when the data write condition is satisfied, that is, when the write signal WE (bar) is at the “L” level and Din = 1 due to the polarity of the input data. =
If it is 1, the potential is changed to -Vcc / 2 + β.

In the above description, when writing data "1" and writing data "0",
Although the potential control in the opposite direction is performed, it is also possible to control only one of them. Also in this case, at the time of writing one of the data, it is possible to increase the fluctuating potential difference of the common electrode of each capacitor in the second group far from the bit line, thereby increasing the output level to the bit line at the time of reading.

[0034]

As described above, according to the present invention,
Since the potential of the counter electrode of each capacitor can be controlled by the capacitor potential control means, by controlling the potential of the counter electrode in accordance with the distance from the bit line for each capacitor or each group, the distance from the bit line can be increased. Attenuation of information read from the memory cell, that is, a decrease in potential appearing on the bit line can be prevented, and as a result, the level of output from each capacitor can be made uniform. Therefore, the operation of the sense amplifier connected to the bit line can be stabilized, and the number of memory cells connected in series can be increased.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main configuration of a semiconductor memory device according to the present invention.

FIG. 2 is a timing chart showing an operation at the time of writing.

FIG. 3 is a block diagram showing a main configuration of a conventional semiconductor memory device.

FIG. 4 is a timing chart showing an operation at the time of reading.

FIG. 5 is an explanatory diagram showing V _BL at the time of reading according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Bit line 12 Cell block 14 Memory cell 16 Capacitor 16a Counter electrode 18 Transfer transistor 40 Potential control part

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G11C 11/407

Claims (2)

(57) [Claims] The method according to claim 1 memory cells consisting of the connected transfer transistor to the capacitor and a word line as a memory element, the cell blocks formed by connecting a plurality series, in a semiconductor memory device which is connected to the bit line, said cell One end of the block is connected to the bit line, and
From the connection point of each memory cell constituting the cell block
Unlike distance to each other, it viewed including the capacitor voltage control means for controlling the potential of the counter electrode of the capacitors in the cell block, the capacitor voltage control means, when data is written,
The connection point of each memory cell constituting the cell block
As the distance from the memory increases, each memory
A semiconductor memory device characterized by increasing a fluctuating potential difference of a counter electrode of a cell capacitor. 2. A capacitor as a storage element and a word line
Cell consisting of transfer transistor connected to
Are connected in series to form a cell block
In one embodiment, one end of the cell block is connected to the bit line, and
From the connection point of each memory cell constituting the cell block
Distances from each other, and each memory cell in the cell block includes a plurality of groups.
It is divided into over-flop, the potential of the counter electrode of the capacitor in the cell block
The capacitor potential control means for controlling the
Whether the connection point of each group constituting the cell block
As their distance increases, each group
Increase the fluctuation potential difference of the counter electrode of the memory cell capacitor
The semiconductor memory device, characterized in that Kusuru.