JP3175768B2 - Composite instruction scheduling processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a composite instruction for determining a combination and an arrangement position of operations in a composite instruction in which a plurality of operations are stored in an instruction serving as a unit of simultaneous transmission. The present invention relates to a scheduling processing device.

[Conventional technology]

FIG. 10 shows an example of a compound instruction for explaining the problem of the present invention.

A computer that has a plurality of operation units and simultaneously issues a composite instruction in which several instructions are combined and executes the instructions in parallel to increase the speed of instruction execution has been considered. Figure 10 shows an example of the compound instruction.
Each of the 6-bit complex instructions can store three 32-bit instructions. Hereinafter, each instruction stored in the compound instruction is referred to as an “operation”.

How this operation is arranged in a sequence of compound instructions will affect its execution performance. However, an efficient method has not yet been established for the instruction scheduling processing for allocating operations. Was.

[Problems to be solved by the invention]

At the time of instruction scheduling of the hybrid instruction architecture, the following points must be considered.

(1) Each operation has a different execution time. That is, the number of machine clocks required for execution is different.

(2) There are restrictions on the combination of operations and where to place operations in a compound instruction.

In consideration of these points, it is desired to create a composite instruction that can be executed in the shortest time and to realize a desired process with the minimum number of composite instructions.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above problems and to efficiently create a composite instruction having good execution performance.

[Means for solving the problem]

 FIG. 1 is a diagram illustrating the principle of the present invention.

In FIG. 1, reference numeral 10 denotes a data processing device having a CPU, a memory, and the like; 11, an operation sequence storage unit for storing a sequence of individual operations; 12, a data dependence analysis processing unit for creating a data dependence graph; A priority order determination processing unit that analyzes the dependency graph and rearranges the graph according to the priority order; 14 determines a placement position of the operation, and generates a composite instruction generation processing unit;
Denotes a data dependency graph indicating the definition / reference relationship of data handled in each operation, and 16 denotes a composite instruction storage unit for storing the prepared composite instruction.

The operation sequence storage unit 11 stores, for example, a linear operation sequence composed of an instruction sequence equivalent to the assembler language output by an existing compiler.

The present invention provides a technique for creating an optimal compound instruction sequence from the operation sequence stored in the operation sequence storage unit 11.

The data dependence analysis processing unit 12 performs each operation i1, i2,
Analyze the data dependencies between..., That is, define / reference relationships, and create a data dependency graph 15.

The priority order determination processing unit 13 determines the priority order of operations based on the data dependency graph 15 based on several criteria such as an instruction end time and an instruction dispatch time, and rearranges the operations in the data dependency graph 15. I do.

The composite instruction creation processing unit 14 places each operation in a composite instruction according to the priority of the operation determined by the priority determination processing unit 13 and stores the operation in the composite instruction storage unit 16.

[Action]

Operation i2 refers to the data defined by operation i1, and operation i5
And the data defined in operation i4, and ...
… And so on between data definitions /
If there is a reference dependency, the data dependency analysis processing unit 12
Analyzes this to create a data dependency graph 15 as shown in FIG. The data dependency graph 15 is realized by control tables indicating operations and pointers between the control tables.

By referring to the data dependency graph 15, it is possible to determine which operation must be executed first. In addition, by taking into account the time during which each operation can be executed, it is possible to obtain a standard that can be executed in the shortest time.

In particular, as a criterion, the inversion of the definition / reference relationship can be prevented by taking into account the instruction transmission possible time, and the overall end time can be shortened by considering the instruction termination possible time.

The composite instruction creation processing unit 14 arranges each operation in the composite instruction while determining whether or not the combination of the operations is correct based on the result of the priority order determination processing unit 13.

In the example shown in FIG. 1, operations i1, i3, and i4 are arranged in the first composite instruction I1, operations i2, i5, and i7 are arranged in the second composite instruction I2, and so on. Type instructions have been created.

〔Example〕

FIG. 2 is an example of a compound instruction computer for executing a compound instruction created according to the present invention, and FIG. 3 is an application example of the present invention.
FIG. 5 shows an example of a sequence of operations for explaining the embodiment of the present invention, FIG. 5 shows an example of a data dependency graph according to the embodiment of the present invention, and FIG. 6 shows a data dependency graph used in the embodiment of the present invention. FIG. 7 shows a data structure of a dictionary used in the embodiment of the present invention, FIG. 8 shows an example of a priority standard according to the embodiment of the present invention, and FIG. 9 shows a process of an embodiment of the present invention. Shows the flow.

In the present invention, for example, a sequence of compound instructions to be executed by the compound instruction computer 20 shown in FIG. 2 is created. This composite instruction computer 20 has two integer operation units 22 and 23,
Floating point addition unit 24 and floating point multiplication unit
It has 25 operation units. Each of these arithmetic units can operate in parallel.

The composite instruction is fetched from the main memory (not shown) and is sequentially set in the composite instruction register 21. In this example, a maximum of three operations are included in one compound instruction. The three operations are transmitted simultaneously, and the corresponding integer operation units 22, 23, floating-point addition unit 24, floating-point multiplication The unit 25 is operated.

Since each unit can execute only one operation, the operations that can be combined in the compound instruction are as follows. Here, I: Integer operation (including LOAD / STORE) F: Floating operation B: Branch operation

 B → 1 and I → 2.

 B → 1 piece, I → 1 piece, F → 1 piece.

 B → 1 and F → 2.

 I → 2 and F → 1.

 I → 1 and F → 2.

FIG. 3 shows an example of the configuration of a compiler 30 that outputs a compound instruction executed by the compound instruction computer 20 as described above.

Processing phases (a) to (f) in compiler 30
Is similar to a conventional ordinary compiler. That is,
The following processing is performed.

(A) Input a source program and perform syntax analysis.

(B) Perform semantic analysis based on the syntax analysis results.

(C) Allocate data.

(D) Optimization such as a change in processing logic or a change in data type is performed.

(E) Allocate registers.

(F) Generate code at the assembler language level.

The present invention relates to the next processing phase (g), and performs instruction scheduling by regarding the output of the code generation phase (f) as an operation sequence listed in the order of execution. As a result, a compound instruction is created.

 Hereinafter, embodiments of the present invention will be described according to specific examples.

For example, it is assumed that a composite instruction to be executed by the composite computer 20 shown in FIG. 2 is created from the sequence of operations shown in FIG.

The operations shown in FIG. 4 have the following functions.

Note that fpr1 to fpr5 indicate floating-point registers, and S, b
(I), a (i) and the like indicate variables.

(1) fload x, r1 Loads the value of floating-point variable x into register r1.

(2) fstore r1, x Store the floating point value in register r1 in variable x.

(3) fmult r1, r2, r3 Multiplies the register r1 by the floating point in the register r2 and stores the result in the register r3.

(4) fadd r1, r2, r3 Add the floating point in register r1 to the register r2 and store the result in register r3.

In the instruction scheduling according to the present invention, the following processing is performed by inputting a sequence of operations as shown in FIG.

(I) Creation of data dependency graph Each input operation is set as a node, and from there,
Chain and reverse chain the nodes defining the operands of the operation and nodes whose execution order cannot be changed (the instruction cannot be overtaken and executed).

FIG. 5 is an example of a data dependency graph created from the sequence of operations shown in FIG. The arrow shown in FIG. 5 is a definition chain, and the reverse of this arrow is a reference chain. For example, the operation refers to fpr1 and fpr2, and since the operation defining fpr1 and fpr2 is, the definition chain from to and from is performed.

The information of this node is managed by a data structure as shown in FIG. 6, for example. Here, each element has the following contents.

Instruction sequence: Refers to an input operation.

Node number: The number of the operation in the input order.

Definition chain: A chain to the operation that this operation is using (ie, a chain to an operation that must have been executed before this operation).

Reference chain: a chain to the operation that is using the result of this operation.

FINISH: Reference value for sorting nodes.

DISPATCH: Second reference value for reordering nodes.

Operand definition / reference is performed by registering operands appearing in each operation in a “dictionary” having a data structure as shown in FIG. 7, and referencing / updating / registering this dictionary every time an operand appears. By going, you can find out.

In this embodiment, in order to speed up the search, this dictionary is managed in a binary tree structure. In the alphabetical order of the operands, the front one is the left child and the rear one is the right child. Manage with pointers. If no operand is a child, the DICTIONARY element is an empty pointer.

The type of the operand indicates the type of the floating-point register number, general-purpose register number, variable name or constant name.

(Ii) Analysis of Data Dependence Graph When the data dependence graph is completed, a criterion of priority for selecting an instruction is calculated based on the graph.

As described above, the data dependency graph indicates each node (operation definition / reference relationship).

The fact that there is a relationship v → u between two nodes u and v (the definition chain of node v points to node u) means that execution of v is u
Means that you have to wait until the execution is complete. This means that if the execution of u takes tτ (τ is a machine cycle), the execution of v will be executed tτ after the start of u.

Thus, "priority" exists between the nodes connected by the definition chain. The schedule must take this priority into account. In addition, when there are some executable operations, it is possible to schedule efficiently by giving priority to the operations that take a long time to finish the execution. Therefore, the following two criteria, FINISH, which indicates the time at which the command can be completed, and DISPATCH, which indicates the time at which the command can be transmitted, are used.

The criterion that indicates the time at which the FINISH instruction can be completed is called FINISH and is calculated using the following formula. The higher the FINISH value, the sooner it needs to be transmitted.

{V | v → u} →: definition chain Here, EXEC (x) is the number of machine cycles required to execute the operation of node x.

DISPATCH DISPATCH (v) indicates the shortest machine cycle when operation v is transmitted to the operation unit.

If the operation unit in which each operation is executed is in an empty state and there is no cache miss or TLB hit miss in a normal state, the execution time of the operation is determined by hardware.

Therefore, DISPATCH (v) can be calculated and is calculated by the following equation. The smaller the DISPATCH value, the sooner you must send.

Fig. 8 (a) shows the FINISH value (FI) of each node calculated by the above formula for the data dependence graph shown in Fig. 5.
FIG. 8 (b) shows the DISPATCH value (DI). In this example, the execution time of the operation is assumed as follows.

fload / fstore execution time → 1τ fmult execution time → 4τ fadd execution time → 3τ (iii) Sorting nodes Sort nodes based on FINISH and DISPATCH obtained by graph analysis. In this embodiment, the rearrangement criteria are as follows, starting from the one with the highest priority.

Smallest order of FINISH values If FINISH values are equal, small order of DISPATCH values. If FINISH and DISPATCH are equal, input order. (Iv) Creation of compound instruction. A composite instruction is created in the manner of (a) to (c).

(A) First, a composite type instruction to store the operation v is searched. The starting point for searching is the base point of the compound instruction, the position of the instruction where the node u defining v is stored, and using the same arithmetic unit as v, and the operation u issued before v Is the instruction farthest from the starting point of the compound instruction, that is, the instruction that is sent the latest among the positions of the instructions in which is stored.

(B) Trace the composite instruction I from the starting point and check whether the node v can be stored in combination in the instruction I. If it can be stored, v is incorporated in the compound instruction I. If it cannot be stored, the same operation is performed for the instruction following the compound instruction I.

The conditions under which the node v can be stored in the instruction I are as follows: i) there is room to put an operation in the instruction I (not all three operations are buried); ii) the combination of the three operations is hardware. The condition is that it is legally allowed. The condition of ii) can be easily checked by preparing a table for a combination of operations.

(C) If the instruction I is filled by three operations during the processing (b), a new composite instruction is created and v is incorporated therein.

When the above-described processes (a) to (c) are completed, an example of the composite instruction to be obtained is sequentially obtained from the base point of the composite instruction.

FIG. 9 shows the outline of the processing according to the embodiment of the present invention described above in the form of a processing flow, and is as follows.

(I) Create a data dependency graph with each operation as a node.

(Ii) Analyze the data dependency graph, and calculate the FINISH value and DISPATCH value that are the priority criteria for each node.

(Iii) Reorder the nodes based on the FINISH value and DISPATCH value.

(Iv) According to the order of the rearranged nodes, a composite type instruction to store each operation is searched, conditions for storing are checked, and then incorporated into the composite type instruction.

In the above processing, (i) to (iii) are processing in consideration of shortening the instruction execution time as much as possible.
(Iv) is a process in consideration of shortening the instruction length.

As an embodiment, the instruction scheduling for creating a composite instruction to be executed by the composite computer 20 as shown in FIG. 2 has been described. However, the present invention can be similarly applied even if the configuration of the arithmetic unit changes. is there. In addition, the number of simultaneous transmissions is not necessarily three, and the same operation can be performed even if the number of simultaneous transmissions is different.

〔The invention's effect〕

As described above, according to the present invention, it is possible to create an optimal composite instruction sequence having a short overall execution time, and to efficiently pack operations into composite instructions to reduce the number of composite instructions. Can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining the principle of the present invention, FIG. 2 is an example of a compound instruction computer for executing compound instructions created according to the present invention, FIG. 3 is an application example of the present invention, and FIG. FIG. 5 is an example of a data dependency graph according to an embodiment of the present invention, FIG. 6 is a data structure of nodes of the data dependency graph used in the embodiment of the present invention, FIG. 7 is a data structure of a dictionary used in the embodiment of the present invention, FIG. 8 is an example of a priority standard according to the embodiment of the present invention, FIG. 9 is a processing flow of an embodiment of the present invention, FIG. Shows an example of a compound instruction for explaining the problem of the present invention. In the figure, reference numeral 10 denotes a data processing device, 11 denotes an operation sequence storage unit, 12 denotes a data dependence analysis processing unit, 13 denotes a priority order determination processing unit, 14 denotes a composite instruction creation processing unit, and 15 denotes a data dependence graph.

──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Hiroji Hotta 1015 Uedanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Co., Ltd. (56) References Nikkei Electronics, No. 487, 1989-11-27, p. 199-200 IEICE Technical Report, Vol. 89, No. 167 (CPSY89-3), p. 43-48 IEICE Transactions, J67-D, 7, 1984, p. 792-799 (58) Field surveyed (Int. Cl. ⁷ , DB name) G06F 9/44

Claims (1)

(57) [Claims] In a compound instruction scheduling processing apparatus for determining a combination and an arrangement position of operations in a compound instruction in which a plurality of operations are stored in an instruction serving as a unit of simultaneous transmission, operations which are linearly arranged A data dependency analysis unit that analyzes the data dependencies of each operation; a priority order determination unit that determines the priority of operations based on the analyzed data dependencies; And a composite instruction creation processing unit arranged in the first order, wherein the priority order determination processing unit sets a first reference value indicating a possible instruction end time of each operation and a second reference value indicating a possible instruction transmission time. The priority order of operations to be used and executed is determined at least in ascending order of the first reference value, When the reference values are equal, the composite instruction scheduling processing device is determined so that the second reference value is in ascending order.