JP3173555B2 - Transmission line error correction code circuit and transmission line termination device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a plurality of linear repeaters (L).
The present invention relates to a transmission path error correction coding circuit used for improving the error rate of a received signal and a transmission method using the transmission path error correction coding circuit in a long-distance and large-capacity optical transmission system using (REP).

[0002]

2. Prior Art and Problems to be Solved by the Invention Er
A linear repeater using a doped fiber optical amplifier is expected to be used in various optical transmission systems in the future because of its economy, bit rate independence, and high reliability.
However, since an Er-doped fiber optical amplifier is a kind of analog amplifier that does not perform signal regeneration and resynchronization, a repeater system using a large number of linear repeaters using this Er-doped fiber optical amplifier has noise. Accumulation is inevitable. For this reason, in an optical transmission system using a large number of the linear repeaters and having a long regenerative repeat interval, the error rate of the received signal (BE
In the R) characteristic, a floor characteristic that the error rate is hardly improved (a phenomenon that the error rate does not decrease below a certain value at high speed even when the optical input increases) appears. For example, 10Gbi
When a signal of t / s is relayed using 19 linear repeaters (regeneration relay interval: 1260 km), the light receiving power is set to 4.1d in order to improve the error rate from 10 ^-9 to 10 ^-11 .
B has also been reported to have to be increased (K. Aoyama, Y. Yamabayashi, and K. Hagimoto: "De
sign and Operationof Transmission Lines containing
Er-Doped Fiber Amplifiers "IEEE GLOBECOM., 1992,
pp.1875).

There are roughly two methods for overcoming the drawbacks of such a linear repeater. One is to increase the optical power as in the prior art. Increasing the optical power increases the error rate in principle, but causes a new problem that the waveform of the optical signal is degraded by the nonlinear optical effect. Another solution is to improve the error rate without depending on the optical power. One of the methods is
There is a transmission line error correction code technology. At present, the transmission path error correction code technology is applied to satellite communication and mobile communication which are easily affected by interference waves and have a limited available transmission power. However, in these wireless communications, the transmission speed is at most 100 Mbit / s, and several hundred Mb / s.
As for the error correction code suitable for optical communication at a transmission speed of from it / s to several tens Gbit / s, only a small number of studied examples have been studied. Hereinafter, this will be described.

[0004] In 1991, Moro et al.
200 km-565 using H (167,151) code
Mbit / s (700 Mbit / s after encoding) transmission experiment without a regenerative repeater was performed (P. Moro and D. Candian).
i, "565Mbit / s Optical Transmission System for Repe
aterless Sections up to 200km ", IEEE ICC, 1991, pp.
1217). This BCH (167, 151) code is 167
Error correction of up to 2 bits in a bit was possible, and the coding gain of Moro et al. was 2.5 dB.

Also, in 1992, Gabla
Use the RS (255, 239) code for 401 km
-622 Mbit / s (710 Mbit / s after encoding)
And 357 km-2.4 Gbit / s (2.8 G after encoding)
bit / s) regenerative relay span experiment (PM
Gabla, JL Pamart, R. Uhel, E. Leclerc, JOFro
rud, FX Ollivier, and S. Borderieux, "410km, 62
2Mbit / s and 357kn, 2.488Gbit / s IM / DD Repeaterless
Transmission Experiments Using Er-DopedFiber Ampli
fies and Error Correcting Code ", IEEE Photonics Te
chnologyLetters, Vol.4, No.10, 1992, pp.1148). Have obtained an encoding gain of 5 dB using an optical transmission line using a linear repeater.

However, although the codes used in these studies have the possibility of multiple error correction,
It can be said that it is not suitable for an ultra-high-speed circuit of / s or more. In addition, these codes increase the bit rate, so the International Telegraph and Telephone Consultative Committee (CCITT) recommendation G7
07, 708, 709 (STM:
Not conforming to the Synchronous Transport Module (Synchronous Transport Module) format, these unique optical transmission formats cannot be applied to an optical transmission system without an encoding circuit.

To overcome these difficulties, 1990
There is a proposal of Grover et al. This is because shortened hamming at the VC-3 level (6208, 61
95) encoding (WD Grover and TE Moore,
"Design and Characterization of an Error-Correcti
ng Code for the SONET STS-1 Tributary "IEEE Transa
ctions on Communications, Vol.38, No.4, 1990, pp.4
67). Hamming codes have good coding efficiency and can be realized with a simple shift register configuration, and are suitable for coding high-speed signals. Glover et al. State that the error rate can be reduced by adding two bytes to the path overhead (POH) of the SONET format.

However, the path overhead P
At present, only three bytes of the OH are free bytes, and if two bytes are used for error correction, the remainder is only one byte. Therefore, it is not considered suitable for more advanced path management. Furthermore, according to the proposal of Glover et al., Application to a path other than the path VC-3 (STS-1) is impossible. At present, the VC-3 path is mainstream, but in the future, the asynchronous transfer mode (ATM: Asynchronous
s Transfer Mode) Cell mapping (CCITT draft Rec)
ommendation I.311- "B-ISDN General Network Aspect
s ", SG XVIII Temporary Document 56 Geneva, 1992)
For example, the high-speed path VC-4-Xc (X = 1, 4, 1
6) is introduced. However, as described above, the proposal of Glover et al. Cannot be applied to these high-speed paths corresponding to B-ISDN at all.

Suzuki has proposed an error correction code (humming code) processing method for a VC-4-16c connection path (Tetsuhiko Suzuki, "Error Correction Code Insertion Processing Method and Optical Transmission Device for SDH Signal"). Kaihei 6-299
56 gazette). In that proposal, the reporting unit is a concatenated nine-row payload, with one row of payloads.
While transmitting the data without processing it, the payload data is calculated by the generator polynomial calculation circuit,
As shown in FIG. 20, the 16-bit surplus polynomial error correction code obtained by the completion of the operation of the payload data for one column is converted to the path overhead POH of the next column of the payload data for one column, as shown in FIG. It is inserted into the stuff area at the back, where waste (stuff) bits are stored.
Therefore, this code processing method cannot be applied to a path having a speed of VC-4 or less where no stuff area exists.
Also, this code processing circuit can control the V
It cannot be applied to paths other than C-4-16c.

Furthermore, in both the Glover and Suzuki systems, since the error is corrected after the end of the path, the section overhead (SO
The transmission path is switched by the multiplex section protection circuit by the B2 byte of H). That is, this is a deployment method that is inconsistent with the purpose of correcting errors in the transmission path and improving the error rate.

Incidentally, in the future, the undefined portion of SOH will be
Since it is expected to be used for individual purposes of the user or to be newly recommended, it is expected that serial-type Hamming codes having excellent code efficiency will be applied over a wide range.
However, in that case, the encoding / decoding circuit is 156
It is necessary to operate at a clock frequency of MHz, and at present, the circuit must be constituted by a BiC-MOS or an LSI capable of operating at a higher speed than the BiC-MOS.

This leads to problems such as an increase in power consumption, an increase in heat, and an increase in the size of the circuit, and makes it difficult to apply an economical coding circuit. For this reason, a circuit configuration method for configuring a circuit with the simplest and low power consumption C-MOS logic programmable circuit (FPGA: Field Programmable Gate Array) is desired. From such a background, there is a need for a circuit configuration for processing a plurality of serial Hamming codes in parallel and a configuration method thereof.

A parallel processing circuit for cyclic codes which is an example of such a circuit configuration is described in "Error Correction Device for Parallel Processing" by Nakamura (NEC Corporation) (JP-A-52-86011).
Gazette). In the above publication, a (255, 247) Hamming code is cited as an example of a code applied to the parallel processing circuit, and a method of performing four parallel processings is described. However, the method disclosed in Japanese Patent Application Laid-Open No. 52-86011 is not suitable when the code word is large. Hereinafter, the reason will be described.

In order to constitute the (255, 247) Hamming code encoding / decoding circuit, it is necessary to provide a connection for outputting a remainder obtained by dividing a predetermined equation by a generation rule polynomial. Therefore, for example, in order to use (18880, 18865) Hamming codes and implement the eight parallel processing by the above method, a complicated connection is required and an enormous amount of calculation is required. Therefore, in parallel processing of a cyclic code having a large codeword, a simpler circuit configuration and a derivation method thereof are required. That is, there is a demand for simplification of a processing circuit such as an error correction encoding / decoding circuit.

The present invention has been made in view of such a background, and a transmission line capable of correcting a transmission line error without increasing a bit rate, which is the strictest condition for an ultrahigh-speed optical transmission line. An object of the present invention is to provide a transmission method using an error correction code circuit and a transmission line error correction code circuit.

[0016]

According to the first aspect of the present invention,
A transmission line error correction code circuit applied to an SDH network, comprising: a VC path or each derived from a synchronous transfer module (STM) frame according to the recommendations of the International Telegraph and Telephone Consultative Committee, which matches the input data string. For AU-4 signal, transmission error correction coding /
A code operation circuit for decoding, and a check bit insertion circuit for writing a check bit into an undefined area of a multiplex section overhead field in a section overhead field of the STM frame, wherein the check bit The transmission error correction is performed based on

According to a second aspect of the present invention, in the first aspect, the code operation circuit performs k-bit interleaving (k is a natural number) of the input data character string and applies the k-bit interleaved signal to the k-bit interleaved signal. Transmission error correction encoding / decoding.

According to a third aspect of the present invention, in the first aspect, the sign operation circuit performs division for dividing the AU-4 signal by a predetermined generator polynomial, and the check bit insertion circuit performs the division. Is written as the check bit.

According to a fourth aspect of the present invention, there is provided a transmission line terminating device using the transmission line error correcting code circuit according to the second aspect, wherein the code operation circuit divides the AU-4 signal by a predetermined generator polynomial. In addition to performing the division, the check bit insertion circuit writes the remainder of the division as the check bit.

According to a fifth aspect of the present invention, there is provided the transmission line error correction code circuit according to the second aspect, disposed between the transmission line and a multiplex section protection circuit for switching the transmission line when a failure occurs in the multiplex section. It is characterized in that whether or not a switch used in the multi-section protection circuit is on is determined based on a bit error rate after error correction.

According to a sixth aspect of the present invention, in the fourth aspect, the transmission line error correction code circuit is provided between a transmission line and a multiplex section protection circuit for switching a transmission line when a failure occurs in the multiplex section. And whether the switch used in the multi-section protection circuit is on or not is determined based on the bit error rate after error correction.

According to a seventh aspect of the present invention, the transmission line error correction code circuit of the second aspect is arranged between a multi-section protection circuit and a multi-section termination circuit, and the multi-section protection circuit has a fault in the multi-section. When this occurs, the transmission path is switched, the multi-section termination circuit terminates the processing in relation to the multi-section overhead field, and the switch used in the multi-section protection circuit corresponds to the bit error rate after error correction. And turned on based on the check bit.

According to an eighth aspect of the present invention, in the fourth aspect, the transmission line error correction code circuit is disposed between a multi-section protection circuit and a multi-section termination circuit, and the multi-section protection circuit is a multi-section protection circuit. When a failure occurs in the section, the transmission path is switched, the multi-section termination circuit terminates the processing in relation to the multi-section overhead field, and the switch used in the multi-section protection circuit switches the bit after error correction. It is characterized by being turned on based on the check bit, corresponding to an error rate.

According to a ninth aspect of the present invention, in the communication system of the eighth aspect, the transmission line error correction coding circuit converts m (m is an integer satisfying m> 1) data from the input data sequence. A serial-to-parallel conversion circuit that generates and outputs the data in parallel, and m clocks of division logic by a generator polynomial for m data output from the serial-to-parallel conversion circuit are realized in one clock, and check bits are generated. A logical operation circuit, and a check bit for writing and adding the check bit to an undefined area of a multiple section overhead field in a section overhead field of an STM frame, or extracting the check bit from the undefined area A read / write circuit.

According to a tenth aspect of the present invention, in the ninth aspect, the logical operation circuit comprises a plurality of exclusive OR circuits and a plurality of shift registers, and each of the shift registers is Input data is held and output for only one clock, and has one input terminal connected to one of the first, second and third ports. One of the m output ports of the conversion circuit, the second port is an output port of any one of the shift registers other than the own shift register, and the third port is the first port And an output port of the means for calculating the exclusive OR of the output from the second port and the output from the second port. The output port of each shift register is connected to the check bit read / write circuit. It is characterized in that.

[0026]

According to the first aspect of the present invention, the code arithmetic circuit is constituted by a VC path or is derived from a synchronous transfer module (STM) frame according to the recommendation of the International Telegraph and Telephone Consultative Committee, which matches the input data character string. Each AU
-4 signal is subjected to transmission error correction encoding / decoding, and a check bit insertion circuit checks an undefined area of a multiplex section overhead field in a section overhead field of an STM frame. Bits are written, and transmission error correction is performed based on the check bits.

Further, according to the second aspect of the present invention, the code arithmetic circuit interleaves the input data character string by k bits (k is a natural number) and corrects the transmission error correction for the k-bit interleaved signal. Perform encoding / decoding. Alternatively, according to the invention as set forth in claim 3, the sign operation circuit performs division for dividing the AU-4 signal by a predetermined generator polynomial, and the check bit insertion circuit uses the remainder of the division as the check bit. Write.

According to the fourth aspect of the present invention, the sign operation circuit performs division for dividing the AU-4 signal by a predetermined generator polynomial, and the check bit insertion circuit converts the remainder of the division to the remainder. Write as check bit. Alternatively, according to the fifth aspect of the present invention, the transmission line error correction code circuit is arranged between a transmission line and a multi-section protection circuit for switching a transmission line when a failure occurs in the multiplex section. Whether the switch used in the circuit is on or not is determined based on the bit error rate after error correction.

According to the present invention, the transmission line error correction code circuit is disposed between the transmission line and a multiplex section protection circuit for switching a transmission line when a failure occurs in the multiplex section. Whether the switch used in the protection circuit is on or not is determined based on the bit error rate after error correction.

According to a seventh aspect of the present invention, the transmission line error correction code circuit of the second aspect is disposed between a multi-section protection circuit and a multi-section termination circuit, and the multi-section protection circuit is provided in a multi-section. When a fault occurs, the transmission path is switched, the multi-section termination circuit terminates the processing in relation to the multi-section overhead field, and the switch used in the multi-section protection circuit switches the bit error rate after error correction. And turns on based on the check bit.

According to the eighth aspect of the present invention, the transmission line error correction code circuit is arranged between a multi-section protection circuit and a multi-section termination circuit, and the multi-section protection circuit has a fault in the multi-section. Switching the transmission path in the case, the multi-section termination circuit terminates the processing in relation to the multi-section overhead field, the switch used in the multi-section protection circuit corresponds to the bit error rate after error correction, Also, it is turned on based on the check bit.

According to the ninth aspect of the present invention, in the transmission line error correction coding circuit, the serial / parallel conversion circuit generates m (m is an integer satisfying m> 1) data from the input data sequence. Then, the logical operation circuit realizes m clocks of the division logic by the generator polynomial in one clock for the m data output from the serial-parallel conversion circuit, and generates a check bit. A check bit read / write circuit stores the check bit in a section of the STM frame.
Write and add to an undefined area of the multiple section overhead field in the overhead field, or extract from the undefined area.

According to the tenth aspect of the present invention, the logical operation circuit includes a plurality of exclusive OR circuits, and the first and second exclusive OR circuits.
And a plurality of shift registers that hold and output data input from any one of the third ports for one clock. The first port is any one of m output ports of the serial / parallel conversion circuit, and the second port is an output port of any one shift register other than the own shift register. The third port is an output port of means for calculating an exclusive OR of the output from the first port and the output from the second port.

[0034]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a transmission line error correction coding circuit 1 (FIG. 1A) and a transmission line error correction decoding circuit 2 (FIG. 1B) according to a first embodiment of the present invention. The transmission line error correction code circuit 1 and the transmission line error correction decoding circuit 2 realize a cyclic hamming code capable of correcting a single error, and include a transmission line termination device (L
T).

In this embodiment, A including a pointer
A signal of U (Administrative Unit) unit is used as a reporting unit, but for a normal VC-3 and VC-4 path,
AU-4 unit signal and VC-4-Xc pad
Then, a signal obtained by dividing AU-4-Xc by X is used as a reporting unit. In the latter case, since the AU-4-Xc can be described as a report in AU-4 units after the X-parallel expansion of AU-4-Xc, it will be described below as a report in AU-4 units. The AU-4 unit signal is used as the report unit because a phase difference occurs at the time of clock switching, and data may use the H3 byte of the pointer. Therefore, if this problem does not occur, VC-4 may be used as the reporting unit. In this embodiment, a serial processing type for directly processing an AU-4 unit signal is used.
The case of 1, that is, corresponds to 1-bit interleaving. Here, 15 bits are required for the check bits, and only 2 bytes out of the 24 bytes available in the multiple section overhead (MSOH) are used. Therefore, this code is a (18880, 18865) shortened Hamming code.

The transmission line error correction code circuit 1 is shown in FIG.
As shown in (1), it is composed of a sign operation circuit 3 and a check bit insertion circuit 4, and has a function of encoding a report in AU-4 units including a pointer and writing a check byte into the multiplex section overhead MSOH. . The check bit insertion circuit 4 has a function of storing a check bit in an unused portion of the multiplex section overhead MSOH. On the other hand, transmission path error correction decoding circuit 2
Has a decoding operation circuit 5 and a check bit branching circuit 6, as shown in FIG. 1B, and has a function of checking a code word and correcting a report bit when a different code word is obtained. Have. This transmission line error correction decoding circuit 2
It has a function of correcting only an arbitrary one-bit error in a codeword even when multiple errors occur in one frame. Therefore, error propagation due to decoding can be minimized. For example, the input error rate at which the error rates before error correction and after error correction become equal is about 10 ^{-5. If the} transmission path error rate is better than this, a coding gain can be obtained by error correction. The check bit branching circuit 6 has a function of extracting a check bit from the multiplex section overhead MSOH and passing the check bit to the decoding operation circuit 5 together with the notification.

Next, FIGS. 2 and 3 show an example of the configuration of the sign operation circuit 3 and the decoding operation circuit 5. FIG. The sign operation circuit 3 shown in FIG. 2 includes an exclusive OR circuit 7, a shift register 8 composed of a flip-flop, and a selector 9 having a selector switch. Each shift register 8 generates a remainder obtained by dividing a polynomial representing a data stream by a primitive polynomial (x ¹⁵ + x + 1) and outputs the remainder as signals P1 to P15. The selector 9 selects a report signal to be passed through and a check bit signal passed through each shift register 8. After passing through the data stream, the selector 9 inverts the selector switch so that the remainder of the division is divided into multiple section over data. It has a function of adding to the head MSOH.

On the other hand, the decoding operation circuit 5 shown in FIG.
Exclusive OR circuit 7, shift register 8, 3-input AND gate 10 with inverted input terminal, 3-input AND gate 11, 5-input AND gate 12 with inverted input terminal
And one frame buffer 13. The decoding operation circuit 5 calculates (x ¹³ + x ¹²
+ X ¹¹ + x ⁶ + x ⁴ + x ³ +1), and the remainder (syndrome) obtained by dividing the result by (x ¹⁵ + x + 1) is output as signals S1 to S15. If there is no error in the data, the syndrome is "0", but if there is an error in the data, a signal other than "0" is output. Therefore, 15
If the number and position of "1" in the bits are known, it is possible to identify which bit is wrong.

The decoding operation circuit 5 causes the non- "0" syndrome to circulate in the shift register 8 and the data in the one-frame buffer 13 at the same clock. Non- "0" syndrome must be "1000000000000" after patrol.
00 ". In this case, since the output data bit of one frame buffer 13 is erroneous, the erroneous bit is corrected by the exclusive OR circuit 7. More specifically, one unit of the error correction report block is from the fifth line of the AU-4 to the payload including the pointer on the fourth line of the next frame. Figure 4 shows this situation.
Shown in By using such a phase of the notification block, the number of buffer circuits can be reduced.

In the first embodiment described above,
Although an example in which the sign operation circuit 3 and the decoding operation circuit 5 are configured using the shift register 8 has been described, the invention is not limited thereto.
The sign operation circuit 3 and the decoding operation circuit 5 may be configured by using only the exclusive OR circuit 7. If this circuit configuration is simple, the shift register 8 does not always need to be used.

Next, a second embodiment of the present invention will be described. FIG. 5 is a block diagram showing an example of a configuration of a code operation circuit 14 used in a transmission line error correction coding circuit according to a second embodiment of the present invention, and FIG. 6 is used in a transmission line error correction decoding circuit according to the second embodiment. FIG. 14 is a block diagram illustrating an example of a configuration of a decoding operation circuit 15. In these figures, parts corresponding to the respective parts in FIGS. 2 and 3 are denoted by the same reference numerals,
The description is omitted.

In this embodiment, a signal in AU-4 unit is first separated into bytes, and encoding / decoding is performed on each of the parallelly developed signals. This corresponds to the case where k = 8, that is, 8-bit interleaving in the first aspect of the present invention. Therefore, the code operation circuit 14 shown in FIG. 5 and the decoding operation circuit 15 shown in FIG. 6 are provided with a 1: 8 separation circuit 16 and an 8: 1 multiplexing circuit 17. Further, the decoding operation circuit 15 is provided with the ８ frame buffer 18 for the same reason.

Also, since 12 bits of check bits are required for each separated signal, a total of 12 bytes of check bytes are required. Therefore, in this embodiment, all check bytes are
It can be stored in an empty byte of the overhead MSOH.
This code is a (2370, 2358) shortened Hamming code. Further, in this embodiment, as in the first embodiment, only a single error correction in each of the separated signals is enabled.

Each shift register of the sign operation circuit 14 shown in FIG. 5 generates a remainder obtained by dividing a polynomial representing a data stream by a primitive polynomial (x ¹² + x ⁶ + x ⁴ + x + 1) and outputs the remainder as signals P1 to P12. I do. Also, as in the first embodiment, the notification signal to be passed through and each shift register 8
Selector 9 for selecting the check bit signal passed through
And has a function of inverting the selector switch after passing the data stream and writing the remainder data of the division to the multiplex section overhead MSOH.

On the other hand, the decoding operation circuit 15 shown in FIG.
Is (x ¹¹ + x ¹⁰ + x ⁷ + x ⁶ + x ³
+ X ² + x) and multiply the result by (x ¹² + x ⁶ + x ⁴ +
x + 1) and the remainder (syndrome) divided by the signals S1 to S1
Output as S12. In this embodiment, similarly to the decoding operation circuit 5 of the first embodiment, "10000000"
Only when "0000" is output, the error is corrected. However, in this embodiment, since eight bit errors in one frame, that is, one byte error can be corrected, the correction capability is superior to that of the first embodiment. However, more check bits are required.

In the transmission line error correction decoding circuit in this embodiment, up to one byte in one report can be corrected. That is, a maximum of 8 bits in the signal of the AU-4 unit can be corrected, and the error correction capability is much better than the conventional Hamming code.

In the second embodiment described above,
An example in which the sign operation circuit 14 and the decoding operation circuit 15 are configured using the shift register 8 has been described. However, the present invention is not limited to this, and the sign operation circuit 14 and the decoding operation circuit 15 are exclusive as in the first embodiment. Alternatively, the shift register 8 may not necessarily be used if the circuit configuration is simple.

Next, a third embodiment of the present invention will be described. In this embodiment, a transmission line error correction code circuit and a transmission line error correction code circuit (these are collectively referred to as FE
As shown in FIG. 7, a multi-section protection circuit (MSP: Multiplex Section Protection) and a multi-section termination circuit (MST: Multiplex Section Protection) in a transmission line terminating device LT (multiplexing terminal device) recommended by CCITT. Ter
mination). This is based on the following two reasons. The first reason is that if the transmission path is switched according to the transmission path error rate before error correction, the meaning of correcting the error is reduced by half. The second reason is that the transmission side checks the parity of the encoded signal and transmits it, while the reception side checks the parity including the hamming check byte, thereby eliminating the transmission line error correction decoding circuit. This is to ensure compatibility with the transmission system.

Each circuit block shown in FIG.
(CCITT Recommendations, G78
1, 782, 783). PTE is a path termination circuit, REP is a repeater, LS is a low-speed interface, HS is a low-speed interface, HUG is a high-order path unquip generation circuit,
MSA (Multiplex Section Adaption) is a multiplex section adaptation circuit, RST (Regenerator Section Terminatio)
n) is a relay section termination circuit, SPI (SDH Ph)
ysical Interface functio
n) is the SDH physical interface.

The multi-section adaptation circuit MSA is a functional circuit that generates an AU from a higher-order path and vice versa, and also assembles / disassembles an AU group. Therefore, the multisection adaptation circuit MSA performs byte interleaving demultiplexing and pointer generation and processing. The multi-section protection circuit MSP switches the transmission path in units of STM-N in response to a fault occurring in the multi-section. Multiple section protection circuit MSP in conventional SDH transmission system
Are K1 and K2 between the multi-section termination circuit MST.
In this embodiment, the multi-section protection circuit MSP is activated by a switching trigger after passing through the FEC.

The multi-section termination circuit MST is a functional circuit for processing the multi-section overhead MSOH. Multiple section overhead MSOH
Are B2, K1, K2, D4 to D12, Z1, Z2, Z
3 and other undefined bytes. Therefore, the multi-section termination circuit MST performs the parity operation (BIP-24
N), functions such as transmission path automatic switching signal communication and data communication are performed at a multiplex section speed.

The relay section termination circuit RST is a functional circuit that processes a relay section overhead (RSOH). RSOH is A1, A2, B1, C1,
E1, F1, D1 to D3, and other undefined bytes. Therefore, the relay section termination circuit RST performs frame synchronization, parity calculation (BIP-8), and multiplicity (S
Functions such as TM-N) definition, order wire, alarm oscillation / detection, and data communication are performed at the speed of the relay section. The SDH physical interface SPI is a circuit that provides an interface between the electrical output of the relay section terminating circuit RST and the physical transmission medium.
/ OR.

In FIG. 7, all paths are STM-1
Therefore, the FEC that processes the AU notification signal excluding the SOH from one frame in the STM-N can encode paths of all speeds. For example, a VC-3 path is defined by three VC-3s with a pointer indicating the location of the J1 byte of each path overhead POH as defined in CCITT Recommendations G707, 708, and 709. AU-3, which is mapped to one frame in STM-N. The VC-4-Xc high-speed path is provided with a section overhead SOH for each VC-4, and becomes a signal of one frame unit in the STM-N. In this case, the pointer indicating J1 is the first pointer. It is attached to only one frame in STM-N. In any case, by applying error correction in AU-4 units excluding the section overhead SOH from one frame in the STM-N, it can be applied to all path units.

Also, STM-N data having an arbitrary transmission line speed is multiplexed in STM-1 units. Regardless of the transmission line speed, if the SDH transmission method is used, the FEC according to this embodiment is used. Can be applied. After performing the processing described in the first embodiment or the second embodiment, the transmission path error correction code circuit passes the data to the multiplex section termination circuit MST. As a result, after data is added to the section overhead SOH,
It becomes an STM-1 signal and becomes a multiplex section termination circuit MST.
At STM-N, and transmitted after being converted into an optical signal.

On the other hand, the received STM-N signal is
The separation circuit separates the signal into STM-1.
The signal in the unit of M-1 is transmitted to the relay section terminating circuit RST and the multiplex section terminating circuit MST by the section overhead S other than the Hamming check byte.
OH is terminated and input to the transmission path error correction decoding circuit. In the transmission line error correction decoding circuit, the error correction function described in the first embodiment or the second embodiment is realized, and the corrected AU-4 unit signal is transferred to a subsequent circuit. Thereby, error-free transmission is realized.

As described above, in the conventional SDH transmission system, communication of the K1 and K2 transmission line automatic switching signals is performed between the multi-section termination circuit MST and the multi-section protection circuit MSP to perform multi-section protection. Although the transmission line is switched in the circuit MSP, in this embodiment, the multi-section protection circuit MSP is activated by a switching trigger after passing through the FEC. Therefore, F
The EC requires a transmission path switching trigger transmission function.

FIGS. 8A and 8B show the transmission line error correction coding circuit 19 and the transmission line error correction decoding circuit 2.
0 shows an example of the configuration. The switching trigger transmitting circuit 22 and the switching trigger receiving circuit 24 have a BIP-8 arithmetic function circuit therein, monitor the error rate after error correction, and transmit the switching trigger. Only one byte is required for the BIP-8, and it is assumed that the byte is mapped to the multi-section overhead MSOH.

The switching trigger transmitting circuit 22 and the switching trigger receiving circuit 24 simply change the threshold value of the multi-section protection circuit MSP using the relational expression between the input bit error rate of the Hamming code and the output bit error rate. Or just In this case, neither the switching trigger sending / receiving function nor the new BIP-8 byte is required in the FEC. Therefore, the circuit has the same configuration as in FIGS. 1 (a) and 1 (b). However, the trigger is transmitted by the multiple section termination circuit MST.

Further, double error detection may be added as an FEC function by adding only one bit in addition to the check bit. As a result, by performing a 1-bit parity operation on the message after the error correction, it is possible to detect a double error. In this case, the switching trigger may be sent to the multi-section protection circuit MSP after a protection stage of several frames.

The check bit + BIP insertion circuit 21
It has a function of accommodating check bits and BIP-8 in unused portions of the multi-section overhead MSOH. On the other hand, the check bit branch circuit 6 has a function of extracting the check bit and the BIP-8 from the multiplex section overhead MSOH, and transferring the check bit and the BIP-8 to the decoding operation circuit 5 together with the notification.

As described above, the present invention proposes a cyclic hamming code for performing code processing and decoding processing in STM-1 units in the transmission line terminating device LT. The transmission line error correction code used in the first embodiment is a cyclic Hamming code that processes signals in STM-1 units in series. The Hamming code has a code efficiency almost equal to the optimum efficiency, and can minimize a bit rate increase, which is the most severe limiting factor in ultra-high-speed communication. In the code used in the first embodiment, since 15 bits are required for the check bits, the error can be corrected using only 2 bytes out of the 24 empty bytes of the multi-section overhead MSOH. The error correction capability can correct one error in one frame. That is, there is a possibility that an error rate up to 5.3 × 10 ^-5 is passed without error.

The error correction code used in the above-described second embodiment is a cyclic Hamming code for processing a signal obtained by expanding a signal in AU-4 units into eight columns in parallel. The code used in the second embodiment has the ability to correct an error of up to 1 byte (8 bits) in an STM frame. That is, there is a possibility that a signal having an error rate of up to 4.3 × 10 ⁻⁴ is passed without error. Second
The code used in the embodiment is that the check bit is 1
Two bytes are required, and all of them can be accommodated in the empty bytes of the multiple section overhead MSOH of the STM-1 frame.

FIG. 9A shows the section overhead SOH when the circuit according to the first embodiment is used.
FIG. 9B shows the arrangement of the section overhead SOH when the circuit according to the second embodiment is used. The arrangement of the section overhead SOH shown in FIG. 9 is merely an example, and any location may be used as long as empty bytes are used. In FIG. 9, the dark portion is the current free byte. Relay section over
Since the head RSOH may be rewritten by a regenerative repeater on the transmission line, it cannot be used for storing the code check byte of the present invention.

The error correction code of the present invention does not change the bit rate and can be received even in a transmission system having no transmission line error decoding circuit. In addition, the encoding method according to the present invention can handle all speed paths with one type of circuit, which is more advantageous than preparing a circuit for each path. That is, since the encoding circuit and the decoding circuit are generally applicable, the development or manufacturing cost of the circuit can be reduced. That is, the configuration of the first embodiment and the configuration of the second embodiment can be selectively used depending on the characteristics of the transmission path. In other words, on a transmission line having a relatively good error rate characteristic but with limited free bytes, the code in the first embodiment is replaced by a second embodiment on a transmission line with a relatively severe error rate characteristic and a loosely limited free byte. The symbols in the example are more suitable.

Next, another example of the configuration of the sign arithmetic circuit illustrated in FIG. 2 will be described. FIGS. 10 and 11 are diagrams showing a second configuration example of a code operation circuit (hereinafter, referred to as an error correction code processing circuit). The error correction code processing circuits shown in these figures are composed of (18880, 18865) Hamming. It forms a code serial processing operation circuit.

The serial processing circuit shown in FIG. 11 is realized by a logical operation circuit using a shift register for realizing normal serial processing. Each shift register c1
c15 is a 1-bit register that sequentially shifts data input to the uppermost shift register c1 toward the lowermost shift register c15. Here, the data held in each of the registers c1 to c15 is also c1 to c.
The data sequence sequentially input to the shift register c1 is i1 to i8. A′1 to a′1
5 is a check bit, and CW is a check bit a '
This is a check bit write circuit for writing 1 to a'15 and adding it to the data strings i1 to i8.

The shift register c1 stores the exclusive OR of the data strings i1 to i8 and the data (c15) output from the shift register c15.
2 includes data (c output from the shift register c1).
1) and data (c) output from the shift register c15.
15) is connected so that an exclusive OR with 15) is input. That is, the shift register group shown in FIG.
Generating a data sequence i1~i8 input polynomial x ¹⁵ + x +
The logic for generating the remainder when divided by 1 is realized.

Since the (18880, 18865) Hamming code is a shortened Hamming code, 32767 data to which 13887 dummy bits are added are input. Therefore, check bit a'1
32767 clocks are required to obtain ~ a'15. Here, the operation speed of the shift register is 156M
Hz. In the shift register shown in FIG. 11, there is data input on the opposite side (shift register c1 side) from the direction in which the clock advances.

Here, in the above-described serial processing circuit, a state in which one clock has elapsed from a certain state will be considered. In this case, the relationship between the data string and the value of each shift register is i'8 = arbitrary, i'7 = i8, i'6 = i
7, i'5 = i6, i'4 = i5, i'3 = i4, i '
2 = i3, i′1 = i2, c′1 = i1 + c15, c ′
2 = c1 + c15, c′3 = c2, c′4 = c3, c ′
5 = c4, c′6 = c5, c′7 = c6, c′8 = c
7, c'9 = c8, c'10 = c9, c'11 = c1
0, c′12 = c11, c′13 = c12, c′14 =
c13, c′15 = c14. However, i'1 ~
i'8, c'1 to c'15 are data after one clock has elapsed, and correspond to i1 to i8 and c1 to c15, respectively.

FIG. 12 shows this relationship in a matrix format.
Is the determinant shown in FIG. In this determinant, the input of the matrix is a 23-dimensional vector (i8 to i1, c1 to c15), and the output is a 15-dimensional vector (c'1 to c'15). The 23 × 23 initial matrix in this determinant consists of three parts. The first part is 7x15 0
The matrix M1, the second part is a unit matrix M2 of 15 × 15, and the third part is a negative feedback vector M3 representing feedback.

Based on this determinant, the relationship between the state of each shift register after eight clocks (c ″ 1 to c ″ 15) and the input vector (data sequence i1 to i8) can be easily obtained. is there. That is, each column vector of the initial matrix may be shifted to the left in the figure seven times using the property of the cyclic code. Thereby, the determinant shown in FIG. 13 is obtained. Hereinafter, the 23 × 23 matrix in this determinant is referred to as a final state matrix.

The parallel processing deriving method using the above-described matrix is as follows.
Nakamura and D. -W. How to derive Choi's scrambled parallel processing circuit configuration (AT & T Technical Journa
1, Vol. 65, Issue 5, 123, 1986). For example, if the calculation amount is estimated based on the number of bits to be handled, Nakamura's O (8220)
83584); -W. Choi's is O (423
2) In the case of the present invention, it is O (345). D. −
W. In Choi's method of deriving a scrambled parallel circuit,
Since the 8th power of a 23 × 23 matrix is required, the calculation becomes enormous.

Here, the second configuration example will be described again. According to FIG. 13, the values of the shift register after 8 clocks have passed are c ″ 1 = c8 + i8, c ″ 2 = c8 + c9 + i
7, c ″ 3 = c9 + c10 + i6, c ″ 4 = c10 + c
11 + i5, c ″ 5 = c11 + c12 + i4, c ″ 6 =
c12 + c13 + i3, c ″ 7 = c13 + c14 + i
2, c ″ 8 = c14 + c15 + i1, c ″ 9 = c1 + c
15, c ″ 10 = c2, c ″ 11 = c3, c ″ 12 = c
4, c ″ 13 = c5, c ″ 14 = c6, c ″ 15 = c7
Becomes

Therefore, if a circuit for realizing the logic for eight clocks shown in FIG. 13 with one clock is constituted, it becomes an eight-parallel encoding circuit. However, since 32767 is not divisible by 8, another 1-bit dummy bit is added to perform the operation. The number of clocks required to obtain the check bits a′1 to a′15 is 32768/8 = 4096. Here, the shift register is 19.5 MH
It operates with the clock of z.

FIG. 10 is a diagram showing an eight-parallel processing operation circuit that performs eight-parallel processing. In the circuit shown in this figure,
Although the number of shift registers constituting the logical operation circuit is fifteen as in the case of FIG. 11, the number of exclusive ORs used is sixteen. By the way, in the circuit configuration obtained by Nakamura's method, the exclusive OR is at least 29.
Required. Therefore, it can be seen that the second configuration example can realize eight parallel processing with a simpler circuit configuration than the conventional configuration.

In FIG. 10, a serial-to-parallel conversion circuit (1: 8 DEMUX) d is provided on the input side, and its eight output ports, fifteen shift registers, and sixteen exclusive ORs are provided. Are connected to realize the logic represented by the determinant shown in FIG. This connection is completely different from that shown in FIG. A check bit write circuit CW is provided on the output side of the shift register.

Next, a third configuration example of the error correction code processing circuit will be described with reference to FIGS.
FIG. 14 is a diagram showing a configuration of a serial processing operation circuit for a Hamming code of (18880, 18865). In this drawing, the same reference numerals are given to parts common to FIG. In the circuit shown in this figure, unlike the circuit shown in FIG. 11, the positions of the input data strings i1 to i8 are arranged in the direction in which the clock advances (c15 side). The number of clocks required to obtain the check bits of this circuit is 32
752 clocks.

In the serial processing circuit of FIG. 14, a state in which one clock has elapsed from a certain state will be considered. In this case, the relationship between the data string and the value of the shift register is i'8 = arbitrary, i'7 = i8, i'6 = i7, i '
5 = i6, i'4 = i5, i'3 = i4, i'2 = i
3, i′1 = i2, c′1 = i1 + c15, c′2 = c
1 + c15 + i1, c′3 = c2, c′4 = c3, c ′
5 = c4, c′6 = c5, c′7 = c6, c′8 = c
7, c'9 = c8, c'10 = c9, c'11 = c1
0, c′12 = c11, c′13 = c12, c′14 =
c13, c′15 = c14.

After eight clocks have elapsed, the values of the shift registers are c ″ 1 = c8 + i8, c ″ 2 = c
8 + c9 + i7 + i8, c ″ 3 = c9 + c10 + i6 +
i7, c ″ 4 = c10 + c11 + i5 + i6, c ″ 5 =
c11 + c12 + i4 + i5, c ″ 6 = c12 + c13
+ I3 + i4, c ″ 7 = c13 + c14 + i2 + i3,
c ″ 8 = c14 + c15 + i1 + i2, c ″ 9 = c1 +
c15 + i1, c "10 = c2, c" 11 = c3, c "
12 = c4, c ″ 13 = c5, c ″ 14 = c6, c ″ 1
5 = c7.

On the other hand, FIG. 15 shows the processing in eight parallel (1
8880, 18865) is a diagram showing the configuration of an 8-parallel processing arithmetic circuit for Hamming codes, in which the same reference numerals are given to parts common to FIG. 3275
Since 2 is divisible by 8, there is no need to add a 1-bit dummy. Further, 4094 clocks are required to obtain the check bits a'1 to a'15.

Here, the number of shift registers is fifteen as shown in FIG. 14, but the number of exclusive OR is two.
The number is increased to four (here, one exclusive OR of three inputs is counted as two). In FIG. 15, a serial-to-parallel conversion circuit (1: 8 DEMUX) d is provided on the input side, and the output of each of the eight ports, 15 shift registers, and 24 exclusive ORs is shown in FIG. Wired to implement the logic shown. Also in the third configuration example described above, the number of exclusive ORs is smaller than that of Nakamura. If there is a limitation on the circuit, either the second or third configuration example may be used.

The code processing circuit described above requires 32767 or 32752 clocks for abbreviated codes, and about half of the clocks are for the dummy bit 0. Methods for reducing this useless clock are conventionally known (for example, S. Lin and DJCostello, Jr.,
"Error Control Coding: Fundamental and Applicatio
ns ", Prinston-Hall 1983).

When this is applied to a (18880, 18865) Hamming code, the result is as shown in FIG. Here, a polynomial x ¹³ + x ¹² + x ¹¹ + x ⁶ + x ⁴ + x ³ + for shortening
1 is multiplied by the data, and the remainder obtained by dividing the result by the generator polynomial is output. Note that a polynomial for shortening is obtained by x ^{(n−m + j)} mod (x ¹⁵ + x + 1). Here, n is the code word length 18880, m is the report length 18864, and j is the number of dummy bits 13887.
FIG. 16 shows a circuit configuration of the serial processing. The number of clocks required is 186 Mbit / s and 18864.

FIG. 17 shows an eight parallel processing circuit. The operation logic at one clock (19.44 MHz) is as follows. c'1 = i8 + i6 + i5 + i4 + c8 c'2 = i7 + i6 + i3 + c8 + c9 c'3 = i6 + i5 + i2 + c9 + c10c'4 = i8 + i5 + i4 + i1 + c10 + c11 C'5 = i8 + i7 + i + 12 + c3 + i3 + i3 + i3 + i + i3 + i + i3 + i + i3 + i + i3 + i + i3 + i + i3 + i + i3 + i + i3 + i3 + i + i3 + i + i3 + i + i3 + i + i3 + i + i3 + i + i3 + i3 + i + i3 + i + i3 + i + i3 + i + i3 + i + i3 + i + i3 + i + i3 + i + i3 + i + i3 + i + i3 + i + i3 + i + i3 + i + i3 + i + c3 + i3 + i + i3 + i + i3 + i + i3 + i + i3 + i + i3 + i + i3 + i ++
4 c'8 = i7 + i5 + i4 + i1 + c14 + c15 c'9 = i6 + i4 + i3 + c1 + c15 c'10 = i5 + i3 + i2 + c2 c'11 = i4 + i2 + i1 + c3 c'12 = i8 + i3 + i1 + c4 + i8 + i3 + i8 + i3 + i8 + i3 + i8

The writing of the check bit is 188
64/8 = 2358 clocks later. According to the circuit of FIG. 17 (fourth configuration example), the number of useless clocks can be reduced and a simple C-MOS FPGA can be used, so that not only low power consumption and circuit versatility but also propagation delay can be achieved. Can also be suppressed. However, the number of exclusive ORs is 61, which is 3.8 times the second configuration example and the third
2.5 times as large as the above configuration example is required.

Next, experimental results of the circuit according to the third configuration example will be described with reference to FIG. The experiment performed here is an STM-1 (156 Mbit / s) back-to-back optical transmission experiment. FIG. 18 is a diagram showing an improved bit error rate (bit error rate: BER), where the vertical axis represents the bit error rate and the horizontal axis represents the optical power. As is apparent from this figure, the BER was improved by the parallel processing type error correction code processing circuit (the circuit shown in FIG. 15). For example, a coding gain of about 3 dB was obtained at a BER of 10 ^-9 . .

FIG. 15 shows the input BE to the error correction circuit.
FIG. 9 is a diagram showing a relationship between R and an output BER from the same circuit;
The solid line in the figure is a theoretical curve when errors are assumed to be random. As shown in this figure, the results obtained in the experiment are consistent with the theoretical curves. Therefore, (1
8880, 18865) It was confirmed that the function of the Hamming code was correctly realized.

As described above, according to the second, third, and fourth configuration examples, the SDH error correction code characterized by a large code word can be converted to a low-speed clock, low power consumption,
Further, it can be realized with a simple circuit configuration. Therefore, it is suitable for constructing an economical, high-quality and general optical transmission system in the SDH terrestrial optical transmission system.
Further, the circuits according to the second and third configuration examples can be realized with the number of exclusive ORs being about １ ／ to の of the number according to the fourth configuration example. More preferred. Further, the circuit according to the fourth embodiment requires only a small number of clocks, and thus is suitable for use in a case where the number of clocks in which delay is a problem is limited.

In each of the above configuration examples, m =
Although an example in which the number of bits is eight, that is, an example in which the processing unit is eight bits has been described, the present invention is not limited to this, and it is needless to say that the present invention is applicable to an arbitrary number of bits. As described above, the embodiments of the present invention have been described in detail with reference to the drawings. However, the specific configuration is not limited to these embodiments, and there are design changes and the like that do not depart from the gist of the present invention. Are also included in the present invention.

[0090]

As described above, according to the present invention,
Since errors can be corrected without increasing the bit rate, which is the strictest restriction condition for an ultra-high-speed transmission line, a high-quality transmission line can be provided. STM of various speeds
Since an error correction code that can be commonly applied to a multiplexed signal can be provided, circuit development and manufacturing costs can be reduced due to the generality of the encoding circuit and the decoding circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a transmission line error correction coding circuit 1 and a transmission line error correction decoding circuit 2 according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating an example of a configuration of a sign operation circuit 3.

FIG. 3 is a block diagram illustrating an example of a configuration of a decoding operation circuit 5.

FIG. 4 is a diagram illustrating an example of an error correction report block.

FIG. 5 is a block diagram illustrating an example of a configuration of a code operation circuit 14 used in a transmission line error correction coding circuit according to a second embodiment of the present invention.

FIG. 6 is a block diagram illustrating an example of a configuration of a decoding operation circuit 15 used in a transmission line error correction decoding circuit according to a second embodiment of the present invention.

FIG. 7 is a block diagram illustrating an example of an arrangement in a transmission system of a transmission line error correction coding circuit and a transmission line error correction decoding circuit according to a third embodiment of the present invention.

FIG. 8 is a block diagram illustrating a configuration of a transmission line error correction coding circuit and a transmission line error correction decoding circuit according to a third embodiment of the present invention.

FIG. 9 is a diagram showing an example of an arrangement of the section overhead SOH when the circuits according to the first and second embodiments are used.

FIG. 10 is a diagram illustrating a second configuration example of the code operation circuit 3 of the transmission error correction code processing circuit according to the first embodiment of the present invention.

FIG. 11 is a diagram showing a configuration of an error correction code processing circuit (serial processing operation circuit) according to the configuration example.

FIG. 12 is a diagram illustrating a configuration method of an error correction code processing circuit according to second and third configuration examples of the code operation circuit 3.

FIG. 13 is a diagram illustrating a configuration method of an error correction code processing circuit according to second and third configuration examples of the code operation circuit 3.

FIG. 14 is a diagram showing a configuration of an error correction code processing circuit (serial processing operation circuit) according to the third configuration example.

FIG. 15 is a diagram showing a configuration of an error correction code processing circuit (8 parallel processing operation circuits) according to the configuration example.

FIG. 16 is a diagram illustrating a configuration of an error correction code processing circuit (serial processing calculation circuit) according to a fourth configuration example of the code calculation circuit 3.

FIG. 17 is a diagram showing a configuration of an error correction code processing circuit (8 parallel processing operation circuits) according to the same configuration example.

FIG. 18 is a diagram for describing experimental results obtained by an error correction code processing circuit according to a third configuration example of the code operation circuit 3.

FIG. 19 is a diagram for explaining an experimental result by the circuit.

FIG. 20 is a diagram illustrating a conventional transmission path error correction code insertion process.

[Explanation of symbols]

1, 19: transmission line error correction coding circuit, 2, 20: transmission line error correction decoding circuit, 3, 14: code operation circuit, 4: check bit insertion circuit, 5, 15: decoding operation circuit, 6: check bit branch Circuit, 21 ... Check bit + BIP
Insertion circuit, 23 ... check bit + BIP branch circuit,
a'1 to a'15 ... check bits, c1 to c15 ... shift registers, CW ... check bit writing circuits, d
... serial-parallel conversion circuit, i1 to i8 ... data strings.

────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Seiji Nakagawa 1-6, Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (56) References JP-A-52-86011 (JP, A) 6-318931 (JP, A) JP-A-6-29956 (JP, A) IEEE TRANSACTIONS ON COMMUNICATIONS Vol. 38, No. 4 (1990-4), W.C. D. Grover T. E. FIG. Moore, “Design and Charactorization of an Error-Correcting Code for the SONE T STS-1 Tributary”, p. 467-476 IEICE Technical Report, CS 96-35 (1996-6-24), Masato Tomizawa et al., SDH Optical Communication System with Error Correction Function, p. 21-26 (58) Field surveyed (Int.Cl. ⁷ , DB name) H04J 3/00-3/26 H04L 1/00-1/24

Claims (10)

(57) [Claims] 1. A transmission line error correction code circuit applied to an SDH network, comprising: a synchronous transfer module (STM) according to a recommendation of the International Telegraph and Telephone Consultative Committee, comprising a VC path or matching an input data string. Each AU drawn from the frame
-4 signal, a code operation circuit for performing transmission error correction coding / decoding, and a check bit in an undefined area of a multiplex section overhead field in a section overhead field of an STM frame. A transmission line error correction code circuit, comprising: a check bit insertion circuit for writing; and performing transmission error correction based on the check bit. 2. The sign arithmetic circuit interleaves the input data character string by k bits (k is a natural number),
2. The transmission path error correction coding circuit according to claim 1, wherein transmission error correction coding / decoding is performed on the bit-interleaved signal. 3. The method according to claim 2, wherein the sign operation circuit performs division for dividing the AU-4 signal by a predetermined generator polynomial, and the check bit insertion circuit writes the remainder of the division as the check bit. Item 2. A transmission line error correction code circuit according to item 1. 4. A transmission line terminating device using the transmission line error correction code circuit according to claim 2, wherein the code operation circuit performs division for dividing the AU-4 signal by a predetermined generator polynomial. The transmission line terminating device, wherein the check bit insertion circuit writes the remainder of the division as the check bit. 5. The transmission line error correction coding circuit according to claim 2, which is disposed between the transmission line and a multiplex section protection circuit for switching the transmission line when a failure occurs in the multiplex section, and used in the multiplex section protection circuit. A transmission line terminating device for determining whether or not a switch to be turned on is on the basis of a bit error rate after error correction. 6. The transmission line error correction code circuit is disposed between a transmission line and a multi-section protection circuit for switching a transmission line when a failure occurs in a multi-section, and a switch used in the multi-section protection circuit is turned on. 5. The transmission line termination device according to claim 4, wherein the determination is made based on the bit error rate after error correction. 7. A transmission line error correction coding circuit according to claim 2, which is disposed between a multi-section protection circuit and a multi-section termination circuit, wherein said multi-section protection circuit operates when a failure occurs in a multi-section. And the multi-section termination circuit switches the multi-section over
A transmission line termination characterized in that the processing is terminated in relation to the head field, a switch used in the multi-section protection circuit corresponds to the bit error rate after error correction, and is turned on based on the check bit. apparatus. 8. The transmission line error correction code circuit is disposed between a multi-section protection circuit and a multi-section termination circuit, and the multi-section protection circuit switches a transmission line when a failure occurs in a multi-section. The multi-section termination circuit terminates the processing in relation to the multi-section overhead field, and the switch used in the multi-section protection circuit corresponds to the bit error rate after error correction and is turned on based on the check bit. The transmission line terminating device according to claim 4, wherein 9. A serial-parallel conversion circuit that generates m (m is an integer that satisfies m> 1) data from an input data sequence and outputs the data in parallel, wherein: A logic operation circuit for realizing m clocks of division logic by a generator polynomial in one clock for m data output from the serial-parallel conversion circuit and generating a check bit;・
9. A check bit read / write circuit for writing and adding to an undefined area of a multiplex section overhead field in the overhead field or extracting from the undefined area.
The transmission line terminating device according to any one of the preceding claims. 10. The logical operation circuit comprises: a plurality of exclusive OR circuits; and a plurality of shift registers. Each of the shift registers holds input data for one clock and outputs the data. , First, second and third
The first port is any one of m output ports of the serial / parallel conversion circuit, and the second port is An output port of any one of the shift registers other than the shift register, wherein the third port is an output of a means for obtaining an exclusive OR of an output from the first port and an output from the second port 10. The output port of each of the shift registers is connected to the check bit read / write circuit.
The transmission line terminating device according to any one of the preceding claims.