JP3166164B2 - Still video camera - Google Patents

Description

The present invention relates to a still video camera that converts a still image into an electric signal and records the electric signal on an electronic recording medium.

[Conventional technology]

Still video cameras that convert a still image into an electric signal by a photoelectric conversion element such as a CCD and record the electric signal on a recording medium such as a magnetic disk or an IC memory are already known.
This type of recording medium is capable of recording, reproducing, and erasing an image, and the recording medium can be used repeatedly.

[Problems to be solved by the invention]

As described above, the recording medium of the still video camera can delete recorded images, so that editing processing for deleting unnecessary images while reproducing recorded images can be easily performed. However, there is a possibility that an image to be stored is erroneously deleted at the time of editing. An object of the present invention is to solve the above problems.

[Means for solving the problem]

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems. According to a first aspect of the present invention, in a still video camera capable of recording and erasing an image signal, a captured image signal is recorded in a predetermined image recording area of a recording medium. An image signal recording unit, an erasure prohibition mode setting unit for setting a mode for prohibiting erasure of a recorded image, a manual operation member, and in response to an operation of the manual operation member when the erasure prohibition mode is set. A control operation for recording a protection signal for inhibiting erasure of an image recorded in a predetermined image recording area on a recording medium is executed. When the erasure inhibition mode is not set, operation of the manual operation member is performed. Performs a control operation of erasing a recorded image in response to the image signal. A still video camera, characterized in that a control means for executing a control operation for prohibiting.

Further, the still video camera may have a function of deleting the protection signal.

Further, the still video camera may further include a display unit, and the display unit may display that the protection signal is recorded.

The display means may display that the protection signal has been recorded and also display a symbol for identifying an image recording area in which the protection signal has been recorded.

[Operation] At the time of shooting, if there is an image to be saved, set the mode to prohibit image deletion by the prohibition mode setting means.
When the manual operation member is further operated, a protect signal for prohibiting erasure of an image is recorded in a predetermined image recording area of the recording medium in response to the operation. When the mode for prohibiting image erasure is not set, a control operation for erasing the recorded image is executed in response to the operation of the manual operation member.

Then, when the protect signal is recorded, erasure of the recorded image is prohibited.

〔Example〕

Hereinafter, embodiments of the present invention will be described. FIG. 1 is a perspective view showing the appearance of a camera according to the present invention.
Denotes a camera body, 2 denotes a photographing lens, 3 denotes an opening / closing knob for a lens protection barrier, and 4 denotes a shutter button. A first-step pressing thereof closes a switch S1 described later, and a second-step pressing thereof closes a switch S2.

A display unit 5 displays the frame number of the recorded image, the presence / absence of an IC card, the date, and other operation states of the camera.
Reference numeral 6 denotes a finder window, 7 denotes a light emitting window for macro photography, 8 denotes an insertion slot of an IC card for recording an image, 9 denotes a connection portion of a flash device, and 10 denotes a connection contact between the camera body and the flash device. Next, the operation switches will be described. S3 is a slide-type mode switch for switching various functions of the camera, and the selectable modes are as follows.

 OFF: Startup of the camera is prohibited.

REC: Recording mode, internal memory of the camera or removable external recording medium (hereinafter referred to as IC card)
The image is recorded on the.

PLAY: Playback mode, internal memory or IC
The image recorded on the card is reproduced, and a video signal is output. A recorded image is reproduced on a video display device (not shown) based on this signal.

ERASE-ALL: This is an erasing mode for erasing all images recorded in the internal memory and the IC card.

ERASE-SINGL: A single frame erasing mode for erasing one frame of a captured image recorded in the internal memory or the IC card. Even in this mode, the image protected by the protection function described later is not erased.

S4 and S5 are access switches, and switch S4 (UP) functions as a forward switch for recorded images during image playback.
When setting the date, it functions as a switch to increase the date. The switch S5 (DOWN) functions as a switch for reversing the recorded image during image reproduction, and functions as a switch for decreasing the date when setting the date.

S6 is a protect switch for protecting an image to be kept from being accidentally erased among images recorded in an internal memory or an IC card, and is displayed as "PROT." When the switch S6 is in the OFF position, the protect function does not work, and when the switch S6 is in the ON position, the protect function works. When the image is at the REMOVE position, that is, at the release position, the protection state of the once protected image is released.

S7 is a protect / erase operation switch. When the mode switch S3 is turned on when the switch S3 is in the ERASE (either SINGL or ALL position) position, the erase operation is executed.
When the protection switch S6 is turned on while in the PROT position, the protection operation is performed.

S8 is a frame feed switching switch for switching whether to automatically or manually perform the frame feed during the reproduction of the recorded image, and when set to AUTO, that is, automatically, a fixed time regardless of the operation of the access switches S4 and S5 each time. Each time, the recorded image is automatically frame-advanced and sequentially reproduced. When the mode is set to MANUAL, that is, manually, the frames are advanced one by one by operating the access switches S4 and S5.

S9 is a switch for macro photography, and S10 is a switch for setting flash photography.

S12 is a date setting mode switch.
Y (year) → M (month) → D (day) → H (hour) → M1 (minute) →
The mode is cyclically switched in the order of Y (year).

S13 is a date setting switch for setting data of the mode selected by the switch S12.

 FIG. 2 shows a block diagram of a control circuit of the camera.

Reference numeral 30 denotes a CPU that controls the entire camera, and 31 denotes a signal processing unit that performs a recording / reproducing process of a video signal. The details will be described later. Reference numeral 32 denotes a solid-state imaging device (hereinafter, referred to as a CCD) including a CCD or the like, which converts an image incident from the photographing lens 2 into a video signal. 33 is a correlated double sampling unit for the video signal output from the CCD, 34 is an A / D converter for converting the video signal into a digital signal, 35 is a CCD 32, a sampling unit 33, and a synchronizing unit for the A / D converter 34. The clock generation circuit is controlled by control signals INREL and EXSTP output from the CPU 30. A photometric circuit 36 measures the luminance of the subject, outputs the measurement result to the CPU 30, operates as a dimming circuit, and performs dimming control of flash light. A flash device 37 has a light emitting unit and a charging capacitor. Reference numeral 38 denotes a power supply, which is controlled by a control signal PWC output from the CPU 30. A display unit 5 displays the number of image frames and other information as described above. LA is an illumination lamp for macro photography, and PL is an electromagnetic plunger for shutter operation.

40 is the internal memory built into the camera, at least one
It has an image recording capacity of frames (10 frames in this embodiment). 41 is an IC card that can be detached from the camera body, SR
Equipped with semiconductor memory such as AM, and for multiple frames (in this embodiment,
It has an image storage capacity of 32 frames).

Next, the switches will be described. S1 is a switch that is turned on when the release button 4 is pressed in the second step, and S2 is a switch that is turned on when the release button 4 is pressed.
Is a switch that is turned ON by pressing the second step. S3 to S9 and S11 to S13 are switches whose operation units are shown on the camera main body shown in FIG. 1, and their functions are as described above with reference to FIG. S10 is a switch that is turned on when the IC card 41 is inserted from the insertion section 8 of the camera body, and outputs a signal indicating that the IC card 41 is attached.

 Next, a signal transmitted through a signal line will be described.

CHSTA is a signal for instructing the capacitor of the flash device 37 to start charging, CHC is a signal for indicating that the capacitor of the flash device 37 has been charged, FLSTA is a signal for instructing the flash device 37 to emit flash light, and FSTOP is detected by the photometry circuit 36. This signal is for instructing to stop flash emission when the light amount of the flash reaches a predetermined value (when dimming is completed).

INREL is a shutter release start signal that is output from the CPU 30 to the clock generation circuit 35. In response to this signal, the clock generation circuit 35 outputs a signal EXSTA indicating the start of exposure control to the CPU.
Output to 30. EXSTP is an exposure control end signal, which is output from the CPU 30 to the clock generation circuit 35. Further, the shutter release start signal INREL and the exposure control end signal EXSTP are also output to a signal processing unit 31 described later.

CSDP is a signal for controlling signal transmission between the CPU 30 and the signal processing unit 31, SOUT and SIN are data signals transmitted as serial data between the CPU 30 and the signal processing unit 31, and SCK is a CPU signal.
The serial clock signal BUSY transmitted from 30 to the signal processing unit 31 indicates that the signal processing unit 31 is performing signal processing.
A signal transmitted to 0, LBC is a signal indicating that macro shooting is performed, and VOUT is a video signal output from the signal processing unit 31.

FIG. 3 is a block diagram showing details of the signal processing unit 31. Reference numeral 51 denotes a signal processing CPU that controls the entire signal processing unit 31;
Reference numeral 2 denotes a signal processing circuit that performs processing (including compression) on a video signal, and 53 denotes an address generation circuit that receives a clock signal from the clock generation circuit 35 and generates an address signal.

Reference numeral 54 denotes an address signal output from the address generation circuit 53 based on the signal RD / CD output from the signal processing circuit 52, that is, an address signal used when recording the video signal output from the CCD 32 in the buffer memory 55. A multiplexer for selecting one of a bus and an address signal bus when using the buffer memory 55 during signal processing.

56 is an address signal bus AD output from the signal processing circuit 52 based on the signals D1 / D2 output from the signal processing CPU 51.
B1, that is, an address signal bus used when recording and reproducing a video signal with respect to the video recording internal memory 40 and the IC card 41, and a data signal other than the video signal output from the signal processing CPU 51, for example, a frame number, protect data, etc. Is a multiplexer that selects one of the address signal buses ADB2 when recording the signal of the internal memory 40 and the IC card 41.

57 is a video signal bus DB1 and a frame number, protect data, erase data (ERASE), protect remove data (REMOVE),
This is a multiplexer for selecting a data signal bus DB2 other than a video signal such as chrono data.

Reference numeral 58 denotes a D / A converter for converting a digital signal into an analog signal when outputting a video signal.

Next, a signal transmitted through a signal line will be described. Of the signals output from the signal processing CPU 51, ENA is a signal that permits signal processing in the signal processing circuit 52, and REC / PLAY is signal processing in the signal processing circuit 52 that is performed in a recording mode or a playback mode. RE / WR is the internal memory 40,
A signal for controlling writing / reading of a video signal to / from the IC card 41, ERASE is a signal for controlling erasing of a video signal recorded in the internal memory 40, the IC card 41, and CSOUT is for controlling data communication with the IC card 41. Signal, CSIN is internal memory
This signal controls data communication with 40.

FIG. 4 is a perspective view showing the appearance of a flash device detachable from the camera of the present invention. A connection portion 21 that engages with the flash device connection portion 9 of the camera body 1 is provided with a connection electrical contact 22, which contacts the electrical contact 10 of the camera body 1. 23 indicates a light emitting unit.

FIG. 5 shows a circuit diagram of the flash device. Since this circuit is a known circuit, its configuration and operation will be briefly described. In the figure, 61 is a power supply battery, 62 is a booster circuit composed of a DC / DC converter, 63 is a main capacitor for charge storage,
64 is a neon tube, 65 is a trigger circuit, 66 is a xenon discharge tube,
67 indicates a thyristor.

Next, the operation will be described.
To start charging applied to terminal L1
When STA becomes “H”, the booster circuit 62 starts operating, the voltage of the battery 61 is boosted, and the main capacitor 63 is charged.
When the terminal voltage of the main capacitor 63 reaches a predetermined value, the terminal L3
Becomes "H" to notify the CPU 30 of the completion of charging. When the signal FLSTA for instructing light emission of the flash applied from the CPU 30 of the camera to the terminal L4 becomes “H”, the trigger circuit 65 operates to start the light emission of the xenon discharge tube 66. The light metering circuit 36 of the camera detects the reflected light from the subject, and when the light amount reaches a predetermined value, the light emission stop signal FLSTP applied to the terminal L5 becomes “H”, and the light emission is stopped because a reverse bias voltage is applied to the thyristor 67. You.

The configuration of the imaging unit will be described. FIG. 6 is a cross-sectional view taken along a plane including the optical axis of the imaging unit, wherein 2 is a spherical lens having a focal length f, and 70 is a spherical image forming surface of the lens 2.
Reference numeral 71 denotes an optical fiber, the entrance end of which is arranged along a spherical image plane 70, and the exit end of which is arranged on the surface of the CCD 32. If the magnification of the optical fiber 71 is 3 times,
The same image as the image formed on the CCD 32 with the image having the focal length f × 3 can be formed. By using an optical fiber having a magnification several times as described above, the thickness of the imaging unit can be reduced to about the focal length of the lens and the size of the optical fiber unit (for example, 3 mm).
By combining with a C card, the thickness of the camera body can be reduced.

The advantages of using a spherical lens as a photographing lens are as follows. Generally, when an image of an object at infinity is formed using a spherical lens, the image forming surface is a spherical surface concentric with the spherical lens due to the spherical symmetry of the spherical lens. Therefore, in the spherical lens, the on-axis and off-axis aberrations have the same value, and if almost satisfactory on-axis aberration correction can be achieved, the off-axis aberration is also corrected. Therefore, even if it is a small and simple optical system as compared with an ordinary lens system, if appropriate aberration correction is performed, a decrease in the peripheral light amount is small and a lens with a good image forming performance can be obtained. Things.

Next, the control operation of the camera executed by the CPU 30 will be described with reference to the flowcharts shown in FIGS.

FIG. 7 is a flowchart showing an outline of the whole control, in which the state of various switches is checked, and the process proceeds to a processing routine corresponding to the switches. At the start of the control operation, it is checked whether or not the mode changeover switch S3 is set to the OFF position. If the mode changeover switch S3 is OFF, the process proceeds to the OFF processing routine (steps P100 and P101). Mode switch S3 is R
It is checked whether or not the recording mode is set to the EC, that is, if the recording mode is set, the process proceeds to a recording mode processing routine (steps P102 and P103). Press the shutter release button one step to O
The state of the switch S1 to be N is checked, and if it is ON, the process proceeds to the S1 ON processing routine (steps P104 and P105). It is checked whether or not the mode switch S3 is set to PLAY, that is, the playback mode. If the mode is the playback mode, the process proceeds to the playback mode processing routine (steps P106 and P107). Mode switch S
It is checked whether or not 3 is set to ERASE, that is, the erase mode. If it is the erase mode, the process proceeds to the erase mode processing routine (steps P108 and P109). Access switch S4 (UP)
Is checked, and if it is ON, the process proceeds to the S4 processing routine (steps P110 and P111). Access switch S5 (DOW
The state of N) is checked, and if it is ON, the process proceeds to the S5 processing routine (steps P112 and P113). Frame feed switch S8
Is set to AUTO, that is, whether the automatic mode is set. If the automatic mode is set, the process proceeds to the automatic mode processing routine (steps P114 and P115). The frame feed switch S8 is MANUA
L, that is, whether or not the mode is set to the manual mode. If the mode is the manual mode, the process proceeds to the manual mode processing routine (steps P116 and P117). Check the status of the date setting switch S13,
If ON, move to the date processing routine (steps P118, P11
9).

FIG. 8 shows step P101 of the flowchart shown in FIG.
This is a processing routine when the mode changeover switch S3 is turned off. First, each port and the timer are reset (step P131), and it is determined whether or not the display unit indicating that the protection function is operating is ON.
F (steps P132, P133). It is determined whether or not the end display indicating that the number of frames of the recorded image has reached the number of recordable frames is ON, and if it is ON, the display is turned OFF (steps P134 and P13).
Five). It is determined whether or not the display indicating that the IC card 41 is inserted into the camera body is ON. If the display is ON, the display is turned OFF (step P137). The date display is turned off, and the counter display indicating the number of frames of the recorded image is turned off (steps P138, P1
39) The signal PWC for the power supply 38 is set to "H" to shut off the power supply circuit (step P140), and the process returns to the main routine.

FIG. 9 shows step P103 of the flowchart shown in FIG.
The mode changeover switch S3, which is indicated as
9 shows a recording mode processing routine in the case of C). First, it is determined whether or not the mode switch S3 has been switched from the OFF position to the REC position (step P151).
Is set to "L" to turn on the power supply 38 (step P152). It is determined whether or not the IC card 41 is inserted into the camera (step P153), and if so, the IC card display is turned on.
(Step P154), signal CSDP is set to “L” and signal processing is performed.
The card data indicating the recording state (the number of recording frames, etc.) of the IC card 41 is received from the CPU 51, and after the communication is completed, the signal CSDP is set to "H" to end the communication (steps P155, P156, P157). It is determined whether or not the recording section of the IC card 41 is full and whether or not recording is impossible (step P158).
(Steps P160, P161, P162), and returns to the main routine. In the determination of step P158, there is an unrecorded part in the IC card,
If recording is possible, step P160 is omitted.

If it is determined in step P153 that the IC card 41 is not inserted, the signal CSDP is set to "L" and the signal processing CP is set.
The memory data indicating the recording state (the number of recording frames, etc.) of the internal memory 40 is received from U51, the communication is completed by setting the communication end signal CSDP to "H" (steps P165, P166, P167).
Move to P161.

If it is determined in step P151 that the mode has not been switched from OFF to REC, it is determined whether or not the mode switch S3 has been switched from PLAY to REC (step P170). The display is turned off, the signal CSDP is set to "L", and a signal is output to the signal processing unit to notify that the signal has been switched from PLAY to REC. The signal CSDP is set to "H" to terminate the exchange (steps P171, P172, P173, P174), and returns to the main routine.

FIGS. 10 (a) to 10 (f) show the first release button shown as step P105 in the flowchart shown in FIG.
This is a processing routine in the case where the switch S1 that is turned on by pressing down is turned ON. First, it is determined whether or not the recording mode (REC) is set (step P201). When the mode is not the recording mode, the display on the display unit 5 is blinked to indicate that shooting is not possible, and the process returns to the main routine after the switch S1 is turned off (steps P207 and P208).

In the case of the recording mode in the judgment of Step P201, it is judged whether or not the frame number display counter of the recorded image is 0 (Step P20).
2) Since 0 indicates that image recording is no longer possible, a predetermined value K1 is set in the timer 1 to start timekeeping, and the counter display blinks (steps P203, P20).
Four). Wait for the timer 1 to finish counting, switch the counter display to continuous lighting (steps P205, P206), and return to the main routine.

If the counter is not 0 in the determination of Step P202, that is, it indicates that shooting is possible, and the routine goes to Step P210 and the subsequent processes. First, it is determined whether or not the macro photography switch S9 is ON. If it is ON, the macro photography lamp LA is turned on (steps P210 and P211). If it is not macro shooting, step P211 is omitted. The subject luminance measured by the photometric circuit 36 is A / D converted and input (step P212). It is determined whether or not the macro shooting switch S9 is ON (step P213). If it is ON, the process moves to the switch P230. Macro shooting switch S9 is ON
If not, it is determined whether the subject is backlight or low luminance (Steps P214, P215). If neither the backlight nor the low luminance, the process moves to Step P230. In the case of backlight or low brightness, it is determined whether or not the flash photography switch S11 is ON (step P216).
It is determined whether the signal CHC indicating the completion of charging of 63 is “H” (step P217). If “H”, the process proceeds to step P230. If it is not "H", the charging is started by setting the signal CHSTA for instructing the start of charging of the main capacitor to "H", and after completion of the charging, the signal CHSTA is set to "L" to stop the charging (steps P219, P220, P221). ). Check if switch S1 is ON
Moves to Step P230 in the case of, and returns to the main routine if it is not ON.

In Step P230, it is determined whether or not the flash mode is set. In the case of the flash mode, it is determined whether or not the subject is backlit. In the case of the backlight, the shutter speed TVA determined by the subject brightness is set as the shutter speed for flash control TVF. Otherwise, the shutter speed TVH determined by the camera shake limit is used as the shutter speed for flash control. TVF (Steps P231, P232, P23
3). If the flash mode is not determined in step P230, the shutter speed TVA determined by the subject brightness and the shutter speed TVH determined by the camera shake limit are determined, and TVA ≧ TV
In the case of H, TVA is set to the shutter speed TVC for exposure control, and TVA <
In the case of TVH, TVH is set as the shutter speed TVC for exposure control (steps P234, P235, P236).

Switch S2 that is turned on by pressing the release switch in the second step
Is determined whether or not is ON (step P237). If not ON, the switch S1 is checked. If ON, the process returns to step P237, and ON
If not, the macro photography lamp LA is turned off (steps P238, P239), and the process returns to the main routine.

If the switch S2 is ON in the judgment of Step P236, the shutter operation plunger PL is turned ON to start the exposure operation, and first, the release start signal INREL is set to "L" to release the clock to the clock generation circuit 35 and the signal processing unit 31. The start is notified (steps P240, P241, P242). Macro shooting switch S9
It is determined whether or not the signal is ON. If the signal is ON, the signal LBC is set to “L”, and the correction in the signal processing in the signal processing unit 31 is switched to WB and γ correction for photographing with a lamp.
Is set to “H” to switch to WB and γ correction for normal photographing (steps P234, P244, P245). It waits until the exposure start signal EXSTA output from the clock generation circuit 35 becomes “L” (step P246), and determines whether or not the flash mode is set (step P247). When the camera is not in the flash mode, that is, in the case of normal photographing, the timer 2 is set to a value of 2-TVC based on the shutter speed TVC at the time of normal photographing previously obtained, and time ^measurement is started. Exposure is completed when the timer finishes counting (step
P248, P249, P250), and then proceed to step P260.

If the flash mode is determined in step P247, the value 2 ^-TVF is set in the timer 2 based on the previously obtained shutter speed TVF at the time of flash photography, and time counting is started (steps P251 and P252). A value that defines the flash timing of the flash device is set in the timer 3 and time measurement is started (steps P253 and P254). When the time measurement of the timer 2 is finished earlier than the timer 3 (for example, when the brightness suddenly increases during the exposure), the exposure is completed without emitting the flash light, and the routine goes to Step P260. If the timer 3 finishes counting before the timer 2, the flash device is caused to emit light, the dimming control is performed to stop the light emission, and the exposure ends (step P2).
55, P256, P257, P258), and the routine goes to Step P260.

Turn off the shutter operation plunger PL (step P26
0), and waits for the end of the signal processing in the signal processing unit 31 (step P261). It is determined whether or not the macro shooting switch S9 is ON (step P262). If it is ON, the lamp LA is turned OFF (step P264), and the process proceeds to step P269. If it is OFF, it is determined whether or not the flash shooting switch S11 is ON. judge. If the switch S11 is OFF, the process proceeds to Step P269. If the switch S11 is ON, it is determined whether or not the signal CHC indicating the completion of charging of the main capacitor 63 of the flash device 37 is "H" (Step P256).
In the case of, the process proceeds to Step P269. When the signal CHC is not “H”, the signal CHSTA for instructing the start of charging of the main capacitor is set to “H” to start charging, and after completion of charging, the signal CHST
A is set to “L” to stop charging (steps P266, P267, P
268).

Additional data such as date data is recorded in the internal memory 40 and the IC card 41 via the data bus DB2, and the signal INREL is set to "H" to indicate the end of exposure (steps P269 and P270).

It is determined whether or not the protect switch S6 is set to the ON position (step P271). If not, the protect display is turned OFF (step P272), and the process proceeds to step P280.
Move to If it is ON, a predetermined value K1 is set in the timer 1 to start timing (steps P273 to P275). It is determined whether or not the protect / erase operation switch S7 is turned on while the timer 1 is counting (step P275). If the switch is turned on, the video recording frame photographed immediately before is protected, and the protect data is transferred to the data bus DB1. Via internal memory 40, or I
The data is recorded on the C card 41, the protection display is turned on, and the process goes to step 280 after waiting for the protection / erasing operation switch S7 to be turned off (steps P276, P277, P278). If the switch S7 is not ON in the judgment of step P275, the timer 1 is kept waiting, that is, if the protect / erase operation switch S7 is not pressed while the timer 1 is counting, the protection is not performed. After the time measurement of 1 is completed (step P279), the routine goes to step P280.

1 is subtracted from the content of the frame number counter and the content of the counter is 0
Then, it is determined whether or not the IC card 41 is inserted (steps P280, P281, P282). When the counter is not 0, and when the IC card is not inserted, the process shifts to Step P286. When the counter is 0 and an IC card is inserted, no more data can be recorded on the IC card. Therefore, the content of the counter is set to 10 (the image recording capacity of the internal memory 40), and the recording of the IC card is completed. Turn on display
(Steps P283, P284, P285). Address bus AD
The image data corresponding to the frame number of the counter is read from the internal memory via B1, and data indicating whether or not the frame is protected is input (steps P286, P287).
It is determined whether or not the protect data has already been written to the frame (step P288). If so, the process returns to step P280 because no image is recorded on the frame, and the process for the next frame is performed. Move on to

If the result of determination in step P288 is that protect data has not been written, the process waits until switch S1, which is turned on by pressing the release button in the first step, is turned off (step P289), and
If it is FF, it is determined whether the protect switch S6 is ON (step P290). When switch S6 is ON, timer 1
Is set to a predetermined value K1 to start timekeeping. After the protection display blinks for a predetermined time, the protection display is continuously lit to notify the completion of the protection (steps P291 to P294), and the routine goes to step P296. Protect switch S6 is OFF in the judgment of step P290
In the case of, the protect display is turned off, the next photographable frame number is displayed on the counter (steps P295, P296), and the process returns to the main routine.

FIG. 11 is a flowchart showing step P107 of the flowchart shown in FIG.
The function changeover switch S3 indicated as is in the playback mode (PLAY).
9 shows a flowchart of a reproduction mode processing routine in the case of. First, it is determined whether or not the function changeover switch S3 has switched from the REC position to the PLAY position (step P301). If the switch has been made, the PLAY display is turned ON, the signal CSDP is set to "L", and the signal processing unit 31 performs the PLAY operation. Informing that the mode has been switched, the signal CSDP is set to "H" to end the communication (steps P302 to P305). If the switch S3 has not switched from REC to PLAY in the determination of step P301, the mode switch S3 is switched from ERASE to P.
It is determined whether or not the mode has been switched to LAY (step P306). If the mode has been switched, the ERASE display is turned OFF and the process proceeds to step P302.
If not, the process shifts to Step P308.

It is determined whether or not the IC card 41 has been inserted (step P308). When the IC card 41 has been inserted, the card display is turned ON, and it is determined whether or not the IC card has just been inserted in the playback mode. If it has just been inserted, the number of reproducible frames is set to 32 in the counter, and the card mode is set (steps P309 to P312). If it is determined in step P310 that the IC card has been inserted first, processing such as setting the number of reproducible frames (steps P311 and P312) is omitted. If no IC card is inserted in the judgment of step P308, the card display is turned off, and it is determined whether or not the IC card has just been removed in the playback mode. If the IC card has just been removed, the number of reproducible frames is set to 10 in the counter. Then, the internal memory mode is set (steps P313 to P316). If it is determined in step P314 that the IC card has been removed first, processing such as setting the number of reproducible frames (steps P315 and P316) is omitted.

The counter contents are output via the address bus ADB1, the counter contents are displayed, and the IC card 41 or the internal memory
The image data at the corresponding address is read from 40 and output as a video signal (steps P317 to P319). When the access switch S4 (UP) is pressed, the process proceeds to the S4 processing routine described below. When the access switch S5 (DOWN) is pressed, the process proceeds to the S5 processing routine described later. Further, the other mode selection switch is pressed. If it has, the program returns to the main routine and moves to the corresponding subroutine (steps P320 to P322). If none of the access switches S4, S5 and the other mode selection switch has been pressed, the process returns to step P319, and the output of the video signal is continued.

FIGS. 12 (a) to 12 (c) show an erase mode processing routine when the mode switch S3 shown as step P109 in the flowchart shown in FIG. 7 is in the erase mode (ERASE). First, the mode switch S3 is set to ERASE S
It is determined whether or not INGLE has been set (step P331).
In the case of RASE / SINGLE, that is, in the case of erasing a single frame, the flow proceeds to Step P332, and in the case of ERASE / ALL, that is, in the case of erasing all frames, the flow proceeds to Step P371.

In step P332, the mode switch S3 is switched from PLAY to SI
It is determined whether the display has been switched to NGLE or from ALL to SINGLE. In the former case, the PLAY display is turned off, and in the latter case, the "A" display showing all the frames is turned off (step P332).
~ P335). The "S" display indicating a single frame is turned on, the signal CSDP is set to "L", the signal processing CPU 51 is informed of the single frame erasing mode, the signal CSDP is set to "H", and the communication is terminated (step P336). ~ P339).

Then, depending on whether or not the IC card 41 is inserted,
The IC card mode or the internal memory mode is set (steps P340 to P348). The details are shown in the PL shown in FIG.
Since the steps are the same as steps P308 to P316 of the AY processing routine, description thereof will be omitted.

Proceed to step P350 to set the counter contents to address bus AD.
Output via B1, display the contents of the counter, and read the protected data of the image to be reproduced (steps P350-P35
2). It is determined whether or not the image to be reproduced has protected data. If there is no protected data, that is, if the protected data is not output, a video signal is output. If the protected data is recorded, 1 is subtracted from the counter content and the next frame is deleted. The process returns to Step P350 (Steps P353, P354, P355). By the above processing, the reproduction of the image on which the protected data is recorded is prohibited, and the image is not accidentally erased.

It is determined whether or not the protect / erase operation switch S7 has been turned on (step P356). If it is on, the erase data is output to the signal processing CPU 51, and the erase display is turned on after the completion of the erase processing of the recorded image. (Steps P357 to P359). Wait for the protect / erase operation switch S7 to be turned off (step P360), and then proceed to step P361. If the switch S7 is not ON in the determination of Step P356, the process also proceeds to Step P361.

When the access switch S4 (UP) is pressed, it will be described later.
When the access switch S5 (DOWN) is pressed, the process proceeds to the S5 process routine described later. When the other mode selection switch is pressed, the process returns to the main routine and proceeds to the corresponding subroutine ( Step P361
~ P363). If none of the access switches S4 and S5 and the other mode selection switch have been pressed, the process returns to step P350.

If it is determined in step P331 that all frames are to be erased instead of erasing a single frame, the process proceeds to step P371. First, the "S" display indicating a single frame is turned off, and the "A" display indicating all frames is turned on.
To The signal CSDP is set to "L" to notify the signal processing CPU 51 of the all-frame erasing mode, and the signal CSDP is set to "H" to terminate the communication (steps P371 to P375). Protect /
It is determined whether the erase operation switch S7 is ON (step P37).
6) If it is ON, erase data is output to the signal processing CPU 51,
Waiting for the completion of the erasing process, the erasure display blinks. And
After the switch S7 is turned off, the erasure display is turned on (steps P377 to P381). It is determined whether or not the IC card 41 has been inserted. If the IC card 41 has been inserted, the counter content is set to 32. If not, the counter content is set to 10 (steps P382 to P385), and the process returns to the main routine. .

FIGS. 13 (a) to 13 (d) show the sequence of image frames during reproduction of a recorded image by the operation of the access switch S4 (UP) shown in step P111 of the flowchart shown in FIG. 9 is a flowchart illustrating a process of sequentially moving image frames at the time of erasing; First, it is determined whether or not the mode switch S3 is in the playback mode (PLAY) (step P4).
01), when not in the reproduction mode, the erasing mode (S
(ERASE) is determined, and if the mode is the erase mode, the process proceeds to Step P441; otherwise, the process returns to the main routine (Step P402).

In the case of the playback mode in the determination of Step P401, it is determined whether or not the access switch S4 has changed from OFF to ON.
→ The process proceeds to Step P405 each time the status changes to ON (Step P40
3, P404). Add 1 to the contents of the counter (Step P40
5) It is determined whether or not the IC card 41 has been inserted (step P406).
Is determined (step P407). If the content of the counter is 33, it means that the reproduction of all the frames recorded on the IC card 41 has been completed. Therefore, the counter is set to 1, and the internal memory mode is set to reproduce the image recorded in the internal memory 40. Is set (steps P408 and P409). If the content of the counter is not 33 in the determination at Step P407, it is determined whether or not the internal memory mode is set, and if the content is the internal memory mode, it is determined whether or not the content of the counter is 11 (Steps P410, P411). If the content of the counter is 11, it means that the reproduction of all the frames recorded in the internal memory 40 has been completed. Therefore, the counter is set to 1, and the IC card mode for reproducing the image recorded on the IC card 41 is set. This is set (steps P412, P413). If the determinations in steps P410 and P411 are negative, the process proceeds to step P416. If no IC card is inserted in the judgment in step P406, the counter content is
It is determined whether or not it is 11, and if it is 11, the counter is set to 1, and if it is not 11, the process immediately proceeds to Step P416 (Steps P414, P415).

Outputs the contents of the counter via the address bus ADB1,
It accesses the IC card 41 or the internal memory 40 to display the contents of the counter, reads out the image data of the frame at the corresponding address from the IC card 41 or the internal memory 40, and outputs it as a video signal (steps P416 to P418). The protection data of the frame being reproduced is read, and it is determined whether or not the image being reproduced is protected (steps P419 and P42).
0). If the result of the determination is that the protection is protected, the protection display is turned ON, and it is determined whether or not the protection switch S6 is at the release position (REMOVE) for releasing the protection.
If it is at the release position, the release data is output, the protection display is turned off (steps P422 to P424), and step P40
Return to 1. When the switch S4 is not at the release position, the process immediately returns to Step P401.

If it is determined in step P420 that the protection is not protected, it is determined whether the protection switch S6 is in the ON position.
In the case of the position, the timer 1 is set to a predetermined value K2, and time measurement is started (steps P425 to P427). If the switch S6 is not at the ON position in the determination of Step P425, the process returns to Step P401.
While timer 1 is counting, protect / erase switch S6
Is determined (step P428), and if it is ON, the protection data is output to the IC card or the internal memory via the data bus DB2 and written, the protection display is turned ON, and the switch S6 is turned OFF. (Steps P429 to P432), and the process returns to Step P401.

In the above embodiment, the time at which the protect switch S6 is operated is defined by the time K2 set in the timer 1, and is protected only when the switch S6 is operated at this time. For example, when switching to the next image, the protectable time may be defined.

The case of the single frame erasing mode in the determination in step P402 will be described. In this processing, steps P441 to P455 (the thirteenth
The processing of FIG. (C) corresponds to steps P403 to
Since the contents of the process are the same as those of P417 (FIGS. 13A and 13B), the description is omitted here.

In Step P456, the protection data of the image to be reproduced is read. It is determined whether or not the image to be reproduced has protected data.If there is no protected data, that is, if the protected data is not output, a video signal is output.If the protected data is recorded, the process proceeds to step P443 to process the next frame. Transfer (steps P457 to P458). With the above processing, the reproduction of the protected image is prohibited, and the image is not accidentally erased.

It is determined whether the protect / erase operation switch S7 has been turned on (step P459). If it is on, the erase data is output to the signal processing CPU 51, and the erase display is turned on after the completion of the erase processing of the recorded image. (Steps P459 to P462). Then, the flow shifts to Step P401 after waiting for the switch S7 to be turned OFF. If the switch S7 is not ON in the judgment of Step P459, the process also proceeds to Step P401.

FIGS. 14 (a) to 14 (d) show reverse movement of the image frame at the time of recording image reproduction by operation of the access switch S5 (DOWN) shown in step P113 of the flowchart shown in FIG. 9 is a flowchart illustrating processing such as reverse feeding of an image frame when erasing an image. First, it is determined whether or not the function switch S3 is in the playback mode (PLAY) (step P5).
01), when not in the reproduction mode, the erasing mode (S
(ERASE) is determined, and if the mode is the erase mode, the process proceeds to Step P541; otherwise, the process returns to the main routine (Step P502).

In the case of the playback mode in the determination of Step P501, it is determined whether or not the access switch S5 has changed from OFF to ON (Steps P503, P504), and every time the access switch S5 changes from OFF to ON, 1 is subtracted from the content of the counter. (Step P505). It is determined whether or not the IC card 41 has been inserted (step P506). If it has been inserted, it is determined whether or not the content of the counter has become 0 (step P507). IC when the counter content is 0
Since it means that the reproduction of all the frames recorded on the card 41 has been completed, the counter is set to 10 and the internal memory 40 is set.
The internal memory mode is set for the reproduction of the image recorded in (P508, P509). If the content of the counter is not 0 in the determination in Step P507, it is determined whether or not the internal memory mode is set, and in the case of the internal memory mode, it is determined whether or not the content of the counter is 0 (Steps P510 and P511). If the content of the counter is 0, it means that all the frames recorded in the internal memory 40 have been reproduced.
It is set to 32, and the IC card mode is set for reproducing the image recorded on the IC card 41 (steps P512, P513).
If the determinations in steps P510 and P511 are negative, step P51
Move to 6. If the IC card is not inserted in the determination in step P506, it is determined whether the counter content is 0,
If it is 0, the counter is set to 10, and if it is not 0, the process immediately proceeds to Step P516 (Steps P514, P515).

The process of outputting a video signal from an image recording frame, the process of steps P516 to P532 for recording and releasing protect data by operating the protect / erase operation switch S6 are the same as the processes of steps P416 to P432 in the process of the access switch S4. Since they are the same, the description is omitted here.

The processing in the case of the single frame erasing mode in the determination in step P502 will be described. This processing starts from step P541, but the processing of steps P541 to P555 (FIG. 14 (c)) is performed in steps P503 to P517 in the case of the reproduction mode (FIG. 14 (a)).
The processing contents are the same as (b)). Step P5
56 to P563 (the process of FIG. 14 (d) is a process of erasing a single frame, and this process is the process and process shown in steps P456 to P463 (FIG. 13 (d)) in the process of the access switch S4. The contents are the same, and therefore, the description is omitted here.

FIGS. 15 (a) to 15 (c) show the automatic frame feed (AU) during image reproduction, which is selected by the frame feed switch S8 and is shown as step P115 in the flowchart shown in FIG.
6 is a flowchart illustrating the processing of (TO).

When automatic frame advance is selected by operating switch S8,
First, whether the function changeover switch S3 is in the image playback mode (PLAY),
Alternatively, it is determined whether or not an erase mode (S · ERASE) is set for each frame (steps P601 and P602), and only in the case of these two modes, the process proceeds to step P603 and thereafter.

It is determined whether the access switch S4 has changed from OFF to ON, and if not, the same determination is made for the access switch S5 (steps P603, P604). Switch S4
Is changed from OFF to ON, a predetermined value K4 is set in the timer 4 to start time counting, and 1 is added to the counter content (steps P605 to P607).

The internal memory mode or IC card mode is set depending on whether all the frames recorded on the IC card or all the frames recorded on the internal memory have been reproduced, and the image is reproduced and the video signal Are output in the same manner as steps P406 to P418 of the access switch S4. Therefore, the description is omitted here.

It is determined whether or not the access switch S4 or S5 before the time count of the timer 4 has changed from OFF to ON (steps P622 to P624). If the time measurement by the timer 4 ends first, the process returns to step P605, where the time measurement by the timer 4 is started again, and the reproduction of the next image is started. If the switch S4 or S5 is turned on before the timer 4 finishes counting, the timer 4 stops counting and reads the protected data of the reproduced image (steps P625 and P626).

Read the protected data of the playback image, and
The processing of steps P626 to P639 for recording and canceling the protected data by operating the erase operation switch S6 is the same as the processing of steps P419 to P432 in the processing of the access switch S4, and thus the description is omitted here.

Access switch S5 is OFF to O in the judgment of step P604.
If it has changed to N, the process moves to Step P641. First, a predetermined value K4 is set in the timer 4 to start timing, and 1 is subtracted from the counter content (steps P641 to 643).

The internal memory mode or IC card mode is set depending on whether all the frames recorded on the IC card or all the frames recorded on the internal memory have been reproduced, and the image is reproduced and the video signal Are output in the same manner as steps P506 to P518 of the access switch S5. Therefore, the description is omitted here.

Before the timer 4 finishes counting, it is determined whether the access switch S4 or S5 has changed from OFF to ON (steps P658 to P660). If the time measurement by the timer 4 ends first, the process returns to step P641 to start the time measurement by the timer 4 again and shift to the reproduction of the next image. If the switch S4 or S5 is turned on before the end of the time counting by the timer 4, the process proceeds to step P625, where the recording of the protected data and the
Release processing is performed.

FIG. 16 is a flowchart showing Step P117 of the flowchart shown in FIG.
Selected by the frame feed changeover switch S8 shown as
9 is a flowchart illustrating manual frame forwarding (MANUAL) processing during image reproduction. As is clear from the flowchart,
When the switch S8 is set to MANUAL, the processing of S4 described above is executed each time the access switch S4 changes from OFF to ON, and the processing of S5 described above is performed each time the access switch S5 changes from OFF to ON. The processing is executed.

FIG. 17 is a flowchart showing step P119 of the flowchart shown in FIG.
It is a flowchart of the date setting process shown as. First, when the date setting switch S13 is turned ON, a “year” setting mode is set, and a desired year is set by operating the access switches S4 and S5 (step P701). When the mode shift switch S12 is turned on, the mode is switched to the “month” setting mode, and the desired month is set by operating the switches S4 and S5 (steps P702 and P7).
03). Hereinafter, similarly, by operating the mode shift switch S12 and the access switches S4 and S5, "day", "hour",
The “minute” is set (steps P704 to P709). It is determined whether the date setting switch S13 is ON (step P710), and ON
If not, the process returns to Step P701, and the date can be set again. If ON, end the date setting and return to the main routine. The display on the right in FIG. 17 shows an example of the display state of the display unit 13 in each step.

In this embodiment, after the “minute” setting is completed, the switch
Although the state of S13 is determined, the state of the switch S13 may be determined after setting data in each setting mode, and the display may return to the original display when it is ON.

FIGS. 18 (a) and 18 (b) are flowcharts showing a process of transferring an image recorded in the internal memory to the IC card when the IC card is inserted. First, it is determined whether the IC card 41 is inserted into the camera (step P80).
1) If inserted, the signal CSDP is set to “L” and the state of the IC card memory is input from the signal processing CPU 51, and the signal C
SDP is set to “H” to end communication (steps P802 to P80)
Four). It is determined whether the IC card has not been recorded or whether there is a recorded image in the internal memory (Steps P805 and P806). If the IC card has not been recorded and there is a recorded image in the internal memory, the process proceeds to Step P807. If the IC card has been recorded or if there is no recorded image in the internal memory, the process returns to the main routine.

The first frame number of the image recorded in the internal memory is X (10 in this embodiment), and the first frame number recordable on the IC card is Y (32 in this embodiment) (steps P807 and P80).
8). The mode is switched to the internal memory mode, the content of the counter is set to X, the image data is read from the frame of the internal memory corresponding to the content of the counter X, and stored in the buffer memory (steps P809 to 812). Since this processing is controlled by the signal processing CPU 51 in this embodiment, after the processing is completed (step P813), the counter content X is output again, and
The image data of the corresponding frame in the internal memory is deleted (steps P814 to P815). Wait for the erase process to finish (step
P816), set the IC card mode, set the counter content to Y, and set the IC card piece corresponding to the counter content Y to
The image data stored in the buffer memory is recorded (Steps P817 to P820). Wait for the end of the recording process (step
(P821), the internal memory mode is set again, and 1 is subtracted from the frame number X of the internal memory to be processed to prepare for the processing of the next frame (steps P822 to P823). It is determined whether or not the frame number is 0. If it is not 0, it means that there is a frame to be processed. Therefore, a new frame number X is set in the counter, and the image data is read from the frame in the internal memory corresponding to the counter content X. Is read and stored in the buffer memory (steps P824-
P827). After the completion of the processing (step P828), the counter content X is output again, and the image data of the corresponding frame in the internal memory is deleted (steps P829 to P830). After completion of the erasing process (step P831), the IC card mode is set, 1 is subtracted from the counter content Y, and the image data stored in the buffer memory is stored in the IC card frame corresponding to the new counter content Y. After recording and waiting for the end of the process (steps P832 to P837), the process returns to step P822 and proceeds to the process of the next frame.

When X = 0 in the determination of step P824, that is, when the processing of all the image data recorded in the internal memory is completed,
The number of frames recorded in the internal memory is subtracted from the number of frames that can be recorded on the IC card, the fact that recording on the IC card is possible is displayed from this frame number, and the process is terminated (step P8).
40-P841).

In the above embodiment, the image recorded in the internal memory is transferred to an unrecorded IC card, but the image data is partially recorded in an unrecorded area of the IC card. You may. In the above embodiment, the images of all the frames recorded in the internal memory are transferred to the IC card. However, only the images of the protected frames may be transferred.

FIG. 19 shows a display example of the display unit 5. Among the display elements of the display unit 5, 5a is a display element indicating a frame number of an image processed in each mode of recording, protection, reproduction, and erasing, 5b is a display element indicating mounting of an IC card, and 5c is a date setting. It is a display element that indicates the current mode (year, month, day, hour, minute). Reference numeral 5d denotes a display element indicating a protect mode, 5e a reproducing mode, and 5f a display element indicating a single frame erasing mode.

FIGS. 19 (a), (b), and (c) show display examples in the recording mode, and (a) shows that an IC card is mounted and an IC card is set, and that 32 frames of images can be recorded. I have.
In (b), the fact that all the frames of the IC card have been recorded is indicated by the oblique line at the center of the display 5b, indicating that the image of 10 frames can be recorded in the internal memory. (C) shows that the IC card is not mounted, the internal memory mode is set, and image recording of 10 frames is possible.

19 (d), (e) and (f) show display examples in the protect mode, (g), (h) and (i) show display examples in the reproduction mode, and (j) (k) ( 1) shows a single frame erasing mode among the erasing modes, in which "S.ERASE" is displayed. In the case of the all frame erasing mode, "A.ERASE" is displayed.

In the above embodiment, a digital image signal is recorded using an IC card as a recording medium. Alternatively, the present invention can be applied to a case where an analog image signal is recorded using a magnetic disk.

〔The invention's effect〕

As described above, according to the present invention, when shooting,
When there is an image to be stored, a mode for prohibiting image erasure is set by the prohibition mode setting means, and furthermore, a manual operation member is operated to protect the image from being erased in a predetermined image recording area of the recording medium. Since the signal is recorded, the camera operator can be clearly conscious of the setting of the erasure prohibition mode (protect mode), the target image can be protected reliably, and even unnecessary images can be protected. Can be prevented.

Further, when the erasure prohibition mode is not set, the manual operation member can be used as an operation member for erasing a recorded image different from the recording of the protection signal, and the operation panel can be simplified by also using the operation member. Can be summarized.

[Brief description of the drawings]

FIG. 1 is a perspective view showing an appearance of a camera according to the present invention, FIG. 2 is a block diagram of a control circuit of the camera, FIG. 3 is a block diagram showing details of a signal processing unit in the control circuit, and FIG. Is a perspective view showing the appearance of the flash device, FIG. 5 is a circuit diagram of the flash device, FIG. 6 is a perspective view showing the configuration of the imaging unit,
7 to 17 are flow charts for explaining the control operation of the camera, FIG. 7 is a flow chart showing an outline of the entire control, FIG. 8 is a flow chart showing a process when the mode changeover switch is OFF, and FIG. Fig. 10 is a flowchart showing a process in a recording mode, Fig. 10 is a flowchart showing a process of turning on a switch S1 which is operated by pressing a release button one step, Fig. 11 is a flowchart showing a process in a reproduction mode,
FIG. 12 is a flowchart showing processing in the erase mode, and FIG.
The figure is a flowchart showing the processing of the access switch S4,
FIG. 14 is a flowchart showing a process of the access switch S5, FIG. 15 is a flowchart of an automatic frame feed process by the frame feed switch S8, FIG. 16 is a flowchart of a manual frame feed process by the frame feed switch S8, and FIG. FIG. 18 is a flowchart of a date setting process by the setting switch S13, FIG. 18 is a flowchart of a process of transferring an image recorded in an internal memory to an IC card, and FIG. 19 is a diagram showing a display example of a display unit. 1: Camera body, 2: Shooting lens, 4: Release button, 5: Display, 7: Emitter window for macro shooting, 8: IC card slot, 9: Flash device connection, S3: Mode switch, S4 , S5: Access switch, S6: Protect switch, S7: Protect / erase switch, S8: Frame feed switch, S9: Macro shooting switch, S10: Flash shooting switch, 30: C
PU, 31: signal processing unit, 40: internal memory, 41: IC card.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Yoshihiro Tanaka, Inventor Yoshihiro Tanaka 2-3-13 Azuchicho, Chuo-ku, Osaka, Osaka Inside the Osaka International Building Minolta Camera Co., Ltd. Osaka International Building Minolta Camera Co., Ltd. (72) Inventor Katsuyuki Namba 2-3-3 Azuchicho, Chuo-ku, Osaka City, Osaka Prefecture Kaihei 2-125586 (JP, A)

Claims (4)

(57) [Claims] An image signal recording means for recording a photographed image signal in a predetermined image recording area of a recording medium in a still video camera capable of recording and erasing an image signal, and a mode for inhibiting erasure of a recorded image. An erasure prohibition mode setting means for setting, a manual operation member, and when the erasure prohibition mode is set, the image is recorded in a predetermined image recording area on a recording medium in response to an operation of the manual operation member. A control operation for recording a protection signal for prohibiting erasure of an image is performed. When the erasure prohibition mode is not set, a control operation for erasing a recorded image in response to an operation of the manual operation member is performed. Control means for executing a control operation for inhibiting erasure of the image signal in the image recording area when the protect signal is recorded in the predetermined image recording area. Still video camera, characterized in that the. 2. The still video camera according to claim 1, wherein said still video camera has a function of deleting a protection signal. 3. The still video camera according to claim 1, wherein the still video camera further comprises a display means, and the display means displays that the protection signal has been recorded. 4. The apparatus according to claim 3, wherein said display means displays that a protection signal has been recorded and also displays a symbol for identifying an image recording area in which the protection signal has been recorded. Still video camera.