JP3163100U - Integrated circuit element layered structure - Google Patents

Abstract

Provided is a highly reliable device in which the layout of an integrated circuit device is activated, and at the same time, is easily manufactured and has stable characteristics. A plurality of first chip openings 10 are provided on the periphery, and a plurality of first through holes 12 are connected to the first chip holes and the first conduction areas with the first chip holes. A first conductive region in which the first wiring region 13 is provided is formed, and a first die 100 on which a conductive dielectric is installed is deposited in the first through hole, and is deposited on one surface of the first die. A second chip corresponding to the first conductive region, a conductive dielectric is disposed between the first conductive region and the second chip, and a plurality of second through holes The second conductive region 21 provided with each second chip and each second through hole 22 and the second wiring region 23 connecting the second conductive region is formed, and the second through hole is also formed in the second through hole, The second die 200 on which the conductive dielectric is installed and the first and second through holes are formed by high temperature drilling. [Selection] Figure 1

Description

    The present invention relates to an integrated circuit element layered structure, and in particular, conduction is formed by a contact dielectric on a die surface and a conductive dielectric in a notch or through hole, and in particular, the required system is integrated into the first and second dies. Thus, the present invention relates to an element in which the layout of an integrated circuit element is activated, and at the same time, it can be easily manufactured, has stable characteristics, and can provide a highly reliable element.

    When two general conventional integrated circuit elements are combined, as shown in FIG. 8, generally, after two dies 400 and 500 are deposited, an edge of the two dies 400 and 500 is further connected by a conductive wire 60. Crossing and connecting each of the contacts 40 and 50 on the surface of the two dies 400 and 500 by the respective conductive wires 60, the two dies 400 and 500 are combined to be used as an integrated circuit element.

    In the above conventional method, the two dies 400 and 500 can be connected by the conductive wire 60. However, when connecting by the above-described conductive wire 60, it is necessary to cross the edges of the two dies 400 and 500. Dice of the same size must be deposited, it is inconvenient in use, the design of the system using the die is limited, it is difficult to integrate, the manufacturing procedure is complicated, and error detection Is difficult, and the production yield deteriorates.

    Also, in general conventional semiconductor processes, two integrated circuit elements are often coupled using a through-hole. In general, a plurality of through-holes are installed in a related chip to conduct electricity in the through-hole. By embedding material, both surfaces of the chip are electrically connected, and a general conventional method is to form a plurality of through holes in the chip with a tool, and then perform printing or printing on the inner wall surface of each through hole. An insulating layer is formed by coating, ink jet, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, electrolytic plating or electroless plating, and the insulating layer is used to prevent a short circuit of the chip. Inside, a conductive material is embedded to conduct both surfaces of the chip.

    However, in the conventional process, after punching a chip, an insulating layer is installed, and finally a conductive material is embedded, so that the manufacturing process becomes complicated, the yield is low, and the device reliability is not good. The conventional ones are not practical.

    The present inventor proposes the present invention in which the above-mentioned drawbacks are studied carefully, and the above-mentioned disadvantages can be effectively eliminated by utilizing the theory, and the design is rational.

    The main object of the present invention is to solve the above-mentioned conventional problems, and a conduction is formed by using a contact dielectric on the surface of the die and a chip or a through hole. Provided is a highly reliable element that can be integrated into one or the second die, activates the layout of the integrated circuit element, and at the same time is easily fabricated and has stable characteristics.

    In order to achieve the above object, the present invention is provided with a plurality of first notches on the periphery, and a plurality of first through holes, each first notch and each first through hole, and a first A first conductive region is provided in which a first wiring region connecting the conductive region is formed, a first die in which a conductive dielectric is installed in the first through hole, and one surface of the first die. A second chip corresponding to the first conductive region is provided at the periphery, and a conductive dielectric is disposed between the first conductive region and the second chip, and a plurality of second chips are provided on the periphery. A second conductive region provided with two through-holes and a second wiring region connecting each second chip and each second through-hole with the second conductive region is formed in the second through-hole. The second die on which the conductive dielectric is installed and the first and second through holes are formed by high-temperature drilling to form the first and second through holes. That time, respectively, the first and second insulating layer formed on the inner edge by the high temperature, is contained, it is an integrated circuit device layered tissue characterized.

    Hereinafter, the features and technical contents of the present invention will be described in detail with reference to the drawings. However, the drawings and the like are for reference and explanation, and the present invention is not limited thereby.

3D appearance conceptual diagram of the first embodiment of the present invention Three-dimensional decomposition conceptual diagram of the first embodiment of the present invention Cross-sectional state conceptual diagram of the first embodiment of the present invention Three-dimensional decomposition conceptual diagram of the second embodiment of the present invention Cross-sectional state conceptual diagram of the second embodiment of the present invention Three-dimensional decomposition conceptual diagram of the third embodiment of the present invention Cross-sectional state conceptual diagram of the fourth embodiment of the present invention Conventional three-dimensional appearance conceptual diagram

    1 to 3 are a three-dimensional appearance conceptual diagram of the first embodiment of the present invention, a three-dimensional exploded conceptual diagram of the first embodiment of the present invention, and a sectional state conceptual diagram of the first embodiment of the present invention, respectively. As shown in the figure, the present invention is an integrated circuit element layered structure, which is composed of at least a first die 100 and a second die 200, and deposits the first die 100 and the second die 200. The required system is integrated into the first and second dies 100 and 200, so that not only the layout of the integrated circuit element is activated but also easy to fabricate and stable in characteristics, and High reliability can be obtained.

    The first die 100 includes at least a substrate 101, a first line layer 102 deposited on the substrate 101, an insulating layer 103 deposited on the first line layer 102, and a first line deposited on the insulating layer 103. And a plurality of first notches 10 are provided at the periphery of the first die 100, and the first die 100 is provided with a first conductive region 11 and a plurality of first dies. A first wiring region 13 that connects each through hole 12 and each first chip 10 and each first through hole 12 and the first conductive region 11 is provided, and a conductive dielectric 14 is provided in the first through hole 12. Embedded in, for example, conductive silver paste, the first conductive region 11 has a plurality of contacts 111, the first wiring region 13 has a plurality of conductive wires 131, and each conductive wire 131 1st chip 10 and 1st conduction area 11, or each 1st consistency In addition to connecting the hole 12 of the first conductive region 11 may extend to another side of the first die 100.

    The second die 200 is deposited on one surface of the first die 100, and the second die 200 includes at least a substrate 201, a first line layer 202 deposited on the substrate 201, The second line layer 204 is composed of an insulating layer 203 deposited on one line layer 202 and a second line layer 204 deposited on the insulating layer 203. The second die 200 is formed on the periphery of the first conductive region 11. A corresponding second chip 20 is provided, and a conductive dielectric 24 is filled between the first conductive region 11 and the second chip 20, and the conductive dielectric 24 is a conductive silver paste, and The second die 200 is connected to the second conductive region 21, the plurality of second through holes 22, the second chipped holes 20, the second through holes 22 and the second conductive region 21. A second wiring region 23, and the second through hole 2 is also filled with a conductive dielectric 24, the second conductive region 21 has a plurality of contacts 211, the second wiring region 23 has a plurality of conductive wires 231, and each conductive wire In addition to connecting each second notch 20 and the second conductive region 21 or each second through hole 22 and the second conductive region 231, 231 may extend to the other surface of the second die 200.

    The first and second dies 100 and 200 are doped with silicon (Si) or silicon doping, for example, boron, boron, phosphorous, arsenic or antimony. The first and second dies 100 and 200 are made of a high-temperature drilling facility (for example, a laser) in an oxygen atmosphere and penetrated through the first and second dies. When the holes 12 and 22 are formed and the first and second through holes 12 and 22 are formed, the first and second insulating layers 121 and 221 are formed at the inner edges thereof at a high temperature, respectively ( As in FIG. 3). With the above structure, a new integrated circuit element layered structure is formed.

    When depositing, the present invention is provided with a second chip 20 and a second through hole 22 corresponding to the first conductive region 11 on the second die 200 and its peripheral edge. Each conductive wire 231 communicates with each other through each second through hole 22, and a conductive dielectric 24 is filled between the first conductive region 11 and the second chip 20, and into the second through hole 22. As a result, the first and second dies 100 and 200 are electrically connected to the conducting wires 131 and 231 by the second chip 20 and the second through hole 22, whereby the first and second dies are connected. Both surfaces of the dies 100 and 200 are conducted.

    4 and 5 are respectively a three-dimensional exploded conceptual diagram of the second embodiment of the present invention and a sectional state conceptual diagram of the second embodiment of the present invention. As shown in the figure, in the present invention, in addition to the structure of the first embodiment, a third die 300 may be practically deposited on the second die 200. Has a third chip 30 corresponding to the second conductive region 21 at the periphery, and a conductive dielectric 34 is filled between the second conductive region 21 and the third chip 30, and A third cloth connecting the third conductive region 31, the plurality of third through holes 32, the third chip holes 30, the third through holes 32 and the third conductive region 31 to the third die 300. A line region 33 is provided, a third insulating layer 321 is formed on the inner edge of the third through hole 32, and the third through hole 32 is also filled with a conductive dielectric 34, whereby the second through hole 32 is filled with the second through hole 32. A third die 300 is further deposited on the die 200, so that the present invention is more practical. To become.

    FIG. 6 is a three-dimensional decomposition conceptual diagram of the third embodiment of the present invention. As shown in the figure, in addition to the structural forms of the first and second embodiments, the present invention is practically directly connected to the second conductive region 21 and the first die on one surface of the second die 200. 100 corresponding to the first conduction region 11 in 100, so that the contacts 111, 211 in the first and second conduction regions 11, 21 can be in contact with each other, as well as in the first The die 100 and the second die 200 are deposited and used, and the required system can be integrated into the first and second dies 100 and 200. In this embodiment, the second die 100 and the second die 200 are integrated. The die 200 can be selectively provided with the second chip opening, the second through hole, the conductive dielectric, and the second wiring region according to practical use.

    FIG. 7 is a conceptual cross-sectional view of a fourth embodiment of the present invention. As shown in the figure, in the present invention, in addition to the structural forms of the first, second and third embodiments, dies having the same scale may be deposited. In practice, the present invention may be assembled in the structural form of the first or third embodiment, and the deposition of the first die 100 and the second die 200 is performed by the method of the third embodiment. The first and second conductive regions 11 and 21 can be deposited and integrated by bringing the contacts 111 and 211 into contact with each other, and the deposition of the second die 200 and the third die 300 is The third chip 300 and the peripheral edge thereof are provided with a third chip 30 and a third through hole 32 corresponding to the second conductive region 21, and each third chip is formed by the method of the first embodiment. The lead wire 331 communicates with the conductor 331 via the opening 30 and each third through hole 32, and is electrically connected between the second conduction region 21 and the third chip hole 30 and into the third through hole 32. The second and third dies are filled by filling the dielectric 34. 00 and 300 are electrically connected to the conducting wires 231 and 331 via the third chip 30 and the third through hole 32, whereby both sides of the second and third dies 200 and 300 are electrically connected. The purpose of depositing and integrating is realized.

    As described above, the present invention is an integrated circuit element layered structure, and can effectively eliminate the conventional drawbacks, and the required system can be obtained by depositing the first die and the second die. And integrated into the second die, not only the integrated circuit element layout is activated, but also easy to fabricate, stable characteristics and improved element reliability. Therefore, the present invention is more progressive and more practical, and filed a utility model registration request in accordance with the law.

    The above is only a better embodiment of the present invention, and the present invention is not limited thereby, and equivalent changes made based on the scope of claims for patent registration relating to the present invention and the contents of the description. All modifications and changes are included in the scope of the claim for registration of the present invention.

(Invention)
DESCRIPTION OF SYMBOLS 10 1st chip opening 100 1st dice | dies 101, 201 Board | substrates 102, 202 1st line layer 103, 203 Insulation layer 104, 204 2nd line layer 11 1st conduction area 111 Contact 12 1st through-hole 121 1st insulation layer 13 First wire region 131 Conductor 14 Conductive dielectric 20 Second chip 200 Second die 21 Second conductive region 211 Contact 22 Second through hole 221 Second insulating layer 23 Second wire region 231 Conductor 24 Conductive dielectric Body 30 Third chip 300 Third die 31 Third conductive region 32 Third through-hole 321 Third insulating layer 33 Third wiring region 34 Conductive dielectric (conventional)
40, 50 Contact 400, 500 Dice 60 Conductor

Claims (3)

A plurality of first chip holes are provided on the periphery, and a plurality of first through holes and a first wiring region that connects each first chip hole or each first through hole and the first conductive region are provided on the periphery. A first conductive region is provided, and a first die in which a conductive dielectric is installed in the first through hole;
Deposited on one surface of the first die, a second chip corresponding to the first conductive region is provided at the periphery, and a conductive dielectric is disposed between the first conductive region and the second chip. And a second conductive region provided with a plurality of second through holes and a second wiring region that connects each second chip and each second through hole and the second conductive region. A second die in which a conductive dielectric is also installed in the second through hole;
When the first and second through-holes are formed by high-temperature drilling and the first and second through-holes are formed, the first and second insulating layers formed on the inner edge thereof at a high temperature, respectively, An integrated circuit element layered structure comprising: The first and second dies include at least a substrate, a first line layer deposited on the substrate, an insulating layer deposited on the first line layer, and a second line layer deposited on the insulating layer. The integrated circuit element layered structure according to claim 1, wherein the layered structure is configured. In the second die, a third die is deposited, and a third chip opening corresponding to the second conduction region is provided at a peripheral edge of the third die, and the second conduction region and the third chip are provided. In between, a conductive dielectric is provided, and a plurality of third through holes and a third wiring region for connecting the third chip holes and the third through holes and the third conductive region are provided thereon. The integrated circuit element layered structure according to claim 1, wherein a third conductive region is formed, and a conductive dielectric is also disposed in the third through hole.