JP3163023B2 - Electronics - Google Patents
ElectronicsInfo
- Publication number
- JP3163023B2 JP3163023B2 JP34558896A JP34558896A JP3163023B2 JP 3163023 B2 JP3163023 B2 JP 3163023B2 JP 34558896 A JP34558896 A JP 34558896A JP 34558896 A JP34558896 A JP 34558896A JP 3163023 B2 JP3163023 B2 JP 3163023B2
- Authority
- JP
- Japan
- Prior art keywords
- suspend
- supply
- circuit
- cpu
- reset
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
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- Power Sources (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明はサスペンド−レジュ
ーム機能を備えた電子機器に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic device having a suspend / resume function.
【０００２】[0002]
【従来の技術】現在、パソコン、ワープロ等の電子機器
では、携帯性を重視した所謂ノート型と称される小型の
ものが数多く出現している。2. Description of the Related Art At present, many electronic devices such as personal computers and word processors, which are so-called notebook type, which emphasize portability, have appeared.
【０００３】この種装置では携帯使用を可能とするため
に駆動源としてニッケル水素、リチウムイオンというよ
うな二次電池が使用されている。このため、長時間の使
用を可能とするために回路の消費電力を極力抑えるよう
設計すると共に、サスペンド−レジューム機能を付加し
無駄な電力消費を抑えるようにしている。In this type of device, a secondary battery such as nickel-metal hydride or lithium ion is used as a driving source in order to make it portable. For this reason, the power consumption of the circuit is designed to be minimized in order to enable long-time use, and a suspend-resume function is added to suppress unnecessary power consumption.
【０００４】このサスペンド−レジューム機能とは、予
めサスペンドモードに設定されている時に一定時間の間
キー操作がない場合やＣＰＵのアクセスが存在しない場
合等のように電子機器自体が実質的に待機状態となって
いる際、又は、電源スイッチが操作された際に機器のそ
の時点の状態をバックアップメモリに待避すると共にＣ
ＰＵ及び他のＬＳＩ、ＩＣの主要動作を停止し、スイッ
チやキー等の操作の有無を監視するサスペンド状態に入
り、その後スイッチやキー等の操作に応答して上記メモ
リに待避した状態を復旧し動作を再開する（レジュー
ム）ものである（例えば、特開平５−２８２０６３号公
報（Ｇ０６Ｆ１／００）参照）。[0004] The suspend-resume function means that the electronic device itself is substantially in a standby state, such as when there is no key operation for a certain period of time or when there is no CPU access when the suspend mode is previously set. Or when the power switch is operated, the current state of the device is saved in the backup memory and C
The main operation of the PU and other LSIs and ICs is stopped, and a suspend state for monitoring the operation of switches and keys is entered. Then, the state saved in the memory is restored in response to the operation of switches and keys. The operation is resumed (resume) (see, for example, Japanese Patent Application Laid-Open No. 5-280633 (G06F1 / 00)).
【０００５】[0005]
【発明が解決しようとする課題】ところで、上記サスペ
ンド−レジューム機能を有する電子機器がサスペンド状
態にある場合、機器の電源をオフしようとすると、一度
レジュームを実行し、サスペンドモードを解除した後に
電源スイッチをオフする必要があった。このため、単に
電源をオフするだけの操作のために貴重な電力を消費す
るという問題があった。When the electronic device having the suspend-resume function is in the suspend state, when the power of the device is turned off, the resume is executed once, the suspend mode is released, and then the power switch is turned off. Had to be turned off. For this reason, there is a problem in that valuable power is consumed for the operation of simply turning off the power.
【０００６】[0006]
【課題を解決するための手段】本発明は、この課題に鑑
みてなされたもので、その特徴は、サスペンド状態にあ
る時、リセット指示に応答して、駆動電圧の供給を停止
することにある。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problem, and has a feature in that the supply of the driving voltage is stopped in response to a reset instruction in a suspended state. .
【０００７】[0007]
【発明の実施の形態】図１は本発明は実施例であり、Ｃ
ＰＵ１はリセット信号入力ポート２及びサスペンド信号
出力ポート３を有すると共にインターフェースＩ／Ｆ４
を介してキーボード５に接続されている。FIG. 1 shows an embodiment of the present invention.
PU1 has a reset signal input port 2 and a suspend signal output port 3, and has an interface I / F4.
Is connected to the keyboard 5 via the.
【０００８】上記入力ポート２は、常開接点からなるリ
セットスイッチ６を介して所定電圧供給手段ＶＢＢに接
続されると共に抵抗Ｒ及びＣを介してアースに接続され
ている。更には、上記入力ポート２は反転回路７の入力
端子が接続されている。上記リセットスイッチ６が開の
状態では、上記入力ポート２及び反転回路７の入力端子
はアース状態となり、実質的にローレベル信号が入力さ
れることとなる。この結果、ＣＰＵ１はリセット指示が
存在しないと判定し、また反転回路７はハイレベル信号
を出力することとなる。The input port 2 is connected to a predetermined voltage supply means VBB via a reset switch 6 comprising a normally open contact, and is also connected to ground via resistors R and C. Further, the input port 2 is connected to the input terminal of the inverting circuit 7. When the reset switch 6 is open, the input port 2 and the input terminal of the inverting circuit 7 are grounded, and a low-level signal is substantially input. As a result, the CPU 1 determines that there is no reset instruction, and the inversion circuit 7 outputs a high-level signal.
【０００９】上記出力ポート３からはサスペンド信号が
出力される。具体的には、ＣＰＵ１がサスペンド状態に
ない時、出力ポート３からはハイレベル信号が出力さ
れ、サスペンド状態の時、出力ポート３からはローレベ
ル信号が出力される。The output port 3 outputs a suspend signal. Specifically, when the CPU 1 is not in the suspend state, a high-level signal is output from the output port 3, and when the CPU 1 is in the suspend state, a low-level signal is output from the output port 3.
【００１０】上記出力ポート３は、機器内のＬＳＩ・Ｉ
Ｃ８に接続されているため、上記ローレベルのサスペン
ド状態を示す信号が出力ポート３より出力されると上記
ＬＳＩ・ＩＣ８はサスペンド状態となり、逆にハイレベ
ル信号が出力されるとサスペンド状態を解除する。The output port 3 is connected to an LSI / I
Since it is connected to C8, the LSI / IC 8 enters the suspend state when the signal indicating the low-level suspend state is output from the output port 3, and cancels the suspend state when the high-level signal is output. .
【００１１】また、上記出力ポート３は、反転回路７の
出力端子と共に２入力し出力型の論理和回路９に接続さ
れる。この回路９の出力は電源回路１０に出力される。The output port 3 has two inputs together with the output terminal of the inverting circuit 7 and is connected to an output-type OR circuit 9. The output of the circuit 9 is output to the power supply circuit 10.
【００１２】この電源回路１０は上記論理和回路９の出
力に応答してＣＰＵ１、ＬＳＩ・ＩＣ８及びＶＢＢへの
駆動電圧供給を制御する。具体的には、論理和回路９の
出力がローレベルとなった時のみサスペンドモードでは
ない通常モードの際に電源オフ指示があった場合と同様
に駆動電圧の供給を停止する。The power supply circuit 10 controls the supply of drive voltage to the CPU 1, the LSI / IC 8 and the VBB in response to the output of the OR circuit 9. Specifically, the supply of the drive voltage is stopped only when the output of the OR circuit 9 becomes low level in the normal mode, which is not the suspend mode, as in the case where the power off instruction is given.
【００１３】次に本実施例の動作について説明する。Next, the operation of this embodiment will be described.
【００１４】今、ＣＰＵ１が動作中であるとすると出力
ポート３からはハイレベル信号が出力されるのでＬＳＩ
・ＩＣ８はサスペンド状態とならず、また電源回路１０
にもハイレベル信号が供給されるため電源回路１０は駆
動電圧を供給し続ける。また、このときリセットスイッ
チ６が押下されると論理和回路９の一方の入力には反転
回路７よりローレベル信号が供給されるが、上記出力ポ
ート３から他方の入力にハイレベル信号が供給されてい
るため電源回路１０は駆動電圧の供給を継続する。尚、
上記リセットスイッチ６の押下に従ってＣＰＵ１の入力
ポート２にはハイレベル信号が入力されるため、ＣＰＵ
１はリセット動作を開始する。If the CPU 1 is operating, a high-level signal is output from the output port 3, so that the LSI
The IC 8 does not enter the suspend state and the power supply circuit 10
Since the high-level signal is also supplied, the power supply circuit 10 continues to supply the drive voltage. When the reset switch 6 is depressed at this time, a low-level signal is supplied to one input of the OR circuit 9 from the inversion circuit 7, but a high-level signal is supplied to the other input from the output port 3. Therefore, the power supply circuit 10 continues to supply the drive voltage. still,
When the reset switch 6 is pressed, a high-level signal is input to the input port 2 of the CPU 1.
1 starts a reset operation.
【００１５】一方、ＣＰＵ１がサスペンド状態にある時
には、ＣＰＵ１の出力ポート３よりローレベル信号が出
力されるが、リセットスイッチ６が押下されない限り反
転回路７の出力はハイに保持されるので、電源回路１０
には論理和回路９よりハイレベル信号が供給され、電源
回路１０は駆動電圧を供給し続けることとなる。またこ
のとき、リセットスイッチ６が押下されると、反転回路
７の出力はローレベルとなり、この結果論理和回路９の
出力はローレベルとなるので電源回路１０は駆動電圧の
供給を停止する。従って、電子機器はオフ状態となる。On the other hand, when the CPU 1 is in the suspended state, a low-level signal is output from the output port 3 of the CPU 1, but the output of the inverting circuit 7 is held high unless the reset switch 6 is pressed down. 10
Is supplied with a high-level signal from the OR circuit 9, and the power supply circuit 10 continues to supply the drive voltage. At this time, when the reset switch 6 is pressed, the output of the inverting circuit 7 goes low, and as a result, the output of the OR circuit 9 goes low, so that the power supply circuit 10 stops supplying the drive voltage. Therefore, the electronic device is turned off.
【００１６】[0016]
【発明の効果】本発明によれば、サスペンド状態にある
機器をレジュームすることなく電源オフ状態とすること
ができるので、不必要な電力消費を抑制できる。According to the present invention, since a device in a suspended state can be turned off without resuming power, unnecessary power consumption can be suppressed.
【図１】本発明の実施例を示す回路図である。FIG. 1 is a circuit diagram showing an embodiment of the present invention.
１ ＣＰＵ ２ 入力ポート ３ 出力ポート ６ リセットスイッチ ７ 反転回路 ９ 論理和回路 １０ 電源回路 DESCRIPTION OF SYMBOLS 1 CPU 2 Input port 3 Output port 6 Reset switch 7 Inversion circuit 9 OR circuit 10 Power supply circuit
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) G06F 1/26 G06F 1/32 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) G06F 1/26 G06F 1/32
Claims (3)
源スイッチをサスペンド／レジューム指示に兼用可能な
電子機器であって、サスペンド状態にある時、リセット
指示に応答して駆動電圧の供給を停止することを特徴と
する電子機器。A power supply for instructing ON / OFF of a drive voltage supply.
Power switch can be used for suspend / resume instruction
An electronic device, wherein when in a suspend state, supply of a driving voltage is stopped in response to a reset instruction.
源スイッチをサスペンド／レジューム指示に兼用可能な
電子機器であって、サスペンド状態に入ることを指示す
る信号を出力する主制御手段と、リセットを指示する手
段と、上記主制御手段からの指示信号と上記リセット手
段の指示との両信号の存在を条件として上記主制御手段
への駆動電圧の供給を停止する電源回路手段とを有する
ことを特徴とする電子機器。2. An electric power supply for instructing on / off of a drive voltage supply.
Power switch can be used for suspend / resume instruction
The electronic device, wherein main control means for outputting a signal for instructing to enter a suspend state, means for instructing reset, and presence of both an instruction signal from the main control means and an instruction from the reset means Power supply circuit means for stopping supply of the drive voltage to the main control means on condition that:
源スイッチをサスペンド／レジューム指示に兼用可能な
電子機器であって、ＣＰＵと、反転回路と、上記ＣＰＵ
のリセット信号入力ポート及び上記反転回路の入力端子
に接続されたリセットスイッチと、上記反転回路の出力
端子と上記ＣＰＵのサスペンド信号出力ポートとが入力
端子に接続される論理和ゲートと、該ゲートの出力がロ
ーレベルとなると上記ＣＰＵへの駆動電圧の供給を停止
する電源回路とを備えたことを特徴とする電子機器。3. An electric power supply for instructing on / off of supply of a driving voltage.
Power switch can be used for suspend / resume instruction
An electronic device, comprising: a CPU; an inversion circuit; and the CPU
A reset switch connected to the reset signal input port and the input terminal of the inverting circuit; an OR gate in which the output terminal of the inverting circuit and the suspend signal output port of the CPU are connected to the input terminal; An electronic device comprising: a power supply circuit for stopping supply of a drive voltage to the CPU when an output becomes low level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34558896A JP3163023B2 (en) | 1996-12-25 | 1996-12-25 | Electronics |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34558896A JP3163023B2 (en) | 1996-12-25 | 1996-12-25 | Electronics |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10187289A JPH10187289A (en) | 1998-07-14 |
| JP3163023B2 true JP3163023B2 (en) | 2001-05-08 |
Family
ID=18377616
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP34558896A Expired - Fee Related JP3163023B2 (en) | 1996-12-25 | 1996-12-25 | Electronics |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3163023B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007007668A1 (en) | 2005-07-08 | 2007-01-18 | Toray Industries, Inc. | Therapeutic agent and treatment method for ameliorating uremia |
-
1996
- 1996-12-25 JP JP34558896A patent/JP3163023B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007007668A1 (en) | 2005-07-08 | 2007-01-18 | Toray Industries, Inc. | Therapeutic agent and treatment method for ameliorating uremia |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH10187289A (en) | 1998-07-14 |
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