JP3162928B2 - PLL circuit and wireless device using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit used for frequency switching and a radio apparatus using the PLL circuit, and more particularly to control of a loop filter.

[0002]

2. Description of the Related Art In recent years, digital mobile radio communication using a time division multiple access (TDMA) system for connecting a base station and a mobile terminal has been put to practical use. In such a system, a mobile terminal communicates with a base station using a time slot assigned to itself from a frame constituted by a plurality of time slots. Then, with the movement of the mobile station terminal, communication is performed by switching the base station in communication. When switching between base stations, each mobile device terminal receives a time slot other than the time slot assigned to the mobile station,
It is necessary to switch from the radio frequency during communication to the radio frequency of the peripheral base station, measure the received electric field strength, and return to the radio frequency in use. For this reason, a PLL circuit is generally used for a radio circuit of a mobile terminal, and for example, as described in Japanese Patent Application Laid-Open No. 4-142815 (H03L7 / 187), a frequency can be switched at high speed. A PLL circuit having a configuration is used.

FIG. 4 is a block diagram showing the configuration of such a PLL. In the figure, reference numeral 201 denotes a voltage controlled oscillator, which outputs a signal output from a PLL circuit to a frequency divider 202.
Is compared with the output signal of the reference signal generator 203 by the phase comparator 204 to detect a phase difference. This signal is converted into a voltage level by the charge pump 205 and its output is sent to the loop filter unit. The signal smoothed by the loop filter is applied to the voltage controlled oscillator 2
01, and a frequency corresponding to the input voltage level is output from the PLL circuit.

Here, when an operation for switching the output frequency of the PLL circuit occurs, the loop filter section first receives a control signal from the control circuit 209 and sets the first loop filter 207 having a small time constant by the switch 206. Is done. After a predetermined fixed time elapses after the frequency is quickly pulled in by the first loop filter 207, a control signal for switching the filter is sent from the control circuit 209 to the switch 206, Switching to the second loop filter 208 having a larger time constant than that of the first loop filter is performed, and the frequency quickly pulled in by the first loop filter 207 is maintained in a stable state.

[0005]

In the conventional method, PL
When switching the output frequency of the L circuit, the time constant of the loop filter is changed by a specific timing initially set regardless of the frequency difference before and after the switching, and the switching timing is the frequency when the frequency difference before and after the switching is the maximum. Was determined based on the pull-in time. For this reason, even when the switching frequency difference is small, the time constant of the loop filter is changed at the same timing as when the switching frequency difference is maximum, so that extra time is required to obtain a stable frequency.

[0006]

According to a first aspect of the present invention, there is provided a PLL circuit, comprising: a phase comparator for converting a signal of a reference signal generator and a signal divided by a frequency divider into a signal; A phase difference signal is detected, the phase difference signal is converted into a voltage level by a charge pump circuit, and an output of the charge pump circuit is switched by a switch, so that the first loop filter or the first loop filter having a small time constant is obtained. Switching frequency calculation for calculating a difference in switching frequency when switching an output frequency in a PLL circuit that outputs a signal of a desired frequency by inputting to a voltage controlled oscillator via a second loop filter having a larger time constant. Circuit and
A memory for storing a loop filter switching time for a difference in switching frequency; and a control circuit for controlling switching of the switch, wherein the control circuit includes a loop corresponding to the switching frequency difference calculated by the switching frequency calculation circuit. A filter switching time is read from the memory, and switching of the switch is controlled based on the loop filter switching time.

According to a second aspect of the present invention, there is provided a radio apparatus comprising:
In a wireless device that converts the output signal of the L circuit and the modulation signal output from the modulation circuit into an IF signal by mixing with a mixer, and then transmits the IF signal from an antenna via an RF circuit, the PLL circuit includes: A phase comparator detects a phase difference signal from a signal of the reference signal generator and a signal divided by the frequency divider, converts the phase difference signal into a voltage level by a charge pump circuit, and switches an output of the charge pump circuit. And a signal having a desired frequency is output by inputting to the voltage controlled oscillator via the first loop filter having a smaller time constant or the second loop filter having a larger time constant than the first loop filter. A switching frequency calculating circuit for calculating a switching frequency difference when the output frequency is switched; And a control circuit for controlling switching of the switch, wherein the control circuit stores a loop filter switching time corresponding to a switching frequency difference calculated by the switching frequency calculation circuit in the memory. And controlling the switching of the switch based on the loop filter switching time.

According to a third aspect of the present invention, in the wireless device according to the second aspect, a demodulation circuit for demodulating a signal from a base station received by a radio unit, and the demodulation circuit performs demodulation and transmission. And a data processing circuit for performing predetermined signal processing based on the obtained signal, wherein the data processing circuit sends a switching frequency to the switching frequency calculation circuit when a frequency switching instruction is received from a base station. ,
A frequency switching request signal of the PLL circuit is transmitted to the control circuit.

[0009]

According to the present invention, the switching time from the first loop filter having a smaller time constant to the second loop filter having a larger time constant than the first loop filter is changed for each frequency difference before and after the switching of the PLL circuit. The optimal data is stored in the memory. Then, when the frequency switching occurs, the loop filter switching time corresponding to the switching frequency difference is read from the memory, and the control unit generates a loop filter switching control signal based on this data,
The control signal is sent to the changeover switch of the loop filter section.

[0010]

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, a phase comparator 104 compares the phase of a signal obtained by dividing the output of a voltage controlled oscillator 101 by a frequency divider 102 with the output signal of a reference signal generator 103, and detects a phase difference. The detected signal is supplied to the charge pump circuit 1
The signal is converted into a voltage level by 05 and sent to the loop filter section. The loop filter section switches between the first loop filter 107 having a smaller time constant, the second loop filter 108 having a larger time constant than the first loop filter 107, and the two loop filters based on an instruction from the control circuit 109. It comprises a switch 106. Further, a memory 110 for storing optimal data of a switching time from the first loop filter 107 to the second loop filter 108 for each frequency difference between the frequency before switching of the output of the PLL circuit and the frequency after switching. It has. A signal smoothed by the loop filter unit is input to the voltage controlled oscillator 101, and a frequency corresponding to the input voltage is obtained as an output of the PLL circuit. This PLL output is output from mixer 1
At 12, the signal is mixed with the modulation signal output from the modulation circuit 111 and converted into an IF signal. Thereafter, the signal is transmitted from the antenna via an RF circuit (not shown).

Here, an operation of switching from a state in which the PLL circuit is locked to a certain frequency to another frequency will be described. A signal from a base station received by a wireless unit (not shown) is demodulated by a demodulation circuit 113 and sent to a data processing circuit 114. Data processing circuit 114
Performs predetermined signal processing based on the demodulated signal. At this time, if there is a frequency switching instruction from the base station, the switching frequency is sent to the switching frequency calculation circuit 115 and
An LE signal (load enable signal), which is a frequency switching request signal of the PLL circuit, is sent to the control circuit 109. Then, the switching frequency calculation circuit 115 calculates a frequency difference between the first frequency before switching and the second frequency after switching, and sends the difference to the control circuit 109. Control circuit 109
Accesses the memory 110 based on the frequency difference and stores the corresponding loop filter switching time data in the memory 110.
, And generates a loop filter switching control signal as shown in FIG. As a result, the first loop filter 107 is set in synchronization with the rise of the loop filter switching control signal, and at the time of the high level, the first loop filter performs frequency pull-in at high speed. Further, the switch 106 is controlled in synchronization with the falling of the signal, and the second
Is switched to the loop filter 108 to stabilize the frequency.

As shown in FIG. 3, the optimum switching time of the loop filter for each switching frequency difference is stored in advance in the memory as data. When the switching frequency difference is small, a short pulse signal is used to switch the loop filter. When provided as a control signal and the switching frequency difference is large, a long pulse signal is provided as a loop filter switching control signal, and stabilization is performed in a minimum time.

[0013]

According to the present invention, for each frequency difference to be switched, the first loop filter for high-speed pull-in having a small time constant and the second loop for stable operation having a larger time constant than the first loop filter are provided. When the optimum switching timing to the filter is supplied and the frequency difference before and after the switching is small, the high-speed pull-in time by the first loop filter is shortened, and the switching to the second loop filter is performed in a short time to achieve a stable state. be able to. High-speed and stable PLL optimized for each switching frequency difference
Circuits are possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a diagram showing the timing of a loop filter switching control signal.

FIG. 3 is a diagram illustrating an example of data in a memory.

FIG. 4 is a block diagram showing a conventional technique.

DESCRIPTION OF SYMBOLS 101 Voltage controlled oscillator 102 Divider 103 Reference signal generator 104 Phase comparator 105 Charge pump circuit 106 Loop filter changeover switch 107 First loop filter 108 Second loop filter 109 Control circuit 110 Memory 111 Modulation circuit 112 Mixer 113 Demodulation circuit 114 Data processing circuit 115 Switching frequency calculation circuit

Claims (3)

(57) [Claims] 1. A charge pump circuit for detecting a phase difference signal from a signal of a reference signal generator and a signal divided by a frequency divider, and converting the phase difference signal into a voltage level by a charge pump circuit. By switching the output of the circuit by a switch and inputting it to the voltage-controlled oscillator via the first loop filter having a smaller time constant or the second loop filter having a larger time constant than the first loop filter, In a PLL circuit that outputs a frequency signal, a switching frequency calculation circuit that calculates a difference between switching frequencies when an output frequency is switched, a memory that stores a loop filter switching time for the switching frequency difference, and controls switching of the switch. A switching circuit corresponding to the difference between the switching frequencies calculated by the switching frequency calculation circuit. A PLL circuit read-out time from the memory, and switching of the switch is controlled based on the loop filter change-over time. 2. A radio apparatus for converting an output signal of a PLL circuit and a modulation signal output from a modulation circuit into an IF signal by mixing with a mixer, and then transmitting the IF signal from an antenna via an RF circuit. The PLL circuit detects a phase difference signal by a phase comparator from a signal of a reference signal generator and a signal divided by a frequency divider, and converts the phase difference signal into a voltage level by a charge pump circuit. By switching the output of the circuit by a switch and inputting it to the voltage-controlled oscillator via the first loop filter having a smaller time constant or the second loop filter having a larger time constant than the first loop filter, A switching frequency calculation circuit that outputs a frequency signal and calculates a difference between switching frequencies when the output frequency is switched; A memory for storing a loop filter switching time for a difference in wave number; and a control circuit for controlling switching of the switch, wherein the control circuit comprises a loop filter corresponding to a switching frequency difference calculated by the switching frequency calculation circuit. A switching device that reads switching time from the memory and controls switching of the switch based on the loop filter switching time. 3. A radio apparatus according to claim 2, wherein the demodulation circuit demodulates a signal from the base station received by the radio unit, and performs a predetermined signal processing based on the signal demodulated and transmitted by the demodulation circuit. A data processing circuit for performing, when receiving a frequency switching instruction from the base station, the data processing circuit sends a switching frequency to the switching frequency calculation circuit and a frequency switching request signal of the PLL circuit. Transmitting to the control circuit.