JP3159154B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a polysilicon plug formed in an interlayer insulating film is increased in resistance to increase the degree of integration.

[0002]

2. Description of the Related Art Hitherto, a high resistance element included in a semiconductor device has been realized by providing a diffusion layer, a polysilicon layer, and the like on a semiconductor substrate by laying a wiring of a resistor for a long time. For example, when a resistance circuit is formed using a polysilicon wiring, as shown in FIG. 19, the polysilicon wiring 303 is drawn long to form a resistance circuit. FIG. 20 shows A in FIG.
It is -A 'sectional drawing.

In this method of manufacturing a resistance circuit, an interlayer insulating film 302 is formed on a semiconductor substrate 301, and polysilicon is deposited on the interlayer insulating film 302 to a thickness of 50 nm to 250 nm. Next, a photoresist (not shown) is patterned to form a polysilicon wiring 303. In this case, since it is necessary to form a high-resistance polysilicon wiring layer, there is a problem that the number of wiring layers increases.

Further, when the resistance of the diffusion layer of the conventional semiconductor device is used, there is a problem that the resistance value of the diffusion layer cannot be increased, which is not suitable for high integration. Note that Japanese Patent Laid-Open Publication No.
Japanese Patent Publication No. 22562 is known.

[0005]

SUMMARY OF THE INVENTION It is an object of the present invention to improve the above-mentioned drawbacks of the prior art, and in particular, to manufacture a novel semiconductor device capable of high integration by increasing the resistance value of a plug. It provides a method.

[0006]

SUMMARY OF THE INVENTION The present invention basically employs the following technical configuration to achieve the above object. That is, the first aspect of the method for manufacturing a semiconductor device according to the present invention is that the phosphorus contained in the polysilicon plug connecting the diffusion layer forming the resistor formed on the semiconductor substrate and the wiring layer is formed by heat treatment. To increase the resistance value of the polysilicon plug, and a second aspect is characterized in that a plurality of the polysilicon plugs are connected in series, In a third aspect, a plurality of the wiring layers are provided, each of the wiring layers is connected by the polysilicon plug, and phosphorus contained in the polysilicon plug is diffused into the wiring layer. In a fourth aspect, a diffusion layer region forming a resistor formed on a semiconductor substrate, an interlayer insulating film formed on the diffusion layer region, a wiring layer formed on the interlayer insulating film, layer A method for manufacturing a semiconductor device comprising: a polysilicon plug doped with phosphorus for connecting a resistor and a wiring layer formed in an insulating film, wherein the phosphorus contained in the plug is diffused into the wiring layer. The fifth aspect is characterized in that the resistance value of the plug is increased, and a fifth aspect is that a resistor formed on a semiconductor substrate, an interlayer insulating film formed on the resistor, and A method of manufacturing a semiconductor device comprising: a wiring layer to be formed; and a phosphorus-doped polysilicon plug formed in the interlayer insulating film and connecting the resistor and the wiring layer. and characterized in that to increase the resistance of the plug by diffusing to the wiring layer, and the sixth aspect, the wiring layer, characterized in that the tungsten silicon Sai de is there

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor device according to the present invention is directed to a semiconductor device having a plug provided in a contact hole formed on a semiconductor substrate and a wiring layer made of a metal silicide connected to the plug. In the above, P is diffused from the phosphorus-doped silicon contained in the plug buried in the contact hole to the wiring layer to increase the resistance of the plug in the contact hole and increase the resistance value of the resistor including the resistance circuit. As a result, higher products can be achieved compared to the conventional method.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A specific example of a method for manufacturing a semiconductor device according to the present invention will be described below in detail with reference to the drawings. FIG.
6 to 6 are cross-sectional views showing manufacturing steps of a specific example of a method for manufacturing a semiconductor device according to the present invention.
The phosphorus contained in the polysilicon plug 109 connecting the diffusion layer 104 forming the resistor and the wiring layer 110 formed on the semiconductor substrate 101 is heat-treated to remove the phosphorus contained in the wiring layer 110.
A method of manufacturing a semiconductor device in which the resistance value of the polysilicon plug 109 is increased by diffusing the polysilicon plug 109 is shown.

Hereinafter, the present invention will be described in more detail. First, as shown in FIG. 1, an element isolation film 103 is formed on a main surface of a semiconductor substrate 101 on which a p-type well 102 is formed by using a LOCOS method or the like. Next, the gate oxide film 10
5 is formed, and a gate electrode 1 is formed on the gate oxide film 105.
06 is formed. After that, impurities are implanted into the element region,
An n-type impurity is implanted into a desired region to form an n-type diffusion region 104.
(Source / drain regions). Examples of the n-type impurity include phosphorus (P) and arsenic (As). After forming the n-type diffusion region 104, as shown in FIG. 2, an interlayer insulating film 107 is deposited to a thickness of 500 to 800 nm, and a contact hole 108 is formed on the n-type diffusion region 104. Interlayer insulation film is BPSG film, PSG film, US
An oxide film and a nitride film such as a G film or a multilayer film thereof may be used. The opening of the contact is dry-etched using a photoresist (not shown) as a mask. Examples of the dry etching include a plasma etching method and a reactive ion etching (RIE) method. After the opening of the contact hole 108, as shown in FIG. 3, phosphorus-doped silicon is embedded in the contact hole 108, and the polysilicon plug 109 is etched back.
To form The polysilicon plug 109 may be formed by implanting non-doped silicon and then implanting phosphorus. Thereafter, as shown in FIG. 4, a wiring layer 110 is formed on the interlayer insulating film 107. As a wiring material, a metal silicide such as tungsten silicide is deposited to a thickness of 50 nm to 200 nm by a sputtering method or a CVD method, and then patterned as shown in FIG. Next, FIG.
As shown in FIG.
To form Using the photoresist 111 as a mask, phosphorus is added to the wiring layer 110 from 2 × 10 ¹⁵ cm ⁻² to 2 × 10 ^16.
Implant about ² cm ^-2 . As shown in FIG. 6, after the photoresist 111 is removed, 750 ° C. to 85 ° C. in a nitrogen atmosphere.
Heat treatment is performed at a temperature of 0 ° C.

By this heat treatment, the resistance of the polysilicon plug 109 under the wiring layer 111 into which phosphorus has not been implanted increases the contact resistance because the doped (implanted) phosphorus diffuses into the wiring layer 110. On the other hand, the source
Since sufficient phosphorus ions are implanted into the wiring layer 110a on the drain region, the resistance of the plug 109a is kept low without diffusion of phosphorus from the plug 109a.

By manufacturing in this manner, a plug having a large resistance value can be formed, so that a resistance circuit having a large resistance value can be formed. FIG. 18 shows a graph A showing the resistance value of the plug when phosphorus is injected into the wiring layer 110, and a graph B showing a high resistance value of the plug when phosphorus is not injected into the wiring layer 110.

Next, another embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIGS. In this specific example, a p-type well 202 and an element isolation film 203 are formed on a semiconductor substrate 201 in the same manner as in the above-described example, and then a gate oxide film 204 is formed.
Is formed to a thickness of 3 nm to 10 nm, a gate electrode 205G, and a resistance wiring 205. Next, as shown in FIG.
05 is covered with a photoresist 206, an n-type impurity such as P (phosphorus) is implanted to form a diffusion layer region 207, and an impurity is also implanted into a gate electrode not covered with the photoresist 206. Next, as shown in FIG. 9, an interlayer insulating film 208 is deposited to a thickness of 500 nm to 1000 nm, and thereafter, a contact hole 209 is opened. After opening the contact hole 209, the phosphorous-doped polysilicon is
The polysilicon plug 210 is formed by depositing a thickness of about 600 nm to about 600 nm and performing etch back. In this case, as in the above-described example, P (phosphorus) may be ion-implanted after burying non-doped silicon to form a polysilicon plug. Next, as shown in FIG. 11, a wiring layer 211 of tungsten silicide is
A 200 nm film is deposited and patterned using a photoresist (not shown) as a mask as shown in FIG. For the deposition of WSi, a sputtering method and a CVD method are used as in the above-described specific example. Then, as shown in FIG.
2 covers the resistor circuit area, and P is added to the FET wiring layer 211a.
(Phosphorus) is implanted at about 2 × 10 ¹⁵ to 2 × 10 ¹⁶ cm ⁻² . Further, as shown in FIG. 13, after forming an interlayer insulating film 212, a contact hole 213 is opened on the wiring layer 211. Thereafter, as shown in FIG.
14 is formed. Then, tungsten silicide is deposited again on the interlayer insulating film 212, and a wiring layer 215 is formed as shown in FIG. 15 using a photoresist (not shown) as a mask. Subsequently, as shown in FIG. 16, the resistance circuit region is covered with the photoresist 216, and P (phosphorus) is ion-implanted into the wiring region 215a. Then, after removing the photoresist 216, a heat treatment is performed at a temperature of 750 ° C. to 850 ° C. in a nitrogen atmosphere. This allows the polysilicon plug 210,
P in 214 diffuses into tungsten silicide of wiring layers 211 and 215, respectively, and the contact resistance of plugs 210 and 214 increases.

[0013]

According to the present invention, phosphorus in the polysilicon plug connecting the diffusion layer and the wiring layer is diffused into the wiring layer by heat treatment to increase the contact resistance, and a large number of the contact resistances are connected in series. Since a resistance circuit is formed,
An increase in the element area of the resistance circuit can be suppressed, and the number of wiring layers can be reduced because it is not necessary to form a wiring layer having a large resistance value.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of a semiconductor device of a first specific example according to the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 1;

FIG. 3 is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 2;

FIG. 4 is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 3;

FIG. 5 is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 4;

FIG. 6 is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 5;

FIG. 7 is a cross-sectional view illustrating a manufacturing process of the semiconductor device of the second specific example according to the present invention.

FIG. 8 is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 7;

FIG. 9 is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 8;

FIG. 10 is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 9;

FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 10;

FIG. 12 is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 11;

FIG. 13 is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 12;

FIG. 14 is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 13;

FIG. 15 is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 14;

16 is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 15;

FIG. 17 is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 16;

FIG. 18 is a graph showing resistance values of plugs.

FIG. 19 is a diagram showing a conventional technique.

FIG. 20 is a sectional view of FIG. 19;

[Explanation of symbols]

101, 201 Semiconductor substrate 104 N-type diffusion region 107, 208 Interlayer insulating film 108, 209, 213 Contact hole 109, 109a, 210, 214 Polysilicon plug 110, 211, 211a, 215, 215a Wiring layer 205 Resistance wiring

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ identification code FI H01L 27/04 (58) Investigated field (Int.Cl. ⁷ , DB name) H01L 21/28 H01L 21/3205 H01L 21/768 H01L 21/822 H01L 27/04

Claims (6)

(57) [Claims] 1. A method according to claim 1, wherein phosphorus contained in a polysilicon plug connecting a diffusion layer forming a resistor formed on a semiconductor substrate and a wiring layer is diffused into the wiring layer by heat treatment to reduce the resistance value of the polysilicon plug. A method for manufacturing a semiconductor device, characterized by increasing the number of semiconductor devices. 2. The method according to claim 1, wherein a plurality of the polysilicon plugs are connected in series. 3. The wiring according to claim 1, wherein a plurality of wiring layers are provided, each wiring layer is connected by the polysilicon plug, and phosphorus contained in the polysilicon plug is diffused into the wiring layer. A method for manufacturing a semiconductor device. 4. A diffusion layer region forming a resistor formed on a semiconductor substrate, an interlayer insulating film formed on the diffusion layer region, a wiring layer formed on the interlayer insulating film, A method for manufacturing a semiconductor device comprising: a polysilicon plug formed in a film and doped with phosphorus for connecting the resistor and a wiring layer, wherein the phosphorus contained in the plug is diffused into the wiring layer to form the plug. A method of manufacturing a semiconductor device, comprising: increasing a resistance value of a semiconductor device. 5. A resistor formed on a semiconductor substrate, an interlayer insulating film formed on the resistor, a wiring layer formed on the interlayer insulating film, and a resistor formed in the interlayer insulating film. A method of manufacturing a semiconductor device comprising a phosphorus-doped polysilicon plug for connecting a body and a wiring layer, wherein the resistance of the plug is increased by diffusing phosphorus contained in the plug into the wiring layer. A method for manufacturing a semiconductor device, comprising: Wherein said wiring layer is tungsten silicon Sai de
The method for manufacturing a semiconductor device according to claim 1, wherein: