JP3157726B2 - Automatic placement and routing of semiconductor integrated circuits - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for automatically arranging and wiring a semiconductor integrated circuit (LSI), and more particularly to an automatic arranging and wiring method for an LSI having a large scale or a large number of macro cells.

[0002]

2. Description of the Related Art Conventionally, this kind of automatic placement and routing method is called LS
In the mask design of I, it was used to automate the manual design by CAD and shorten the development period.

For example, referring to FIG. 6A showing a flow chart of a conventional automatic placement and routing, net information S61 of an LSI and block data S62 used for the LSI are subjected to an automatic placement and routing process S63 by an automatic placement and routing program. , And outputs LSI mask information.

Referring to FIG. 6B showing an example of a flow chart of the automatic placement and routing processing, net information is read in a first step S631. Next, in a second step S632, block data is read. Next, in a third step S633, blocks are arranged. Finally, in a fourth step S634, wiring between blocks is performed. Referring to FIG. 7, which is a flowchart showing the wiring processing of the fourth step in more detail, in the first step S71, the automatic placement and routing apparatus recognizes the coordinates of each node of the net information. The coordinates of the terminal of each block to be wired are determined from the result of the arrangement.

Next, in a second step S72, since the automatic placement and routing apparatus searches for the shortest path between nodes, the path with the shortest wiring is determined from the coordinates of the terminals of each block already determined in the first step S71. Figure out.

Next, in a third step S73, the automatic placement and routing apparatus searches the wiring prohibited area of the already arranged block for the wiring which has been determined in the second step S72 in order to search whether the wiring is overlapped with the wiring prohibited area. It is compared whether or not the routes overlap, and if they do not overlap, the process proceeds to the fifth step S75,
If they overlap, the process proceeds to the fourth step S74.

Next, in the fourth step S74, when the wiring route and the wiring prohibition information overlap in the third step S73, the dynamic placement and routing apparatus changes the wiring route so as to bypass the wiring prohibition area. Reset.

Finally, in a fifth step S75, the second step S75
The wiring process is performed according to the route set in the 72nd to 4th steps S74. The above-described first to fifth steps S71 to S71
S75 is repeatedly executed by the automatic placement and routing apparatus for the number of pieces of net information.

The L arranged and wired in the manner described above
Referring to FIG. 8 showing an outline of an SI mask layout pattern, when performing automatic wiring of an LSI including macro cells 1002 and 1003 and function block cells 1004 to 1007, macro cells 1002 covering the macro cells 1002 and 1003, The wiring prohibition information having the wiring prohibition areas 1008 and 1009 of the wiring of the hierarchy higher than 1003 is prepared.

Thus, the macro cells 1002, 100
When the automatic wiring is performed by the wiring of the hierarchy higher than the third wiring, the wirings 1014 and 1015 bypassing the macro cells 1002 and 1003
Is formed. At this time, the wires 1014 and 1015 are passing over the functional block cells 1004 and 1005 because
Wiring prohibited area 1 of functional block cells 1004 and 1005
This is because 010 and 1011 do not have the wiring prohibition information of the hierarchy higher than the macro cells 1002 and 1003.

FIG. 9 is a plan view showing an example of a data structure of net information in a conventional automatic placement and routing apparatus. This figure shows that there are only 83 nets of data, each having a net name 81 and a terminal list 82 of blocks constituting the net.

FIG. 10A is a block diagram showing an example of a data structure of block data in a conventional automatic placement and routing apparatus. The figure shows a list of data including a set of a block name 91, a block type 92, a block shape 93, and wiring inhibition information 94.

FIG. 10B shows the wiring prohibition information 94.
FIG. 3 is a diagram showing an example of a data structure in the data. Referring to FIG. 12, the name 91B of the wiring layer to be prohibited and the shape data 92B
Is a set of data.

[0014]

The above-mentioned conventional LSI
The first problem with the automatic placement and routing method is that it prevents high integration of LSI.

The reason for this is that it is necessary to secure a wiring area in order for each wiring to bypass the wiring prohibited area covering the macro cell, which hinders high integration.

The second problem is that in the conventional automatic wiring device or wiring method, it was not possible to determine whether each signal line affected the macro cell.

The reason is that the importance of the function of discriminating a signal line that does not affect the operation of the macrocell and arranging the signal line that does not affect the operation of the macrocell on the upper layer of the macrocell has not been recognized.

[0018]

According to the present invention, there is provided a method for automatically arranging and wiring an LSI, comprising the steps of: obtaining a coordinate value of a terminal of each block and a node name from arrangement information of the functional block of the LSI in which a plurality of functional blocks are arranged and wired; Reading the same, extracting the same node name from the plurality of read node names, and calculating the shortest path based on the design rule from the coordinate values corresponding to the node names. Detecting the overlap between the shortest path and the wiring prohibited area, and calculating the detour path based on the design rule when the shortest path and the wiring prohibited area are overlapped. In the automatic placement and routing method, wherein the calculation is repeatedly performed until all of the plurality of node names are processed, the attribute given in advance to the routing prohibited area and the node name Comprising the step of comparison with the given attribute because, and calculates a detour path by the comparison result.

Also, instead of the step of comparing the attribute previously given to the wiring prohibited area with the attribute previously given to the node name, an attribute permitting passage is provided as the attribute previously given to the wiring prohibited area. And comparing the attribute with the attribute given to the node name. If the two attributes do not match, the step of calculating the bypass route can be executed.

Further, instead of comparing the attribute previously given to the wiring prohibited area with the attribute previously given to the node name, an attribute which does not permit passage is given as the attribute previously given to the wiring prohibited area. The method may further include a step of comparing the attribute with an attribute given to the node name, and when both of the attributes match, a step of calculating the detour route.

Furthermore, the method further comprises the step of determining whether or not the wiring prohibited area is a specific block when detecting the overlap of the wiring prohibited area and the node name. For example, a step of comparing an attribute previously given to the wiring prohibited area with an attribute previously given to the node name can be executed.

Further, the attribute can be represented by at least the first character of the node name.

Further, m pieces (m ≧ m) included in the net information
If the voltage level of the signal line of (0) becomes a constant level after a certain period of time, an attribute indicating whether or not the voltage level is constant is given to each of the m signal lines, and the net information is added to the net information. Can also be described.

Further, when at least one signal line included in the net information is not synchronized with the operation of the macro cell, an attribute indicating whether or not the operation is synchronized with the operation of the macro cell is added to the at least one signal line. It can also be described in the net information.

Further, k lines (k ≧ 0) included in the net information
When the signal lines are macro cell test signals, the net information can be described by adding an attribute indicating whether or not the k signal lines are macro cell test signals to the k signal lines.

Further, the j lines (j ≧ j) included in the net information
0) operating frequency of the signal line change in voltage level macrocell
When the signal is gentle with respect to the wave number, a change in the voltage level of the j signal lines is a function of the operating frequency of the macrocell.
Can be written in the net information by applying an attribute indicating whether or not the gradual signal Te.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the present invention, an attribute is added to net information and wiring prohibition information, and the automatic placement and routing apparatus recognizes and compares the attributes. For this reason, a specific wiring can pass through the hierarchy higher than the macro cell, and the number of wirings bypassing the periphery of the macro cell is reduced.

First, a first embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, in the first step S11, since the automatic placement and routing apparatus recognizes the coordinates of each node of the net information, the terminal of each block to be wired is determined from the net information and the arrangement result of each block. Find the coordinates of.

Next, in the second step S12, the automatic placement and routing apparatus searches for the shortest path between the nodes, so that the path with the shortest wiring is determined from the coordinates of the terminals of each block determined in the first step.

Next, in a third step S13, the automatic placement and routing apparatus searches the wiring prohibited area of the already placed block with the second wiring prohibited area in order to search whether the wiring overlaps the wiring prohibited area.
It is calculated whether or not the wiring paths determined in step S12 do not overlap. If they do not overlap, the process proceeds to a sixth step described later, and if they overlap, the process proceeds to a fourth step S14.

In the fourth step S14, the automatic placement and routing apparatus compares the attribute of the net with the attribute of the routing prohibited area, and if it determines that they match, proceeds to the sixth step S16. If it determines that they do not match, it proceeds to the fifth step. move on.

In the fifth step S15, the automatic placement and routing apparatus performs wiring so as to bypass the routing prohibited area for the route of the wiring for which the attribute of the net is determined to be inconsistent with the attribute of the routing prohibited area in the fourth step S15. Set the route again.

Finally, in the sixth step, the automatic placement and routing apparatus uses the route of the wiring determined in the second step S12 or the fifth path.
The wiring is performed according to the wiring path reset in step S15.

The above first to sixth steps are repeatedly executed by the automatic placement and routing apparatus for the number of net information included in the net information to perform wiring.

Next, referring to FIG. 2 showing a flowchart of the second embodiment of the present invention, the difference from the method of the first embodiment described above is that the overlapping of the wiring prohibited area and the wiring is performed. When an overlap is detected between the step of detecting and the step of comparing the attribute of the wiring prohibited area with the attribute of the net, it is determined whether or not a macro cell is overlapped when an overlap is detected. The other components are the same, and the first to third steps are the same, so the fourth step will be described.

In the fourth step S24, the automatic placement and routing apparatus determines whether or not the block corresponding to the wiring prohibited area overlapping with the wiring path determined in the second step S22 is a macro cell. The type 42 is referred to from the block data table, and if it is determined that the cell is not a macro cell, the process proceeds to a seventh step described later. If it is determined that the cell is a macro cell, the process proceeds to a fifth step S25.

Next, in the fifth step S25, when the automatic placement and routing apparatus determines in the fourth step S24 that the block corresponding to the wiring prohibited area overlapping the wiring path is a macro cell, It is determined whether or not there is an attribute (hereinafter, referred to as a pass attribute) that allows the user to pass through the wiring prohibited area.

If there is a passage attribute, the seventh step S27
If there is no pass attribute, the process proceeds to the sixth step S26.

Next, in a sixth step S26, the automatic placement and routing apparatus bypasses the routing prohibited area of the macro cell with respect to the route of the wiring determined to have no passage attribute in the net information in the fifth step S25. Reset the wiring route.

Finally, in the seventh step S27, the automatic placement and routing apparatus carries out wiring in accordance with the path of the wiring determined in the second step S22 or the path of the wiring reset in the sixth step S26.

The above first to seventh steps are repeated by the automatic placement and routing apparatus by the number of pieces of net information included in the net information.

L wired by the above-described automatic placement and routing method
Referring to FIG. 5 showing the outline of the plan view of the SI,
When performing automatic wiring of the entire LSI including the macro cells 302 and 303 of 301 and the function block cells 304 to 307, the wiring prohibition areas 308 of the wiring of the upper layer of the macro cells 302 and 303 which cover the macro cells 302 and 303, 309 is prepared.

The macro cell 30 is determined by the wiring prohibition information.
When the automatic wiring is performed with the wiring of the upper layer of the macro cell 303, the wiring 314 has the same attribute as that of the wiring prohibited area 309 of the wiring of the upper layer of the macro cell 303 and the attribute of the wiring 314. It passes through the wiring prohibited area 309 of the wiring in the hierarchy.

The line 315 bypasses the wiring prohibition region 309 of the upper layer wiring of the macro cell 303 because the attribute of the wiring prohibition region 309 of the wiring of the upper layer of the macro cell 303 and the attribute of the wiring 315 do not match. . At this time, the wirings 314 and 315 are connected to the functional block cells 304 and 30.
5 are passing through the function block cells 304, 3
05 is the macro cell 30
This is because it does not have the wiring prohibition information of the hierarchy higher than 2,303.

Referring to FIG. 4 showing an example of the data structure of the net information in the automatic placement and routing apparatus according to the embodiment of the present invention, a net name 41, a terminal list 42 of blocks constituting the net, a wiring The number of nets, which is a set of the new attribute 43 that allows passage through the prohibited area, is 4
This indicates that there are only four.

Referring to FIG. 5A showing an example of the data structure of block data in the automatic placement and routing apparatus according to the embodiment of the present invention, a block name 51, a block type 52, and a block shape 53 are shown. , Wiring prohibition information 54
Is a series of data. In particular, referring to FIG. 4B showing the data structure in the wiring prohibition information 54, the name 51B of the wiring layer to be prohibited and the shape data 52
B, which is composed of a series of data in which a new attribute 53B that permits passage through the wiring prohibited area is set.

Here, a signal line which can be set to an attribute permitting the macro cell to pass through the wiring prohibited area is shown as follows: a signal whose voltage level becomes constant after a certain period of time; a signal which is not synchronized with the operation of the macro cell; And the change in the voltage level is gentle with respect to the operating frequency of the macrocell.

[0049]

As described above, the LSI placement and routing method of the present invention adds attributes to net information and routing prohibition information, and the automatic placement and routing apparatus recognizes and compares them. For this reason, a specific wiring can pass through the upper layer of the macro cell, and the number of wirings bypassing the periphery of the macro cell is reduced. Therefore, the wiring area can be reduced by reducing the number of bypass wirings, thereby reducing the LSI area. Chip size from 8.18mm to 7.69mm or 7.19mm
And 11 to 22% reduction.

As a result, a slight increase in the amount of design data due to the addition of the attribute, or a slight restriction on the block naming method can be made.

The reason is that the signal wiring which does not affect the characteristics of the macro cell can pass over the macro cell.

[Brief description of the drawings]

FIG. 1 is a flowchart of automatic placement and routing according to a first embodiment of the present invention.

FIG. 2 is a flowchart of automatic placement and routing according to a second embodiment of the present invention.

FIG. 3 is a schematic plan view of an LSI to which an embodiment of the present invention is applied;

FIG. 4 is a data structure diagram of net information in the automatic placement and routing apparatus.

FIG. 5A is a structural diagram of block data in an automatic placement and routing apparatus. FIG. 6B is a data structure diagram of the wiring prohibition information in FIG.

FIG. 6 (a) is a flowchart until the conventional LSI mask layout information is generated. 7B is a flowchart of the automatic placement and routing in FIG.

FIG. 7 is a flowchart of conventional automatic wiring.

FIG. 8 is a schematic plan view of a conventional LSI.

FIG. 9 is a data structure diagram of net information in a conventional automatic placement and routing apparatus.

FIG. 10A is a structural diagram of block data in a conventional automatic placement and routing apparatus. FIG. 11B is a data structure diagram of the wiring prohibition information in FIG.

[Explanation of symbols]

 41, 91 Net name 42, 92 Terminal list of blocks constituting net 43 New attribute 54, 93 Number of nets 51, 101 Block name 52, 102 Block type 52, 102 Block type 53, 103 Block shape 54, 104 Wiring prohibition information 51B, 101B Name of wiring layer to be prohibited 52B, 102B Shape data 53B New attribute 301, 801 LSI 302, 802 Macro cell 303, 803 Macro cell 304, 804 Functional block to allow passage through wiring prohibited area Cell 305, 805 Function block cell 306, 806 Function block cell 307, 807 Function block cell 308, 808 Wiring prohibited area 309, 809 Wiring prohibited area 310, 810 Wiring prohibited area 311, 811 Wiring prohibited area 312, 812 Line prohibited area 313,813 wiring prohibited area 314,814 wiring 315,815 wiring

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/82 G06F 17/50

Claims (9)

(57) [Claims] A step of reading a coordinate value of a terminal of each block and a node name from arrangement information of the functional blocks of a semiconductor integrated circuit in which a plurality of functional blocks are arranged and wired; Extracting the same node name from the names, calculating the shortest path based on the design rule from the coordinate values corresponding to the node name, and detecting the overlap between the shortest path obtained by this calculation and the wiring prohibited area And calculating a bypass route based on the design rule when the shortest route and the wiring prohibited area overlap, and iteratively repeats until all of the plurality of read node names are processed. In the automatic placement and routing method for performing the calculation, the method further includes a step of comparing an attribute previously given to the routing prohibited area with an attribute given to the node name in advance, An automatic placement and routing method for a semiconductor integrated circuit, wherein a detour path is calculated based on the comparison result. 2. The method according to claim 1, further comprising: replacing the attribute previously given to the wiring prohibited area with the attribute previously given to the node name; 2. The method according to claim 1, further comprising the step of: giving the attribute and comparing the attribute with the attribute given to the node name, and when both of the attributes do not match, executing the step of calculating the bypass route. An automatic placement and routing method for semiconductor integrated circuits. 3. An attribute which does not permit passage is given as an attribute previously given to the wiring prohibited area instead of a step of comparing an attribute previously given to the wiring prohibited area with an attribute given beforehand to the node name. 2. The semiconductor integrated circuit according to claim 1, further comprising a step of comparing the attribute with an attribute given to the node name, and when both of the attributes match, executing the step of calculating the detour path. Place and route method. 4. When detecting an overlap between the wiring prohibited area and the node name, the method further comprises the step of determining whether the wiring prohibited area is a specific block or not. 2. The method according to claim 1, further comprising the step of comparing an attribute previously assigned to the wiring prohibited area with an attribute previously assigned to the node name. 5. The method according to claim 1, wherein the attribute is represented by at least one character of the node name. 6. When the voltage level of m (m ≧ 0) signal lines included in the net information becomes constant after a certain period of time, the voltage level of each of the m signal lines is constant. 2. The method according to claim 1, further comprising the step of adding an attribute indicating whether or not the information is present in the net information. 7. When at least one signal line included in the net information is not synchronized with the operation of the macro cell, the at least one signal line is provided with an attribute indicating whether or not the operation is synchronized with the operation of the macro cell. 2. The method according to claim 1, wherein the information is described in net information. 8. When k (k ≧ 0) signal lines included in the net information are macro cell test signals,
2. The method according to claim 1, wherein an attribute indicating whether or not the signal line is a test signal for a macro cell is added to the signal line and the signal line is described in the net information. 9. The j signal lines (j.gtoreq.0) included in the net information indicate that the change in the voltage level is not related to the operating frequency of the macro cell.
In the case where the signal is a gentle signal, an attribute indicating whether or not the change in the voltage level is a gentle signal with respect to the operating frequency of the macro cell is given to the j signal lines and described in the net information. Item 2. The automatic placement and routing method for a semiconductor integrated circuit according to Item 1.