JP3152761B2 - Circuit pattern defect inspection method and defect inspection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a defect inspection method and a defect inspection of a circuit pattern for detecting a defect such as a disconnection or a short circuit of a circuit pattern having periodicity such as a substrate for a memory circuit or a substrate for a liquid crystal display. Related to the device.

[0002]

2. Description of the Related Art As a conventional defect inspection method for a circuit pattern of this kind, there is, for example, a method called a pattern matching method. The principle of the pattern matching method is to detect a defect in a circuit pattern to be inspected by comparing a circuit pattern to be inspected with a reference circuit pattern and extracting the difference. The details will be described below by taking a defect inspection of a circuit pattern formed on a plurality of dies on a semiconductor wafer as an example.

[0003] First, a reference circuit pattern (hereinafter, referred to as a reference pattern) is determined, and reference data is created by converting the determined reference pattern into quantitative data so as to facilitate data processing. As the reference pattern, for example, a circuit pattern of one non-defective die, an average of circuit patterns of a plurality of non-defective dies, a circuit pattern of a die adjacent to a die to be inspected, or the like is used. Since the reference pattern is used as a comparison target of the circuit pattern to be inspected as described above, the appropriateness of the selection directly affects the inspection result. Therefore, it is necessary to determine an optimal reference pattern according to the inspection object. The reference data is created from the determined reference pattern as follows. That is, the reference pattern is placed on a predetermined XY stage and photographed by a camera, and the photographed area (XY plane) is divided into predetermined pixels ((X _i , Y _j ), i and j are, for example, i = 0-5
11, a two-dimensional array of 512 × 512 where j = 0 to 511), and the brightness of each divided pixel is 25
The data is converted into brightness data (digital data) expressed in six gradations (0 to 255) to create reference data.

Next, the circuit pattern to be inspected is converted into quantitative data (brightness data) by the same method as the reference data, and data to be processed is created. At this time, the circuit pattern to be inspected is placed on the XY stage, and the position of the circuit pattern is aligned with the camera. However, it is impossible to completely match the positional relationship between the reference pattern and the camera when the reference data is created. Difficult due to the accuracy of the device. That is, the position of the reference pattern corresponding to each pixel of the reference data does not correspond to the position of the circuit pattern to be inspected corresponding to each pixel of the data to be processed. Therefore, before comparing the brightness data of each pixel, it is necessary to detect the pixel of the reference data corresponding to the origin pixel (X ₀ , Y ₀ ) of the data to be processed. This detection is performed by examining the correlation between the two. For example, the origin (X
₀ , Y ₀ ), the pixel (X ₁ , Y ₁ ) of the reference data is associated with (X _i , Y _j ) of the data to be processed and (X _ii , Y _jj ) (however, ii = i + 1, JJ = j + 1) is checked by calculating the degree of correlation with each other.

[0005] Detection of a defect in the circuit pattern to be inspected is performed by comparing the brightness data of each pixel corresponding to each other after the registration of the reference data created as described above and the data to be processed. It is. That is, if the brightness data of each pixel corresponding to the reference data and the data to be processed is different, the data to be processed is not a reference pattern, and it can be determined that there is some defect near the pixel. . If you know where the defect is,
Detailed defect detection can be performed, for example, by a static inspection using a microscope.

[0006]

However, the prior art having such a structure has the following problems. That is, in the conventional pattern matching method, when creating the reference data and the data to be processed, it is difficult to match the respective origins due to the accuracy of the apparatus. I do it. As described above, since the correlation is checked for all the pixels as described above, it takes a long time to perform the alignment, and there is a problem that it is difficult to reduce the processing time of the defect inspection.

The present invention has been made in view of such circumstances, and provides a circuit pattern defect inspection method and a defect inspection apparatus capable of shortening the processing time and detecting a circuit pattern defect with high accuracy. The purpose is to do.

[0008]

The present invention has the following configuration in order to achieve the above object. In other words, the invention according to claim 1 is a circuit pattern defect inspection method for detecting a defect in a predetermined inspection area of a circuit pattern having periodicity in at least the X direction on an XY plane, A first processing step of inputting the characteristics of the circuit pattern in the inspection area by a plurality of arranged pixels, quantitatively converting the characteristics of each pixel of the input circuit pattern, and creating data to be processed; A second processing step of dividing the data to be processed created in the first processing step into a processing area constituted by an arrangement of pixels in the X direction with respect to at least one pixel in the Y direction; A third processing step of calculating a cycle of the data to be processed for each of the divided processing areas, and calculating the calculated cycle by the number of pixels, For each processing region, the data to be processed created in the first processing step and the data to be shifted by a predetermined integer multiple of the number of pixels corresponding to the cycle calculated in the third processing step A fourth processing step of calculating the difference data, and for each of the processing areas,
Data to be processed created by the first processing step,
Difference data from data obtained by shifting the data to be processed by Z pixels (Z is an integer) in each direction is ± 1 to ± N
(N is a natural number of a predetermined value) in each of the fifth processing steps, and for each of the processing regions, the difference data with respect to the cycle calculated in the fourth processing step is calculated in the fifth processing step. A sixth processing step of calculating the correlation amount to each difference data for ± 1 to ± N, respectively, for ± 1 to ± N, and for each of the processing regions, ± 1 calculated by the fifth processing step. The respective correction data obtained by multiplying each of the difference data about ± N by the respective correlation amounts for ± 1 to ± N calculated in the sixth processing step is a difference with respect to the cycle calculated in the fourth processing step. A seventh processing step of subtracting and removing each from the data, based on the result of the seventh processing step,
An eighth processing step of detecting a defect in the circuit pattern.

According to a second aspect of the present invention, there is provided the circuit pattern defect inspection method according to the first aspect.
In the fifth processing step, each of the calculated difference data for ± 1 to ± N is further orthonormalized.

According to a third aspect of the present invention, there is provided the circuit pattern defect inspection method according to the first aspect.
In the seventh process, the correction data having the maximum absolute value is obtained from the calculated correction data, and only the correction data having the maximum absolute value is subtracted from the difference data with respect to the cycle and removed. .

According to a fourth aspect of the present invention, there is provided a circuit pattern defect inspection apparatus for detecting a defect in a predetermined inspection area of a circuit pattern having periodicity at least in an X direction on an XY plane. A data input means for inputting the characteristics of each pixel of the circuit pattern in the inspection area by a plurality of pixels arranged in the X direction and generating data to be processed; and at least one pixel in the Y direction in the X direction. For each processing region constituted by the arrangement of pixels, the data to be processed is obtained from the data to be processed input means at predetermined time intervals in accordance with the arrangement of the pixels in the X direction. The data to be processed (hereinafter referred to as standard data) in the processing area to be processed is input to a predetermined integer multiple of the number of pixels of the input standard data. A period difference means for calculating the period difference data by synchronizing the difference between the periodical data delayed relative to the standard data and the input standard data for each time, and calculating the period difference data; Delay instructing means for instructing a time corresponding to a predetermined integer multiple of the number of pixels in the period of the standard data;
Enter the standard data and add the standard data
1 to + N (where N is a natural number of a predetermined value) each pixel delay data for +1 to + N pixels, which are relatively delayed with respect to the input standard data, for each time corresponding to pixels, and Inputting the standard data, and N pixel delay difference means for synchronizing the difference with the standard data and calculating pixel delay difference data for each of the pixel delay data of +1 to + N pixels separately; The input standard data is separately divided by a time corresponding to +1 to + N (N is a natural number of a predetermined value) pixels, respectively.
+1 which is relatively faster than the input standard data
The difference between each pixel early-appearing data for + N pixels and the input standard data is synchronized with each other, and +
N pixel advance difference means for individually calculating pixel advance difference data for each pixel advance data of 1 to + N pixels; and the pixel delay difference means for each of the pixel delay difference means and each of the pixel advance difference means. The pixel delay difference data calculated by the means or the pixel early difference data calculated by the pixel early difference means and the periodic difference data calculated by the cycle difference means are multiplied in synchronization with each other, and +1 to + N pixels Pixel difference data and +1
For each of the (2 × N) inner product multiplying means for calculating the inner product multiplication data for each of the pixel early difference data of up to + N pixels, and for each of the pixel delay difference means and each of the pixel early difference data, The inner product multiplication data calculated by the inner product multiplication means is integrated from the start of the input of the inner product multiplication data of the first pixel to the completion of the input of the inner product multiplication data of the last pixel, to obtain +1 to + N pixels. The inner product data for each pixel delay difference data and each pixel early-appearance difference data of +1 to + N pixels is calculated separately (2 × N).
Number of inner product calculation means, and for each of the pixel delay difference means and each of the pixel advance difference means, the pixel delay difference data calculated by the pixel delay difference means or the pixel advance difference calculated by the pixel advance difference means Square the data, +1 to
(2 × N) squared multiplying means for individually calculating squared multiplied data for each pixel differential difference data of + N pixels and each pixel early difference data of +1 to + N pixels; And for each of the pixel early-appearance difference means, the squared multiplication data calculated by the square multiplication means from the start of the input of the squared multiplication data of the first pixel to the completion of the input of the squared multiplication data of the last pixel. (2 × N) square integration calculating means for respectively calculating the square integration data for each pixel delay difference data of +1 to + N pixels and each pixel early difference data of +1 to + N pixels; For each of the pixel delay difference means and each pixel early appearance difference means, the inner product data calculated by the inner product calculation means is divided by the square integration data calculated by the square integration calculation means. Accordingly, the correlation amounts for the respective pixel delay difference data of +1 to + N pixels and the respective pixel early difference data of +1 to + N pixels are calculated respectively (2 ×
N) correlation amount calculation means, and for each of the pixel delay difference means and each pixel early appearance difference means, the pixel delay difference data calculated by the pixel delay difference means or the pixel calculated by the pixel early difference means For early-appearance difference data,
The correlation amount calculated by the correlation amount calculating means is multiplied by +
(2 × N) correction data calculation means for individually calculating correction data for each pixel delay difference data of 1 to + N pixels and each pixel early difference data of +1 to + N pixels, and calculation by the periodic difference means From the obtained periodic difference data, all the correction data for each of the pixel delay difference data of +1 to + N pixels and each of the pixel early-appearance difference data of +1 to + N pixels calculated by the correction data calculation means are synchronously drawn. A correction difference unit that calculates correction difference data; a defect detection unit that compares the correction difference data calculated by the correction difference unit with a predetermined threshold value and detects the correction difference data larger than the threshold value Means.

According to a fifth aspect of the present invention, in the above-described defect inspection apparatus for a circuit pattern,
The correction difference means calculates the maximum absolute value from among the pixel delay difference data of +1 to + N pixels and the pixel advance difference data of +1 to + N pixels, and corrects only the calculated absolute value maximum correction data. It is used as data to calculate correction difference data.

[0013]

The operation of the present invention is as follows. That is,
According to the first aspect of the invention, first, in the first processing step, the characteristics of the circuit pattern in the inspection area (for example, the brightness when the circuit pattern is photographed by the camera) are arranged at least in the X direction. Pixels (X _i , i = 0 to 0)
m or (X _i , Y _j ), i = 0 to m, j = 0 to n)
The characteristics of each pixel of the input circuit pattern are quantitatively converted (for example, the brightness when photographed by a camera is converted into digital data of 256 gradations), and the data to be processed is create. When the data thus obtained is represented by a function g (x, y), g (x,
y) = f (x, y) + q (x, y). Where f
(X, y) is the data that is periodic a table to function,
q (x, y) is a function representing non-periodic data (defect data). Also, x = 0 to m and y = 0 to n.

Next, in the second processing step, the data to be processed converted in the first processing step is converted into a processing area constituted by an arrangement of each pixel in the X direction with respect to one pixel in the Y direction, that is, the processing area described above. In one processing step, when pixels are configured in a two-dimensional array of (X _i , Y _j ), (X
₀ , Y _j ) to (X _m , Y _j ). Further, when the pixels are simply constituted by the one-dimensional array (X _i ), the arrangement of the pixels can be used as it is as the processing area. At this time, since y becomes constant, the data of each processing area can be expressed as a function g (x) = f (x) + q (x).

Hereinafter, processing from the third processing step to the seventh processing step is performed for each processing area. In the third processing step, the cycle of the data to be processed in a certain processing area is obtained, and the obtained cycle is calculated by the number of pixels. The cycle is, for example, X
The correlation may be obtained for all pixels in the X direction while shifting one pixel in the direction, and the number of pixels shifted in the X direction when the correlation becomes high may be estimated by estimating the number of pixels corresponding to the period. it can. Further, the period may be calculated by the number of pixels based on the period of the circuit pattern known at the time of design.

In the fourth processing step, the data to be processed in a certain processing area and the data to be processed are shifted in the X direction by an integer multiple of the number of pixels corresponding to the cycle of the processing area calculated in the third processing step. The difference with the data is calculated, and the difference data with respect to the cycle is obtained. For example, if the cycle of the processing area is T pixels, the data shifted in the “−” direction by one cycle is g ′ (x) = f (x + T) + q (x +
T), the difference h (x) between these data is
h (x) = (f (x) + q (x))-(f (x + T) +
q (x + T)). At this time, among the data of each pixel, the periodic data are canceled out from each other, and the component of only the non-periodic defect data remains. That is, since f (x) = f (x + T), h (x) = q
(X) -q (x + T).

However, the cycle obtained in the third process is only a calculation. On the other hand, the data to be processed, which is an object of data processing, includes an error at the time of input. And the period in the data to be processed do not always match. When the above-described processing in the fourth processing step is performed with the calculated cycle and the cyclic error in the data to be processed being “t”, h (x) = (f (x) +
q (x))-(f (x + T + t) + q (x + T + t))
= (F (x) -f (x + T + t)) + (q (x) -q
(X + T + t)). Therefore, when the above-described difference processing is performed, a residual component due to the difference between the periodic components shifted from each other remains in addition to the defect data component, so that the defect data cannot be specified and the defect cannot be detected. Therefore, it is necessary to perform correction processing in the following fifth to seventh processing steps to remove the residual component (f (x) -f (x + T + t)) and leave only the defect component.

In the fifth processing step, the data to be processed in a predetermined processing area and the data to be processed are converted by Z pixels (Z is an integer) in the respective directions (directions corresponding to the sign “+” or “−” of each value). ) Is ± 1 to ± N
(N is a natural number of a predetermined value).
The difference data calculated for each of ± 1 to ± N is represented by g _{d1 +} (x), g _d1- (x),..., G _{dN +} (x), g
_dN- (x). In the sixth processing step, the correlation amount of the difference data with respect to the cycle calculated in the fourth processing step to each difference data for ± 1 to ± N calculated in the fifth processing step is expressed as ± 1 ±±. N is calculated for each. This is because the residual component (f (x) -f (x + T +
This is because t)) can be roughly approximated using the difference data for ± 1 to ± N. That is, (f (x) -f
(X + T + t)) = α _n1 × g _{d1 +} (x) + β _n1 × g _d1-
(X) + ... + α _nN × g _{dN +} (x) + β _nN × g _dN- (x)
H (x) = (q (x) -q (x
+ T + t)) + α _n1 × g _{d1 +} (x) + β _n1 × g
_{d1- (x) + ... + α} nN × g dN + (x) + β nN × g
It can be approximately approximated as _dN- (x). Where α
_n1 , _βn1 ,..., _αnN , _βnN are the difference data g
_{d1 +} (x), g _d1- (x), ..., g _{dN +} (x), g _dN-
(X) are correlation amounts. This correlation amount indicates the ratio of the correlation of each difference data to the residual component. Therefore,
For example, if the error “t” is +1 pixel, approximately α _n1
× g _{d1 +} (x) becomes equal to the residual component, and the other correlation amount β
_{n1, ..., α nN, β} nN is "0". Further, when the cycle obtained in the third processing step matches the cycle in the data to be processed, there is no residual component, so that all the correlation amounts are “0”. That is, irrespective of whether or not the cycle obtained in the third processing step matches the cycle in the data to be processed, by performing this correction processing, only the defect component can be extracted. It is not necessary to determine whether or not the cycle obtained in step 1 and the cycle in the data to be processed match.

In the seventh processing step, the respective correlation data for ± 1 to ± N calculated in the sixth processing step are added to the respective difference data for ± 1 to ± N calculated in the fifth processing step. Each correction data (α
_n1 × g _{d1 +} (x), β _n1 × g _d1- (x), ..., α _nN × g
_{dN +} (x) and β _nN × g _dN− (x)) are subtracted from the difference data h (x) for the cycle calculated in the fourth processing step, and removed, and (q (x) −q (x + T +
t)).

Finally, in the eighth processing step, (q (x) -q (x + T +
t)) is detected. For example, among (q (x) -q (x + T + t)) depending on the direction shifted in the fourth processing step,
The original defect component q (x) can be specified, and the value of x can be used to specify the location of the pixel where the defect has appeared. Further, such detection is performed for all processing regions, and defects in all inspection regions of the circuit pattern are detected.

According to the second aspect of the present invention, in the fifth processing step of the first aspect of the present invention, the calculated difference data g _{d1 +} (x), g _d1- (x) _,. g _{dN +}
(X) and g _dN− (x) are each made orthonormal. The result of orthonormalizing each of these difference data is e
_{d1 +} (x), e _d1- (x), ..., e _{dN +} (x), e _dN-
(X), e _{d1 +} (x), e _d1- (x) _{,.
dN +} (x) and e _dN− (x) are _calculated using, for example, Schmidt's orthogonalization method, g _{d1 +} (x), g _d1- (x) _,.
It can be calculated in order from _{dN +} (x) and _gdN- (x). In addition, processing is performed using the orthonormalized difference data in the sixth and subsequent processing steps as well. That is, the residual component (f (x) -f (x + T + t)) is converted to (f (x) -f
(X + T + t)) = α ₁ × e _{d1 +} (x) + β ₁ × e _d1−
(X) + ... + α _N × _{edN +} (x) + β _N × _edN- (x)
H (x) = (q (x) -q (x + T
+ T)) + α ₁ × e _{d1 +} (x) + β ₁ × e _d1- (x) +
... + α _N × is _{e dN + (x) + β} N × e dN- (x) as approximately expressed. Where α ₁ , β ₁ , ..., α _N , β
_N is the orthonormalized difference data e _{d1 +} (x), e
_d1- (x), ..., _{edN +} (x), _edN- (x). As described above, by performing orthonormalization on the difference data for ± 1 to ± N and performing the correction process, the residual component can be more accurately removed, and the defect detection accuracy can be improved.

According to the third aspect of the present invention, in the seventh processing step of the first aspect of the present invention, the calculated correction data (α _n1 × g _{d1 +} (x), β _n1 × g
_d1- (x),..., α _nN × g _{dN +} (x), β _nN × g
_The data having the maximum absolute value is obtained from _dN- (x)), and only the data having the maximum absolute value is used as the correction data to execute the seventh processing. This is because most of the residual components are either differential data (g _{d1 +} (x), g
_{This is because d1-} (x),..., _{gdN +} (x), _gdN- (x)) often show many correlations. Accordingly, if only the data having the highest correlation ratio is subtracted from the difference data with respect to the cycle and removed, most of the residual components are removed, and in practice, sufficient accuracy can be obtained by such a method. .

According to a fourth aspect of the present invention, there is provided an apparatus for approximately realizing the circuit pattern defect inspection method according to the first aspect of the present invention. By means, a characteristic of a circuit pattern in the inspection area, for example, an electric signal is input by at least a plurality of pixels arranged in the X direction, and data to be processed is created.

The period difference means, each pixel delay difference means, and each pixel early difference means are sequentially provided from the data input means to be processed, from the first pixel to the last pixel, in accordance with the arrangement of pixels in the X direction. , Standard data obtained based on being supplied at regular time intervals. If this standard data is represented by a function, it is g (t).
Here, t represents time, t = 0 to t _e (0 is at input start of the first data to be processed pixel, t _e is input upon completion of the processed data in the last pixel) is. Where g (t)
= F (t) + q (t). As described above, f (t) and q (t) are functions representing periodic data and non-periodic data (defect data), respectively. In addition, the cycle delay data, the pixel delay data, or the pixel early appearance data described later are relative to this standard data, and the cycle difference means, the pixel delay difference means, and the standard data respectively input by the pixel early appearance difference means, Gain by delaying or advancing respectively.

The period difference means to which the standard data is input is a period delayed by a time (t _T ) corresponding to a predetermined integer multiple of the number of pixels of the period of the input standard data designated by the delay instruction means. delay data _{(g (t-t T)} )
And the difference between the input standard data and the input standard data are synchronized (subtract the period delay data from the standard data) and output the period difference data. Here, performing the difference in synchronization means performing the difference between the data at different times in consideration of the delay of the period delay data. When this is represented by a function, h (t) = g (t) -g (t
−t _T ), for example, standard data g (t _T + t ₁ )
, The period delay data g (t _T + t ₁ -t _T ) =
The difference from g (t ₁ ) is h (t _T + t ₁ ) = g (t _T + t
₁₎ it will be determined -g (t _1). Note that h (t)
Represents periodic difference data.

In the delay instruction means, for example, standard data is input in advance, and t _T can be obtained by calculating a correlation for each pixel based on the standard data. In addition, based on the cycle of the circuit pattern known at the time of design, t _T obtained in advance may be given to the cycle difference means.

By the above-described processing for calculating the periodic difference data, computationally periodic data are mutually canceled,
Only the defect data is extracted, but actually includes an error at the time of input of the data to be processed. It is necessary to pull from.

In the pixel delay difference means, standard data is input, and the input standard data is separately set for each time (t _{1 to} t _N ) corresponding to +1 to + N (N is a natural number of a predetermined value) pixels. , G (t−t ₁ ),..., G (t−t _N ) of each of the +1 to + N pixels relatively delayed with respect to the input standard data and the input standard data. The differences are respectively synchronized (subtract the standard data from the pixel delay data), and the pixel delay difference data (g for each of the pixel delay data of +1 to + N pixels)
_d1- (t),..., _gdN- (t)) are output separately. This pixel delay difference means is for +1 pixel delay data difference,
.., + N pixel delay data difference is provided separately, and is composed of N pieces. For example, t ₁ is a time until the input of the data of the first pixel is completed, and t _N is a time until the input of the data of the N-th pixel is completed. Also, t ₂ −t ₁ = t ₃ −t ₂ =... = T _N −t _N−1 . When this is expressed by a function, g _d1− (t) = g (t) −g
(T−t ₁ ),..., G _dN− (t) = g (t) −g (t−
t _N) becomes, for example, standard data g (t ₁ + against t ₁₎ of data, + 1 pixel delay of pixel delay data g (t
₁ + t ₁ −t ₁ ) = g (t ₁ ) is _equal to g _d1− (t ₁
+ T ₁ ) = g (t ₁ + t ₁ ) −g (t ₁ ).

In the pixel early appearance difference means, standard data is input, and the input standard data is stored in a time (t _{1 to} t) corresponding to +1 to + N (N is a natural number of a predetermined value) pixels.
_N ), each pixel advance data (g (t + t ₁ ),..., G (t + t _N )) for +1 to + N pixels relatively advanced with respect to the input standard data, and the input standard data. The difference from the data is synchronized with each other (standard data is subtracted from the pixel early-appearing data), and +1 to + N
Pixel advance difference data (g _{d1 +} (t),..., G _{dN +} (t)) for each pixel advance data is output separately. This pixel advance difference means is provided separately for +1 pixel advance data difference,..., + N pixel advance data difference, and is constituted by N pieces. If this is expressed by a function, g _{d1 +} (t)
= G (t) -g (t + t 1), ..., g dN + (t) = g
(T) −g (t + t _N ), for example, standard data g
(T _e -t ₁₎ for the data of + 1 pixels of the pixel early shift early shift data _{g (t e -t 1 + t} 1) = g difference between (t _e) is g _d1- (t _e -t _{1) = g (t e -t 1)} -g (t
_e ).

The inner product multiplying means, inner product calculating means, squaring multiplying means, square integral calculating means, correlation amount calculating means, and correction data calculating means comprise pixel delay difference data of +1 to + N pixels and +1 to + N pixels. , Respectively, for the pixel early-appearance difference data, each of which is composed of (2 × N) pixels. Each means for each pixel delay difference data or each pixel early appearance difference data performs similar processing to calculate each correction data. Therefore, the operations of the inner product multiplying means, inner product calculating means, squared multiplying means, square integration calculating means, correlation amount calculating means, and correction data calculating means for pixel delay difference data of +1 pixel delay are taken as an example. The operation of will be described below.

In the inner product multiplication means, the pixel delay difference data calculated by the pixel delay difference means (also the pixel early difference data calculated by the pixel early difference means) and the cycle difference data calculated by the cycle difference means are respectively The product is multiplied in synchronization to calculate inner product multiplication data. When this is expressed by a function, _nd1- (t) = h (t) * _gd1- (t) (where t
= The 0~t _e). Here, n _d1- (t) indicates inner product data delayed by +1 pixel.

It should be noted that the period difference data output from the above-described period difference unit is compared with the pixel delay difference data output from each pixel delay difference unit and each pixel early difference data output from each pixel early difference unit. To synchronize,
For example, standard data may be input at the same timing in the period difference means, each pixel delay difference means, and each pixel early appearance difference means.

The inner product calculating means converts the inner product multiplied data calculated by the inner product multiplying means from the start of input of the inner pixel multiplied data of the first pixel (t = 0) to the input of the inner product multiplied data of the last pixel. obtaining the inner product data by integrating until complete (t = t _e). When this is represented by a function, N _d1 − = ∫ (n _d1−
A (t)) dt [t = 0 to t _e]. Here, N _d1- indicates inner product data delayed by +1 pixel, “∫dt” indicates integration,
[T = 0 to t _e ] indicates an integration range.

The squaring multiplication means squares the pixel delay difference data calculated by the pixel delay difference means (the same applies to the pixel early difference data calculated by the pixel early difference means) to calculate squared multiplication data. _Expressing this as a function, j _d1- (t)
= G _d1- (t) × g _d1- (t) (where t = 0 to t _e )
Becomes Here, j _d1- (t) indicates the squared multiplication data delayed by +1 pixel.

In the square integration calculating means, the input of the squared multiplication data of the last pixel is completed after the input of the squared multiplication data of the first pixel is started (t = 0). by integrating up to the time (t = t _e) to calculate the square integral data. _Expressing this as a function, J _d1- = ∫
(J _d1- (t)) dt [t = 0 to t _e ]. here,
J _d1- indicates square integration data delayed by +1 pixel.

The correlation amount calculating means calculates the correlation amount by dividing the inner product data calculated by the inner product calculating means by the square integral data calculated by the square integration calculating means. When this is represented by a function, _Vd1- = _Nd1- ÷ _Jd1- . Where V _d1−
Indicates a correlation amount delayed by +1 pixel.

The correction data calculation means multiplies the pixel delay difference data calculated by the pixel delay difference means (also the pixel early difference data calculated by the pixel early difference means) by the correlation amount calculated by the correlation amount calculation means. In addition, the correction data is calculated. When this is represented by a function, k _d1- (t) = V _d1-
× g _d1- (t) (where t = 0 to t _e ). Here, k _d1- (t) indicates correction data delayed by +1 pixel.

The correction data calculated as described above is
It becomes approximately equal to the correction data in the seventh processing step of the first aspect of the present invention. In the correction difference means, the correction data (k _d1- (t),..., K _dN- (t), and k d) are calculated from the cycle difference data h (t) calculated by the cycle difference means.
_{d1 +} (t), ..., k _{dN +} (t); k _d1- (t) is +1 _stroke
Element delay of the correction _data, k dN- (t) is + N pixels delay of the correction data, k _d1 + (t) +1 pixels early shift correction data,
k _{dN +} (t) indicates correction data of + N pixels earlier), and calculates the difference data (data from which only the defect data is extracted) in synchronization. When this is represented by a function, a (t) = h (t)-(k _d1- (t) +... + K
_dN− (t) + k _{d1 +} (t) +... + k _{dN +} (t)) (where t = 0 to t _e ). Here, a (t) indicates the correction difference data.

The periodic difference data calculated based on the standard data input at the same timing as the standard data used to calculate each correction data is input to the correction difference means through different calculations. Therefore, they may not be synchronized in time. Therefore, for example, the processed data input means supplies the processed data in the same processing area twice, calculates each correction data with the standard data obtained based on the initially supplied processed data, and calculates the corrected data. The data is held, and the corrected difference data is synchronized by synchronizing each held correction data with the periodic difference data calculated based on the standard data obtained based on the data to be processed next supplied. What is necessary is just to calculate it.

Finally, the defect detection means compares the correction difference data calculated by the correction difference means with a predetermined threshold value, and detects correction difference data larger than the threshold value. In other words, the data having periodicity has been substantially removed by subtracting the above-described correction data from the periodic difference data, and it can be determined that the remaining component is a defect. Expressing this as a function, "a (t) -S" is expressed as t =
Performed respectively for 0 to t _e, it is determined that "a (t) -S 'is defective portions is not less than" 0 ". In addition,
S indicates a threshold value, and an appropriate value is set by the device.
For example, a value is set so that an error that cannot be removed by the correction processing is erroneously recognized as a defect according to an allowable range of an error when inputting the processed data by the apparatus. In addition, such detection is performed for all processing regions by, for example, sequentially supplying reference data to each processing unit for each processing region to perform inspection, or by separately providing an inspection device for each processing region, for example, to detect the entire circuit pattern. Detect defects in the inspection area.

According to a fifth aspect of the present invention, there is provided an apparatus for approximately realizing the circuit pattern defect inspection method according to the third aspect of the present invention. The operation is achieved by the correction difference means of the apparatus according to the fourth aspect of the present invention, wherein the maximum absolute value data is calculated from the correction data calculated by the correction data calculation means, and the calculated maximum absolute value is corrected. By subtracting and removing only the data from the periodic difference data, most of the residual components of the periodic difference data are removed.

[0042]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram showing a schematic configuration of a circuit pattern defect inspection apparatus used in one embodiment of the present invention.
The apparatus of this embodiment inspects a defect of a circuit pattern formed on a die on a memory wafer. Hereinafter, a case of detecting a defect of a circuit pattern formed on a die on a memory wafer will be described. .

When the circuit pattern P of the die is schematically represented, as shown in FIG. 3A, the die has a predetermined periodicity due to irregularities on the die surface. Such a circuit pattern P
Is usually manufactured by repeating an optical lithography process about 10 to 20 times on the basis of an original pattern called a reticle, and various defects may occur during the manufacture. This defect is schematically shown in FIG. Q ₁
Conductor spacing reduced, Q ₂ is the conductor width shorter, Q ₃ is disconnected, Q ₄
Short circuit, Q ₅ is an isolated defect, Q ₆ is misalignment of the pattern,
Q ₇ represents another pattern deformation respectively.

The defect in the present invention refers to any non-periodic pattern (noise) added to the periodic pattern because the present invention utilizes the periodicity of the pattern. This includes noise of all sizes, shapes and densities. Therefore, in an actual circuit pattern, there are a case where the circuit pattern itself is abnormal (such as the above-described disconnection or short circuit) and a case where a foreign substance is attached to the circuit pattern.

In order to detect the above-mentioned defects, the apparatus of this embodiment inputs a circuit pattern P to be inspected by an input unit 1, converts the circuit pattern P into digital data by an A / D converter 2, and converts the data to be processed. And creates the processed data in the image memory 3.
And a data processing unit 4 based on the data to be processed.
, A defect is detected, and the inspection result is output to the printer 5, converted into analog data by the D / A converter 6, and output to the monitor 7. The processed data input from the input unit 1 and stored in the image memory 3 is output to the monitor 7 via the D / A converter 6 so that the operator can check the inspection area. Further, the entire apparatus is configured to be controlled by the control unit 8. The details of each part will be described below.

In the input section 1, the XY stage 11 on which the memory wafer W is mounted is moved in the XY directions by the control section 8, and the position of the inspection area of the die to be inspected and the lens 12 are adjusted. The sensor 13 senses the circuit pattern P in the inspection area of the die through the lens 12 with a degree of brightness, and outputs the sensed signal (analog data) to A / A.
The D converter 2 is provided. Sensor 13
Is composed of, for example, 512 pixels in the X direction and 512 pixels in the Y direction (512 × 512), and each pixel senses the brightness of the circuit pattern P. Such a sensor 13
Is composed of, for example, a CCD, and the sensed brightness is stored as a charge amount. The sensor 13 may have a one-dimensional array of 512 pixels in the X direction and one pixel in the Y direction. At this time, the set inspection area matches a processing area described later.

The signal sensed by the sensor 13 is converted by the A / D converter 2 into digital data of 256 gradations (0 to 255) for each pixel, and the conversion result is stored in the image memory 3. That is, 512 bytes are stored in the image memory 3.
The brightness of each pixel of the circuit pattern P divided into × 512 pixels is stored as data expressed in 256 gradations.

The data to be processed stored in the image memory 3 is converted by the D / A converter 6 into analog data.
In addition to displaying on the monitor 7, the data processing unit 4 detects a defect of the circuit pattern P according to a processing procedure described later, outputs an inspection result to the printer 5, and displays the result on the monitor 7. The data processing unit 4 includes a microcomputer (not shown) including a CPU (Central Processing Unit), a CPU memory, a ROM (Read Only Memory), and the like. A defect detection procedure (program) described later is stored in the ROM in advance, and the CPU executes processing according to the program. The CPU memory is used for temporary storage of data being processed.

The control unit 8 sends XY to the input unit 1.
The movement of the stage 11 is controlled, the input timing of the data to be processed is measured, the conversion instruction is given to the A / D converter 2, and the defect detection start instruction is given to the data processing unit 4 to control the entire operation of the apparatus. I do. The control unit 8 is also configured by a microcomputer, similarly to the data processing unit 4 described above. The ROM stores the control unit 8 as described above.
Are stored in advance, and the CPU is configured to execute processing in accordance with the programs. In the block diagram shown in FIG. 2 , the control unit 8 and the data processing unit 4 described above are separately illustrated.
That is, it may be constituted by one CPU.

Next, a procedure for detecting a defect by the above-described embodiment will be described with reference to a flowchart shown in FIG. The following steps S1 to S8 correspond to the first to eighth processing steps in the present invention, respectively.

First, data to be processed is input from the input unit 1, converted into digital data, and stored in the image memory 3 (step S1). The flow of such processed data will be described with reference to FIG. A circuit pattern P as shown in FIG. 4A is sensed by the sensor 13 as analog data as shown in FIG. 4B, and the analog data is shown by the A / D converter 2 as shown in FIG. The image data is converted into digital data of 256 gradations (0 to 255) and stored in the image memory 3. In the figure, X _i , Y
_j (i, j = 0 to 511, where i, j = 0 to 9 in the figure)
Only) is the sensor 1
3 pixels. In FIG. 4B, (X ₀ ,
(Y ₀ ) to (X ₉ , Y ₀ ). The processed data of the circuit pattern P expressed in 256 gradations is stored in the image memory 3, and the data processing unit 4 detects a defect based on the data in the procedure described below. However, in order to facilitate understanding, the following description will be made based on binarized data to be processed as shown in FIG. FIG. 5 (a),
4B and 4C show the circuit pattern P, the data sensed by the sensor 13 and the data stored in the image memory 3, respectively, as in FIG. Further, Q in the figure represents a defect, and in the following processing, a case where this defect Q is detected will be described.

The data to be processed stored in the image memory 3 in step S1 is converted into a processing area constituted by an arrangement of each pixel in the X direction with respect to one pixel in the Y direction, that is,
(X ₀ , Y _j ) to (X ₅₁₁ , Y _j ) (j = ₀ to ₅₁₁ )
(Step S2). Here, (X ₀ , Y) of the data to be processed shown in FIG.
₀ ) to (X ₁₇ , Y ₀ ) can be represented by a graph as shown in FIG. However, the defect Q is indicated by a dotted line. When this graph is represented by a function g (x, y), the following equation (1) is obtained. g (x, y) = f (x, y) + q (x, y) (1) where f (x, y) represents periodic data,
q (x, y) is a function representing non-periodic data (defect Q). Also, x = 0 to 511, y = 0, and y
Is constant, and is represented as the following equation (2) for simplicity. g (x) = f (x) + q (x) (2) As described above, when the sensor 13 is configured by one-dimensional pixels, the circuit pattern P input from the input unit 1
Coincides with the processing area, and at this time, the processing in step S2 is simultaneously executed in the processing in step S1 described above.

The following steps S3 to S7 are performed for each processing area divided in step S2.

That is, in the process of step S3, the cycle of the data to be processed in each processing area is obtained, and the obtained cycle is calculated by the number of pixels. The period of this processing region can be obtained by several methods. For example, while shifting the data to be processed by one pixel in the X direction, the correlation is obtained for all the pixels in the X direction, and when the correlation becomes high, the number of pixels shifted in the X direction is estimated as the number of pixels corresponding to the period. Can be obtained. Further, if the period is calculated by the number of pixels based on the period of the circuit pattern P known at the time of design, a somewhat accurate period can be obtained in advance, and the processing time can be reduced. For example,
The period “T” of the processing area for Y ₀ shown in FIG.
Is calculated as “5” pixels from FIG.

Next, the difference between the data to be processed in each processing area and the data obtained by shifting the data to be processed in the X direction by an integer multiple of the number of pixels corresponding to the cycle of the processing area calculated in step S3 is calculated. The difference is calculated and the difference data for the cycle is obtained (step S4). For example, data obtained by shifting the data to be processed (FIG. 6A) in the processing area for Y ₀ by the period “T” (in the case of 1 ×) in the “−” direction is as shown in FIG. 6B. It can be represented in a simple graph. Also, as a function, data g ′ shifted by one cycle
(X) can be expressed by the following equation (3). g ′ (x) = f (x + T) + q (x + T) (3) Therefore, the difference between the data to be processed and the data obtained by shifting the data to be processed in the “−” direction by one cycle is shown in FIG. )
It becomes as shown in. To explain this by a function, the difference data h (x) can be expressed by the following equation (4). h (x) = g (x) −g ′ (x) = (f (x) + q (x)) − (f (x + T) + q (x + T)) (4)

At this time, of the data of each pixel, the periodic data is canceled out from each other, and only the component of the defect Q having no periodicity remains. That is, f (x) = f
(X + T), the above equation (4) becomes the following equation (5)
Can be represented by h (x) = q (x) -q (x + T) (5) Accordingly, since only the component of the defect Q can be extracted, the defect Q can be specified. Note that since the circuit pattern P has periodicity, the same result can be obtained even if the processing is performed with an integer multiple of the period shifted. Therefore, if the number of pixels corresponding to the cycle can be calculated, the difference data for the cycle may be calculated by shifting the number of pixels by an integer multiple. Good.

However, the cycle obtained in step S3 is merely a calculation. On the other hand, the data to be processed is the sensor 13 and the A / D converter 2
In an actual apparatus, the calculation cycle does not always coincide with the cycle in the data to be processed, as shown in FIGS. 5 and 6. As described above, the error between the calculated cycle (referred to as “T”) and the cycle in the data to be processed (referred to as “T ′”) is represented by “t” (T ′).
= T + t), and the above-described processing of step S4 is performed, as shown in FIG. FIG. 7A shows the data to be processed of the pixel “T ′” in the cycle, FIG. 7B shows the data obtained by shifting the data to be processed by the pixel “T” in the calculation,
(C) is a graph showing the difference data. As shown in the figure, a residual component due to an error remains in addition to the component of the defect Q, so that defect data cannot be specified and a defect cannot be detected. When this is expressed by a function, it can be expressed as the following equation (6). h (x) = (f (x) + q (x))-(f (x + T + t) + q (x + T + t)) = (f (x) -f (x + T + t)) + (q (x) -q (x + T + t)) … (6)

Therefore, the residual component (f (x) -f (x + T
+ T)), only the defect Q can be left. Here, if “t” is known, difference data (f (x) −f (x + t)) between the data to be processed in the processing area and the data obtained by shifting the data to be processed by t pixels, where f (x +
By subtracting (T + t) = f (x + t)) from the above-mentioned h (x), residual components can be removed. But,
In general, since “t” is unknown, a correction process in the following steps S5 to S7 is performed, and the residual component (f
(X) -f (x + T + t)) is removed.

The correction process is performed as follows.
That is, in step S5, the data to be processed in the predetermined processing area and the data to be processed are each shifted by Z pixels (Z is an integer) in the respective directions (directions corresponding to the sign “+” or “−” of each value).
The difference data from the shifted data is ± 1 to ± N (N
Calculates a natural number of a predetermined value described later), and normalizes each calculated difference data.
In step S6, the correlation amount between the difference data with respect to the cycle calculated in step S4 and each of the difference data that is orthonormalized for ± 1 to ± N calculated in step S5 is calculated for ± 1 to ± N. Calculate each.

This is the difference data h (x) with respect to the cycle.
Of the residual component (f (x) -f (x + T + t)) is ± 1
This is because ± N can be approximated using each of the difference data that has been orthonormalized. That is, the residual component (f
(X) -f (x + T + t)) can be approximately developed as shown in the following equation (7). (F (x) -f (x + T + t)) = [alpha] ₁ * _{ed1 +} (x) + [beta] ₁ * _ed1- (x) + ... + [alpha] _N * _{edN +} (x) + [beta] _N * _edN- (x) ... ( 7) Here, e _{d1 +} (x), e _d1- (x) _{,.
dN +} (x) and _edN- (x) are difference data g _{d1 +} (x), g _d1- (x), calculated for ± 1 to ± N, respectively.
, G _{dN +} (x) and g _dN- (x) are the results of orthonormalization, respectively, and α ₁ , β ₁ ,..., Α _N , β _N are e
_{d1 +} (x), e _d1- (x), ..., e _{dN +} (x), e _dN-
(X) are correlation amounts. The correlation amount indicates the ratio of the correlation between the orthonormalized difference data and the residual component.

Therefore, the difference data h (x) with respect to the cycle
Can be approximately expressed as shown in the following equation (8). h (x) = (q ( x) -q (x + T + t)) + α 1 × e d1 + (x) + β 1 × e d1- (x) + ... + α N × e dN + (x) + β N × e dN- ( x) ... (8)

Therefore, each of the difference data e _{d1 +} (x), e _d1- (x),
.., E _{dN +} (x), e _dN− (x) and the correlation amounts α ₁ , β
_{By determining 1} ,..., Α _N and β _N , the residual component of h (x) can be removed.

Therefore, a method of calculating each data will be described below. First, e _{d1 +} (x), e _d1- (x),
.., E _{dN +} (x) and e _dN− (x) are difference data g _{d1 +} (x), g calculated for ± 1 to ± N, respectively.
_{d1- (x), ..., g} dN + (x), g dN- a (x), for example, by using the orthogonal method of _{Schmidt, g d1 + (x),} g
_{d1- (x), ..., g} dN + (x), respectively, from _g dN- (x) in order can be obtained by orthonormalization. First, e _{d1 +} (x) normalizes g _{d1 +} (x), which is the first difference data, as shown in the following equation (9). _{e d1 + (x) = g} d1 + (x) / ‖g d1 + (x) || ... (9) where, ‖g _d1 + (x) || represents the norm of g _d1 + (x). This norm is obtained by calculating (g _{d1 +} (x)) ² as x = 0 to 5
11 (corresponding to the number of pixels in the X direction), the sum of the respective results is calculated, and the square root of the sum is calculated.

Next, e _d1- (x) is, g _d1- and (x) e _d1 + (x) obtained in the above (9) for the following equation (10)
Are orthogonalized as follows. _gd1- ^' (x) = _gd1- (x)-( _gd1- (x), _{ed1 +} (x)) * _{ed1 +} (x) (10) where ( _gd1- (x), e ₁₊ (x)) is g
_Represents the inner product of _d1- (x) and e ₁₊ (x). This inner product is
g _{d1 −} (x) × _{ed1 +} (x) corresponds to the sum of the respective results calculated for x = 0 to 511 (corresponding to the number of pixels in the X direction). Then, g _d1- '(x) orthogonalized by the equation (10) is normalized in the same manner as in the above equation (9).
This is represented by equation (11). _{e d1- (x) = g d1-} '(x) / ‖g d1-' (x) || ... (11)

[0065] Furthermore, e _d2 + (x) is, g _d2 + (x) for the above-mentioned (9), (11) e d1 + was determined by the equation (x) and e _d1- (x), the following equation (12) Are orthogonalized as follows. _{g d2 + '(x) =} g d2 + (x) - (g d2 + (x), e d1 + (x)) × e d1 + (x) - (g d2 + (x), e d1- (x)) × e d1 _- (X) ... (12) Then, g _{d2 +} '(x) orthogonalized by the equation (12) is normalized in the same manner as the above equations (9) and (11). This is (1
3) Expressed by the equation. ed2 ₊ (x) = gd2 ₊ '(x) / {gd2 ₊ ' (x)} (13) Hereinafter, _ed2- (x), ..., _{edN +} (x), _edN- (x)
Are similarly orthonormalized in the same manner.

Next, the correlation amounts α ₁ , β ₁ ,..., Α _N , β
_N is h (x), e _{d1 +} (x), e _d1- (x) _,.
Since it is the ratio of each correlation to _{edN +} (x) and _edN- (x), it is obtained as follows. For example, α
₁ is given by h (x) and e as shown in the following equation (14).
It can be obtained by taking the inner product of _{d1 +} (x). α ₁ = (h (x), e ₁₊ (x)) (14) β ₁ ,..., α _N , and β _N can be obtained in the same manner as α ₁ . Each of these correlation amounts is “−1”.
It takes a value in the range from "1" to "1".

[0067] Therefore, each difference data (e _d1 + was orthonormalization respectively for ±. 1 to ± N calculated in step _{S5 (x), e d1- (} x), ..., e dN + (x),
e _dN− (x)) is _added to ± _N calculated in step S6.
Each correlation amount (α ₁ , β ₁ ,..., Α _N ,
β _N ) and each corrected data (α ₁ × e
_{d1 +} (x), β ₁ × e _d1- (x), ..., α _N × e
_{dN +} (x), β _N × e _dN− (x)) are subtracted from the difference data h (x) for the cycle calculated in step S4 to remove them, and (q (x) −q (x + T +
t)) (step S7). The error " t " between the calculated cycle "T" and the cycle "T '" of the input data to be processed is considered to be within approximately one pixel, so that in practice, the correction data _{ed1 +} (x) , E _d1- (x)
Sufficient accuracy can be obtained by performing only (N = 1). For example, if the error “t” is +1 pixel, α ₁ × e _{d1 +} (x) becomes approximately equal to the residual component, and the other correlation amounts β ₁ ,..., Α _N , β _{N become} “0”. ”, And the cycle“ T ′ ”of the processed data to which the calculation cycle“ T ”is input.
If there is no residual component, there is no residual component, and all the correlation amounts are “0”. That is, irrespective of whether “T” and “T ′” match, by performing this correction process, only the defect component can be extracted. There is also an effect that it is not necessary to determine whether or not.

[0068] By the way, e _d1 + calculated in step S5 described above _{(x), e d1- (x} ), ..., e dN + (x), e
_{Since dN-} (x) is orthogonalized, the processes in steps S6 and S7 described above may be performed simultaneously as follows. That is, first, the correlation component of e _{d1 +} (x) is subtracted from h (x), and the subtraction result (h ₁ (x)
And will be), e _d1- (amount of correlation calculated beta ₁ of x), the correlation amount h of e _d1- (x) on the basis of the beta _1
1 (x), and thereafter, the correlation amount is calculated from the result (h _N (x)) obtained by sequentially subtracting the respective correlation components, and each correlation component is calculated based on h _N (x) based on the calculated correlation value. To pull from. This is shown in the following equations (15) to (18). α ₁ = (h (x), _{ed 1+} (x)) (15) h ₁ (x) = h (x) −α ₁ × _{ed 1+} (x) (16) β ₁ = (h ₁ (x _{), e d1- (x))} ... (17) h 2 (x) = h 1 (x) -β 1 × e d1- (x) ... (18) below, successively calculated in the same manner. This is, as described above, e _{d1 +} (x), e _d1- (x),..., E _{dN +} (x),
Since _edN- (x) is orthogonalized, for example, _{ed1 +} (x) and _ed1- (x) can be expressed by the following equation (19). ( _{Ed1 +} (x), _ed1- (x)) = 0 (19) Accordingly, the following equation (20) is established. β ₁ = (h ₁ (x), _ed1- (x)) = (h (x) −α ₁ × _{ed1 +} (x), _ed1- (x)) = (h (x), _{ed1- (x)) - (α 1} × e d1 + (x), e d1- (x)) = (h (x), e d1- (x)) -α 1 × (e d1 + (x), e d1- (X)) = (h (x), _ed1- (x)) (20) Therefore, after calculating the total correlation amount by the above equation (14), it is possible to collectively subtract from h (x). Or the equations (15) to (18)
Even if the calculation is performed in such a manner that the correlation component is sequentially subtracted, the result is approximately the same. In addition, the equations (15) to (1)
Processing by the method as in 8) has the effect of saving CPU memory when calculating by the CPU.

Finally, in step S8, (q (x) -q (x + T +
t)), the original defect component q (x) is specified from the direction shifted with respect to the cycle, and the location of the pixel is x
Can be specified. By performing such processing for all processing regions, the presence or absence of a defect and the position of the defect can be detected for all inspection regions of the circuit pattern.

An example of a defect detection result by the above data processing will be described with reference to FIG. Defective component appears in pairs of Q _R, Q _I. This is calculated from q (x) and q (x + T +
This is because the component (t) is extracted. Which of the two defect components is the original defect q (x) can be determined from the direction shifted in step S4. For example, FIG. 6, as shown in FIG. 7, "-" if the were shifted in the direction, it can be seen that in FIG. 8, the right of the defect Q _R is the original defect q (x). Then, it is possible to detect be based on pixels appears defective Q _R, is defective in any position on the actual circuit pattern P.

It should be noted that step S5 of the above-described defect detection procedure is performed.
In the above, the difference data for ± 1 to ± N are respectively orthonormalized, but the processing of steps S6 and S7 may be executed without normalizing these difference data. At this time, each difference data (g _{d1 +} (x), g
_{d1- (x), ..., g} dN + (x), the amount of correlation _{g dN- (x)) (α} n1, β n1, ..., α nN, β nN) is calculated as follows.

First, each difference data is described in (9) above.
Each difference data (g _{d1 +} ″ (x), g
_d1- "(x), ..., _{gdN +} " (x), _gdN- "(x))
Is shown in the following equation (9) ′. gd1 ₊ "(x) = gd1 ₊ (x) / {gd1 ₊ (x)} _gd1- " (x) = _gd1- (x) / { _gd1- (x)} _{gdN +} "(x) = gdN ₊ (x) / {gdN ₊ (x)} _gdN- "(x) = _gdN- (x) / { _gdN- (x)} (9) '

On the other hand, each correction data in step S7 includes difference data h (x) with respect to the cycle and the above-described normalized difference data (g _{d1 +} "(x), g _d1- ").
(X),..., G _{dN +} ”(x), g _dN− ” (x)) are calculated as in the above equation (14), and the calculated result is multiplied by each normalized difference data. By combining
The ratio of each correlation can be determined roughly. For example, the correction data to be obtained for g _{d1 +} ”(x) can be expressed by the following equation (14) ′. (H (x), g _{d1 +} ” (x)) × g _{d1 +} ”(x) = (h (x), _{g d1 + (x) / ‖g} d1 + (x) _{||) × g d1 + (x)} / ‖g d1 + (x) || = (h (x), g d1 + (x)) / ‖g d1 + (x) || ² × g _{d1 +} (x)… (14) '

Therefore, the correlation amount α _n1 of g _{d1 +} (x) is
_{(H (x), g d1} + (x)) / ‖g d1 + (x) ‖ ² and equal, also, other correlation quantity _{(β n1, ..., α nN} , β nN)
Is similarly obtained. This is represented by the following equation (14) ″. Α _n1 = (h (x), g ₁₊ (x)) / {g _{d1 +} (x)} ² β _n1 = (h (x), g ₁₋ (x )) / {G _d1- (x)} ² α _nN = (h (x), g _{N +} (x)) / {g _{dN +} (x)} ² β _nN = (h (x), g _N− (x )) / {G _dN- (x)} ² ... (14) "

As described above, when correction is performed without performing orthonormalization, the accuracy of correction is lower than in the case of performing orthonormalization, but sufficient accuracy is obtained in practical use.

Further, step S7 of the above-described defect detection procedure
, The calculated correction data (α ₁ × e
_{d1 +} (x), β ₁ × e _d1- (x), ..., α _N × e
_{dN +} (x), β _N × e _dN- (x)), or each correction data (α _n1 × g
_{d1 +} (x), β _n1 × g _d1- (x), ..., α _nN × g
_{From dN +} (x) and β _nN × g _dN− (x)), the correction data with the maximum absolute value is obtained, and only the obtained correction data is
Subtract and remove from the difference data h (x) for the cycle,
(Q (x) -q (x + T + t)) may be obtained. This is because most of the residual components often show many correlations with any of the terms. Accordingly, if only the data having the highest correlation ratio is subtracted from the difference data with respect to the cycle and removed, most of the residual components are removed, and in practice, sufficient accuracy can be obtained by such a method. .

Further, since the above-described defect detection processing for each processing area in S3 to S7 can be performed independently, if the data processing section 4 is constituted by a plurality of CPUs, each processing area can be executed by each CPU. Can be done in parallel.
By executing such parallel processing, the processing time for detecting a defect in the entire inspection area can be reduced.

When the sensor 13 is constituted by a two-dimensional array of pixels, the input is performed at one time and the data processing unit 4
Is performed (step S2), but if the sensor 13 is composed of pixels in a one-dimensional array, the data is divided into processing regions when data to be processed is input, and data input is performed. The process of step S2 of dividing into processing areas by the unit 4 is performed simultaneously with the process of step S1, and the processing procedure is a procedure of performing the input process in a plurality of times.

Further, when the circuit pattern P in the inspection area of the die is captured by the sensor 13 through the lens 12 in the input unit 1, the circuit pattern P in the inspection area is captured.
It is conceivable that the magnification of the lens 12 is different between the central part and the peripheral part of the lens, and the period on the captured data to be processed may not be constant. A region of 512 × 512 pixels) into several regions (for example, a region of 128 × 128 pixels)
And the data to be processed of the circuit pattern P may be separately processed for each of the divided areas.

In the data processing described in the above embodiment, the case where the defect is extracted by shifting the data to be processed by one cycle in the "-" direction has been described. May be.

Further, even if the data to be processed is shifted in either direction, the periodic data at either end cannot be inspected because there is no data to be removed. Inspection of all inspection areas can be performed.

In the above-described embodiment, the circuit pattern having the periodicity in the X direction has been described. However, the circuit pattern having the periodicity only in the Y direction corresponds to the XY pattern of the memory wafer W.
When mounted on the stage 11, if a relatively periodic axis is made to coincide with the X direction by, for example, rotating by 90 °, a circuit pattern having a periodicity in the X direction can be processed.

Next, a second embodiment in which the above-described defect detection method is constituted by an electric circuit will be described with reference to FIG. The defect inspection apparatus 20 according to the second embodiment inputs a characteristic of a circuit pattern P to be inspected as an electric signal at an input unit 21 and outputs a signal to be processed corresponding to the input data to be processed, for each processing region, The defect inspection circuit 30 is supplied to the defect inspection circuit 30.
In a configuration for counting the extracted defect signal counting section 2 4. Reference numeral 22 denotes a delay instruction unit for instructing the periodic phase delay circuit 32 constituting the defect inspection circuit 30 with a predetermined delay time of the signal to be processed which is being processed.
Reference numeral 3 denotes a threshold value setting unit for setting a threshold value used for specifying a defect from a defect signal. The configuration of each unit will be described in detail below.

The input section 21 has substantially the same configuration as the input section 1 of the first embodiment described above. The input section 21 has a circuit pattern P of a predetermined die inspection area of a memory wafer W mounted on an XY stage (not shown). The degree of brightness is detected as an electric signal by a sensor (not shown). This sensor is, for example, a one-dimensional CCD sensor composed of 1024 pixels in the X direction and one pixel in the Y direction, or 512 sensors in the X direction and 512 pixels in the Y direction.
It is composed of a CCD camera composed of individual pixels. Further, the detected signal to be processed is the X signal for one pixel in the Y direction.
A one-pixel phase delay circuit that constitutes the defect inspection circuit 30 in such a manner that a signal to be processed for each pixel is arranged at a constant time interval from the sensor in accordance with the arrangement of pixels in the X direction for each processing region constituted by the arrangement of pixels in the direction. 31 and the addition side of the addition / subtraction circuit 36. The signal to be processed is represented by g
_o (t). At this time, in the case of the above-described one-dimensional CCD sensor, since the signal to be processed is detected from a region coinciding with the processing region, the detected signal is left as it is in the first pixel in order at a fixed time interval (for example, every 1 μs). At 10
What is necessary is just to supply the defect inspection circuit 30 up to the 24th pixel. In the case of a CCD camera, a signal sandwiched between horizontal synchronizing signals provided at the boundary of the pixel arrangement (scanning line) in the Y direction is supplied to the defect inspection circuit 30 to perform defect inspection for each processing area. You can do it. The input unit 1 corresponds to a processed data input unit in the present invention.

The delay instructing section 22 inputs, for example, a signal to be processed to be inspected in advance and calculates a correlation for each pixel based on the signal. The time corresponding to the number of pixels can be calculated. For example, if the cycle is 5 pixels and the transfer time between each pixel is 1 μs, the cycle delay is instructed to the cycle phase delay circuit 32 by 5 μs. Further, a delay time obtained in advance may be given to the periodic phase delay circuit 32 based on the cycle of the circuit pattern known at the time of design. If the delay time is set as in the latter case, the delay instruction unit 22
May be configured so that the circuit constant of the period delay circuit 32 can be variably set. Since the circuit pattern has periodicity, a similar result can be obtained even if the processing is performed by shifting the time by an integral multiple of the time corresponding to the number of pixels in the cycle. Therefore, if the time corresponding to the number of pixels in the cycle can be calculated, an integer multiple thereof may be given to the cycle delay circuit 32. However, in order to maximize the area to be inspected, it is better to specify one time of the cycle. . The delay instruction unit 22 corresponds to a delay instruction unit in the present invention.

The threshold value S set by the threshold value setting section 22 is an appropriate value depending on the apparatus, for example, an error that cannot be removed by the correction processing in accordance with an allowable range of error when a signal to be processed is input by the apparatus. Is set so as not to be mistaken for a defect. The threshold value setting unit 22 is configured to be able to input a voltage value corresponding to a predetermined threshold value S to an addition / subtraction circuit 49 included in the defect inspection circuit 30.

Next, the configuration of the defect inspection circuit 30 will be described. The one-pixel phase delay circuits 31, 33 convert the input signals into
This is a delay circuit that delays and outputs the time corresponding to one pixel (for example, 1 μs if the transfer time between pixels is 1 μs). The periodic phase delay circuit 32
This is a delay circuit that delays and outputs the time instructed by the delay instructing unit 23, that is, the time corresponding to the number of pixels in the cycle of the input signal. Reference numerals 34, 35, 36, 49,
50 is an addition / subtraction circuit for subtracting the signal input to the subtraction side from the signal input to the addition side. In these circuits, each signal input to the addition side and the subtraction side is sequentially subtracted. Reference numerals 37, 40, 42, 43, 4
Numerals 6 and 48 denote multiplication circuits for multiplying the two input signals, respectively.
An integration (average) circuit 47 calculates the accumulation of the input signals (integrates from the start of the input of the signal to the end of the input), and reference numerals 39 and 45 denote the two input signals. A division circuit that performs division using one as a division signal and the other as a division signal.

The defect inspection circuit 30 is configured by combining the above-described circuits. That is, first, an output signal from the one-pixel phase delay circuit 31 (hereinafter, referred to as a standard signal g (t)) and the standard signal g (t) are
The difference from the signal further delayed by the time corresponding to the number of pixels of the cycle via 2 is made by the addition / subtraction circuit 34, and the cycle difference signal h (t) is output. Note that the periodic phase delay circuit 32 and the addition / subtraction circuit 34 correspond to a period difference unit in the present invention.

The difference between the standard signal g (t) and a signal obtained by further delaying the standard signal g (t) by a time corresponding to one pixel via the one-pixel phase delay circuit 33 is calculated by the addition / subtraction circuit 35. , A pixel delay difference signal g delayed by +1 pixel
_d1- (t) is output. The one-pixel phase delay circuit 33 and the addition / subtraction circuit 35 correspond to a pixel delay difference unit that delays by +1 pixel in the present invention.

Further, the standard signal g (t) and the input unit 21
The difference between the signal to be processed g _o (t) supplied from, i.e., the standard signal g (t) and the signal earlier by a time corresponding to one pixel is calculated by the addition / subtraction circuit 36, and +1
A pixel advance difference signal g _{d1 +} (t) of the pixel advance is output.
Note that the addition / subtraction circuit 36 corresponds to a pixel advance difference means of +1 pixel advance in the present invention.

On the other hand, the multiplication circuit 37 multiplies the pixel delay difference signal g _d1- (t) delayed by +1 pixel output from the addition / subtraction circuit 35 with the periodic difference signal h (t) output from the addition / subtraction circuit 34. +1 pixel delayed inner product multiplication signal n
_d1- (t), and outputs the inner product multiplied signal n _d1- (t)
_Is calculated by the integration circuit 38, and the inner product data _Nd1- delayed by +1 pixel is output. On the other hand, the multiplication circuit 40 squares the pixel delay difference signal g _d1- (t) delayed by +1 pixel output from the addition / subtraction circuit 35, and outputs a squared multiplied signal j _d1- (t) delayed by +1 pixel. Squared multiplied signal j _d1-
The integration of (t) is calculated by the integration circuit 41, and the square integration data J _d1- delayed by +1 pixel is output. Further, the integration circuit 3
The division product 39 performs division using the inner product data N _d1- from 8 as a division signal, and the square integration data J _d1- from the integration circuit 41 as a division signal, and _obtains a correlation amount V _d1- delayed by +1 pixel.
And the multiplication circuit 42 multiplies the correlation amount V _d1- by the pixel delay difference signal g _d1- (t) delayed by +1 pixel output from the addition / subtraction circuit 35 to _obtain a correction signal k _d1 delayed by +1 pixel. _- (T) is output, and the correction signal k _d1- (t) is input to the subtraction side of the addition / subtraction circuit 49. The multiplication circuit 37, the integration circuit 38, the multiplication circuit 40, the integration circuit 41, the division circuit 39, and the multiplication circuit 42 are the inner product multiplication means, the inner product calculation means, and the squaring multiplication with a delay of +1 pixel in the present invention. Means, square integration calculating means, correlation amount calculating means, and correction data calculating means.

The multiplication circuit 43 multiplies the pixel difference signal g _{d1 +} (t) output from the addition / subtraction circuit 36 by +1 pixel and the periodic difference signal h (t) output from the addition / subtraction circuit 34 by +1. Pixel-earned inner product multiplication signal n
_{d1 +} (t), and outputs the inner product multiplied signal n _{d1 +} (t)
Is calculated by the integration circuit 44, and the inner product data N _{d1 +} that appears earlier by +1 pixel is output. On the other hand, the multiplication circuit 46 performs squaring of the pixel advance difference signal g _{d1 +} (t) of +1 pixel output from the addition / subtraction circuit 36 to output a squared multiplication signal j _{d1 +} (t) of +1 pixel advance, and squares the signal. Multiplied signal j _{d1 +}
The integration of (t) is calculated by the integration circuit 47, and the square integration data J _{d1 +} of +1 pixel earlier is output. Further, the integration circuit 4
Inner product data N _{d1 +} a from 4 and the division signal, the correlation of +1 pixel early shift is performed in the divider circuit 45 the division was divided signal squaring integration data J _{d1 +} from the integrator 47 V _{d1 +}
Is multiplied by the correlation amount V _{d1 +} and the pixel advance difference signal g _{d1 +} (t) of +1 pixel output from the addition / subtraction circuit 36 in the multiplication circuit 48, and the correction signal k _{d1 +} (t ) _Is output, and the correction signal k _{d1 +} (t) is input to the subtraction side of the addition / subtraction circuit 49. The multiplying circuit 43, the integrating circuit 44, the multiplying circuit 46, the integrating circuit 47, the dividing circuit 45, and the multiplying circuit 48 are the inner product multiplying means, inner product calculating means, squaring multiplying means for the first pixel in the present invention. Means, square integration calculating means, correlation amount calculating means, and correction data calculating means.

Further, the periodic difference signal h (t) output from the addition / subtraction circuit 34 is input to the addition side of the addition / subtraction circuit 49, while the correction signal k delayed by +1 pixel as described above.
_{The signal d1-} (t) and the correction signal k _{d1 +} (t), which is output by +1 pixel, are input to the subtraction side of the addition / subtraction circuit 49, and the respective differences are calculated to output the correction difference signal a (t). Also,
The correction difference signal a (t) is input to the addition side of the addition / subtraction circuit 50, and the threshold S set by the threshold setting unit 23 is set.
Is input to the subtraction side of the addition / subtraction circuit 50, the respective differences are calculated, and a defect signal is output.
4 is input. The addition / subtraction circuit 49 corresponds to a correction difference unit in the present invention, and the addition / subtraction circuit 50, the threshold value setting unit 23, and the counting unit 24 correspond to a defect detection unit in the present invention.

Next, the operation of the defect detection circuit 30 will be described in correspondence with the above-described defect inspection method of the first embodiment.
The periodic difference signal h (t) output from the addition / subtraction circuit 34
As described in the first embodiment, if the delay amount in the periodic phase delay circuit 32 and the phase corresponding to the period on the signal input by the input unit 21 match, the periodicity is Although the component having the component is removed, an error or the like at the time of input is actually included, so that a residual component remains in h (t). Thus, pixels +1 pixels delay output a correction process corresponding to step S5 to S7 in the first embodiment the subtraction circuits 35 and 36 delay the difference signal g _{d1 -} (t) +1 pixel early shift of the pixel early shift difference signal g _{This is} performed using correction data calculated based on _{d1 +} (t) (corresponding to the difference data g _d1- (x) and g _{d1 +} (x) of ± 1 pixel in the first embodiment). The circuit 30 is configured to perform correction using correction data of ± 1 (N = 1) pixels. This is because, as described above, in practice, sufficient accuracy can be obtained even if correction is performed using only the correction data of ± 1 pixel.

The operation of each circuit for realizing the correction processing will be described below. The inner product data N _d1− delayed by +1 pixel output from the integration circuit 38 has been calculated by the following equation (21). _{N d1- = ∫ (n d1- (} t)) dt [t = 0 to t _e] = ∫ (h (t) × g d1- (t)) dt [t = 0 to t _e] ... (21) here, "∫dt 'is integral, shows a [t = 0 to t _e] is an integral range. Also, t = 0 indicates that at the start of input of an input signal, t =
t _e is the time when the input of the input signal is completed. Also, this t =
Between _{0~t e, t 0, t 1} , t 2, ..., signal of each pixel comes is sequentially input for each t _e. For example, h (t)
The _{(t = t 0 ~t 1)} , the first-th pixel components in the period difference signal is _{input, h (t) (t e} -1 ~t e)
Contains the last pixel component in the periodic difference signal (for example, 102
4th pixel component) is input. Also, (t ₂ −
t ₁₎ is a _{= (t 3 -t 2) =} ... = (t e -t e-1). Therefore, equation (21) is equivalent to calculating the inner product of h (x) and g _d1- (x), that is, (h (x), g _d1- (x)). Here, x indicates each pixel described in the first embodiment, and for example, h (x) indicates difference data with respect to the cycle. Similarly, the inner product data N _{d1 +} output from the integrating circuit 44 and which is output by +1 pixel earlier is similarly expressed by h (x) and g
Dot product with _{d1 +} (x), that is, (h (x), g
_{d1 +} (x)).

On the other hand, the square integration data J _d1- delayed by +1 pixel output from the integration circuit 41 has been calculated by the following equation (22). _{J d1- = ∫ (j d1- (} t)) dt [t = 0 to t _{e] = ∫ (g d1- (t)} ) 2 dt [t = 0 to t _e] ... (22) Therefore, formula ( 21) is the sum of the squares of g _d1- (x), that is, the square of the norm of g _d1- (x) (‖g _d1- (x)
‖ ² ) is calculated. Similarly, the square integration data J _{d1 +} output from the integration circuit 47 and which is output by +1 pixel earlier is the square of the norm of g _{d1 +} (x) (‖g
become _{d1 +} (x) || ²⁾ was calculated.

Further, the correlation amount V _d1− delayed by +1 pixel output from the division circuit 39 is calculated by the following equation (23). _Vd1- = _Nd1- / _Jd1- = (h (x), _gd1- (x)) / { _gd1- (x)} ² (23) The +1 pixel output from the division circuit 45 Similarly, for the early correlation amount V _{d1 +} , (h (x), g
_{d1 +} (x)) / {g _{d1 +} (x)} ² was calculated.

Further, +1 output from the multiplication circuit 42
The pixel delay correction signal k _d1- (t) has been calculated by the following equation (24). _kd1- (t) = _{Vd1- gd1-} (t) = (h (t), _gd1- (t)) / { _gd1- (t)} ² * _gd1- (t) (t = 0 to t _e ) (24) Equation (24) is equivalent to the following equation (25). _{k d1- (x) = (h} (x), g d1- (x)) / ‖g d1- (x) || _{^{2 × g d1- (x) ...}} (25) Note that output from the multiplication circuit 48 In the same manner, the calculation represented by the following equation (25) 'has been performed for the correction signal k _{d1 +} (t) which is +1 pixel earlier. _{k d1 + (x) = (} h (x), g d1 + (x)) / ‖g d1 + (x) || _{^{2 × g d1 + (x)}} ... (25) '

Here, (h (x), g _{d1 +}
(X)) / {g _{d1 +} (x)} ² is a modification example of the first embodiment, and is a correlation amount α _n1 of difference data g _{d1 +} (x) for + pixels calculated without performing orthonormalization (described above). Equation (14) "
), And (h (x), g
_{d1 +} (x)) / {g _{d1 +} (x)} ² is also equal to the correlation amount β _n1 of the difference data g _d1- (x) for the _−pixel . That is, the multiplication circuits 42 and 48 output the correction data for ± 1 pixel shown in step S7 according to the modification of the first embodiment.

Then, in the addition / subtraction circuit 49, h
From (t), k _d1− (t) and k _{d1 +} (t) are _calculated from t = 0 to
By subtracting t _e , a signal (a) output from the addition / subtraction circuit 49 is a circuit pattern defect signal.

However, this defect inspection apparatus 20 simply implements the defect detection method described in the first embodiment, and it is considered that the extracted defect signal a (t) still contains an error. So, compared with a predetermined threshold,
It is determined that there is a defect in the portion above the threshold value.

[0102] That is, from the output defect signal a in addition and subtraction circuit 50 (t), the threshold S set by the threshold setting unit 23 subtracts the t = 0 to t _e, equal to or greater than "0" By counting the portion with the counting unit 24,
The number of defects can be detected. It should be noted that the defect signal a (t) indicates the location determined to be defective by the counting unit 24 by the counting unit 2.
4 may be specified from the time input. At this time, the transfer time between each pixel transferred from the input unit 21 (e.g., the time between t ₀ ~t ₁₎ based on, will be determined what is the second pixel. Further, for example, the standard data is sequentially supplied to the defect inspection circuit 30 for all the inspection areas for each processing area and the inspection is performed, or the inspection apparatus 20 is separately provided for each processing area to perform inspection. This can be achieved by detecting defects.

Note that each correction signal (k _d1- (t), k _{d1 +}
(T)) and the periodic difference signal (h (x)) calculated based on the standard signal input at the same timing as the standard signal (g (t)) used to calculate those correction signals. Are input to the addition / subtraction circuit 49 through different calculations, so that they are not synchronized in time. Therefore, the input unit 21 supplies the signal to be processed (g _o (t)) in the same processing area twice, and calculates each correction signal with a standard signal obtained based on the signal to be processed supplied first. , The calculated signal is held, and, on the other hand, by synchronizing each held correction signal with the periodic difference signal calculated by the standard signal obtained based on the signal to be processed next supplied, What is necessary is just to calculate the signal a (t) from which the defect was extracted. Further, even if the same signal to be processed is not supplied twice from the input unit 2, based on each correction signal calculated based on the signal to be processed in the previous processing area and the signal to be processed in the next processing area. Approximate defect signals may be calculated by synchronizing the calculated period difference signals. This is because, since the circuit pattern has periodicity in the X direction, it is considered that the respective periods of two adjacent processing regions are substantially equal. Furthermore, in order to synchronize each signal that is not synchronized in time, a signal output earlier in time may be delayed by a delay circuit to synchronize in time.

As another embodiment, as shown in FIG. 10, a maximum absolute value term selection circuit 51 is provided immediately before an addition / subtraction circuit 49, and a correction signal k _d1- (t) delayed by +1 pixel and a +1 pixel You may be comprised so that any one of the correction | amendment signals _{kd1 +} (t) of an early appearance may be selected. This selection is _{executed by obtaining} the absolute values of the correlation amount V _d1− delayed by +1 pixel and the correlation amount V _{d1 + advanced} +1 pixel by the absolute value circuits 52 and 53, and determining the magnitude by the determination circuit 54. You.

[0105]

As is apparent from the above description, according to the first aspect of the present invention, the periodicity of the circuit pattern is used to
Since the defect is detected by performing data processing using only the data to be processed obtained from the circuit pattern to be inspected, the alignment with the reference data as in the related art is not required. Therefore, since the alignment which requires a long time is not performed, the processing time of the defect inspection processing can be reduced. In addition, since the data can be divided into predetermined processing areas and the respective processing areas can be independently processed, the processing areas can be processed in parallel. Processing time can be further reduced.

According to the second aspect of the present invention, in the fifth processing step of the first aspect, each of the calculated difference data is orthonormalized, thereby enabling more strict correction. More accurate circuit pattern defect inspection is possible.

According to the third aspect of the present invention, in the seventh processing step of the first aspect, a term having the maximum absolute value is obtained from each of the calculated correction data, and only the term is corrected. By using the data as data, practically sufficient accuracy can be provided, and a simple circuit pattern defect inspection can be performed.

According to the fourth aspect of the present invention, since the defect inspection method according to the first aspect of the present invention is simply realized as an apparatus, the processing time of the defect inspection processing can be further reduced. In addition, if the apparatus is configured for each processing area, the defect detection for each processing area can be performed in parallel, so that the inspection processing time can be further reduced.

According to a fifth aspect of the present invention, in the device according to the fourth aspect, the correction difference means is +1 to +1.
The maximum absolute value is calculated from the pixel delay difference data of + N pixels and the pixel early difference data of +1 to + N pixels, and only that data is used as correction data, which is practically sufficient. A simple and accurate circuit pattern defect inspection apparatus can be realized.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating a defect detection procedure performed by an apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a schematic configuration of a circuit pattern defect inspection apparatus used in one embodiment of the present invention.

FIG. 3 is a diagram schematically showing a circuit pattern and its defects.

FIG. 4 is a diagram for explaining a flow of data to be processed.

FIG. 5 is a diagram showing a data flow when data to be processed is represented by binary data.

FIG. 6 is a graph showing data processing of data to be processed in a processing area.

FIG. 7 is a graph showing data processing when there is an error in data to be processed in a processing area.

FIG. 8 is a diagram illustrating an example of a defect detection result.

FIG. 9 is a block diagram illustrating a schematic configuration of a defect inspection apparatus according to a second embodiment of the present invention.

FIG. 10 is a partial block diagram illustrating a modification of the defect inspection apparatus according to the second embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Input part 2 ... A / D converter 3 ... Image memory 4 ... Data processing part 5 ... Printer 6 ... D / A converter 7 ... Monitor 8 ... Control part 11 ... XY stage 12 ... Lens 13 ... Sensor 20 ... Defect Inspection device 21 Input unit 22 Delay instruction unit 23 Threshold setting unit 24 Count unit 30 Defect detection circuit W Wafer P Circuit pattern Q Defect

──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Katsuichi Kitagawa 1-1-1, Sonoyama, Otsu City, Shiga Prefecture Toray Corporation Shiga Works (56) References Hei 1-173172 (JP, A) JP-A-59-192943 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06T 1/00 G01N 21/88 G06T 7/00

Claims (5)

(57) [Claims] 1. A defect inspection method for a circuit pattern for detecting a defect in a predetermined inspection area of a circuit pattern having a periodicity in at least an X direction on an XY plane, comprising: A first processing step of inputting a characteristic of a circuit pattern in the inspection area by a pixel, quantitatively converting a characteristic of each pixel of the input circuit pattern, and creating data to be processed; The data to be processed created by
A second processing step of dividing at least one pixel in the Y direction into a processing area constituted by an arrangement of pixels in the X direction; and a cycle of data to be processed for each processing area divided by the second processing step. A third processing step of calculating each of the obtained periods in terms of the number of pixels; a data to be processed created by the first processing step for each of the processing regions; A fourth processing step of calculating difference data from data shifted by a predetermined integer multiple of the number of pixels corresponding to the cycle calculated by the step, and, for each of the processing regions, created by the first processing step The processed data and the processed data are represented by Z pixels (Z
A fifth processing step of calculating difference data from data shifted in the respective directions by ± 1 to ± N (N is a natural number of a predetermined value), and for each of the processing regions, Sixth processing for calculating the correlation amounts of the difference data with respect to the cycle calculated in the fourth processing step to each difference data for ± 1 to ± N calculated in the fifth processing step, respectively, for ± 1 to ± N And, for each of the processing areas, the difference data for ± 1 to ± N calculated in the fifth processing step, and the correlation amount for ± 1 to ± N calculated in the sixth processing step A seventh processing step of subtracting each correction data obtained by multiplying the difference data from the difference data for the cycle calculated by the fourth processing step, and removing the correction data based on a result of the seventh processing step. Eighth process and defect inspection method of a circuit pattern, comprising the detecting defects serial circuit pattern. 2. The circuit pattern defect inspection method according to claim 1, wherein in the fifth processing step, each of the calculated difference data for ± 1 to ± N is further orthonormalized. Circuit pattern defect inspection method. 3. The defect inspection method for a circuit pattern according to claim 1, wherein, in a seventh processing step, correction data having a maximum absolute value is calculated from the calculated correction data, and the calculated absolute value is calculated. A defect inspection method for a circuit pattern, wherein only the maximum correction data is subtracted from the difference data with respect to the cycle and removed. 4. A defect inspection apparatus for a circuit pattern for detecting a defect in a predetermined inspection area of a circuit pattern having a periodicity in at least the X direction on an XY plane, wherein at least a plurality of the plurality of pixels are arranged in the X direction. Processing data input means for inputting the characteristics of each pixel of the circuit pattern in the inspection area by the pixel to generate the processing data; and a processing comprising at least one pixel in the Y direction and an arrangement of each pixel in the X direction. For each area, the data to be processed in the processing area obtained based on the data to be processed for each pixel being supplied at a fixed time interval from the data to be processed input means in accordance with the arrangement of the pixels in the X direction. (Hereinafter, referred to as standard data), and input the standard data for a time corresponding to a predetermined integer multiple of the number of pixels in the period of the input standard data. A cycle delayed data delayed relative to the difference between the standard data the input,
A synchronous difference calculating means for calculating periodic differential data, and a delay instructing means for instructing the periodic differential means a time corresponding to a predetermined integral multiple of the number of pixels of the standard data. Input the standard data, and add the input standard data to +
1 to + N (where N is a natural number of a predetermined value) each pixel delay data for +1 to + N pixels, which are relatively delayed with respect to the input standard data, for each time corresponding to pixels, and Inputting the standard data, N pixel delay difference means for synchronizing the difference with the standard data and calculating pixel delay difference data for each of the pixel delay data of +1 to + N pixels, +
For each time corresponding to 1 to + N (N is a natural number of a predetermined value) pixels, each of the pixel early-out data for +1 to + N pixels, which is relatively advanced with respect to the input standard data, and N pixel early difference means for synchronizing the difference with the standard data and calculating pixel early difference data for each pixel early data of +1 to + N pixels separately; For each of the pixel advance difference means, the pixel delay difference data calculated by the pixel delay difference means or the pixel advance difference data calculated by the pixel advance difference means, and the periodic difference data calculated by the cycle difference means Are multiplied in synchronization with each other, and +
(2 × N) inner product multiplying means for respectively calculating inner product multiplication data for each pixel delay difference data of 1 to + N pixels and each pixel early difference data of +1 to + N pixels; Inputting the inner product multiplication data calculated by the inner product multiplication means to the inner pixel multiplication data of the last pixel from the start of input of the inner pixel multiplication data of the first pixel for each of the difference means and each of the pixel early difference means. Integrating until completion, each pixel delay difference data of +1 to + N pixels and +1
(2 × N) inner product calculating means for individually calculating inner product data for each pixel early difference data of up to + N pixels; and each of the pixel delay difference means and each pixel early difference device The pixel delay difference data calculated by the delay difference means or the pixel early difference data calculated by the pixel early difference means is squared, and each pixel delay difference data of +1 to + N pixels and each pixel early difference data of +1 to + N pixels are squared. (2 × N) squared multiplying means for individually calculating the squared multiplied data for each of the above, and for each of the pixel delay difference means and each of the pixel early appearance difference means, the square calculated by the squared multiplication means The squared multiplied data is integrated from the start of input of the squared multiplied data of the first pixel to the end of input of the squared multiplied data of the last pixel, and each pixel of +1 to + N pixels Re differential data and +1
(2 × N) square integration calculating means for individually calculating the square integration data for each of the pixel early difference data of up to + N pixels; and for each of the pixel delay difference means and each of the pixel early difference data, The inner product data calculated by the inner product calculating means,
By dividing by the square integration data calculated by the square integration calculation means, each pixel delay difference data of +1 to + N pixels and +
(2 × N) correlation amount calculation means for individually calculating the correlation amount for each pixel early difference data of 1 to + N pixels; and for each of the pixel delay difference unit and each pixel early difference unit, The pixel delay difference data calculated by the pixel delay difference unit or the pixel early difference data calculated by the pixel early difference unit is multiplied by the correlation amount calculated by the correlation amount calculation unit, and each of +1 to + N pixels is calculated. Correction data is calculated for each of the pixel delay difference data and the pixel early difference data of +1 to + N pixels (2 ×
N) correction data calculation means, and from the cycle difference data calculated by the cycle difference means,
All the correction data for each of the pixel delay difference data of +1 to + N pixels and each of the pixel advance difference data of +1 to + N pixels calculated by the correction data calculation means are synchronously drawn to calculate correction difference data. Correction difference means; and defect detection means for comparing the correction difference data calculated by the correction difference means with a predetermined threshold value and detecting the correction difference data larger than the threshold value. A circuit pattern defect inspection apparatus characterized by the above-mentioned. 5. The defect inspection apparatus for a circuit pattern according to claim 4, wherein the correction difference means includes an absolute value from among each of the pixel delay difference data of +1 to + N pixels and each of the pixel advance difference data of +1 to + N pixels. A defect inspection apparatus for a circuit pattern, wherein a maximum value is calculated, and only correction data having the maximum calculated absolute value is used as correction data to calculate correction difference data.