JP3151032B2 - Storage device and its information reading method, information writing method and manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device, and more particularly, to a new storage device using a negative differential diode and a threshold diode as memory cells, and a method of reading information, a method of writing information, and a method thereof. The present invention relates to a method for manufacturing a storage device.

2. Description of the Related Art In recent years, the scale of semiconductor memories has increased, and today, 64 Mb DRAMs (Dynamic Random Access Memories) have been developed.
mory) and the development of a 16 Mb SRAM.
However, the current memory cell structure has a limit in increasing the density, and the development of a new semiconductor memory cell capable of increasing the density is desired.

[0003]

2. Description of the Related Art In general, a memory cell of a DRAM is composed of a capacitor using a junction capacitance of an FET (Field Effect Transister) for storing information and an FET for writing and reading information to and from the capacitor. The SRAM has a flip-flop type memory cell structure and is usually configured using six FETs.

[0004]

As described above, the SRA
The M memory cells require an area of at least six FETs, and there is a limit to miniaturization.

It is an object of the present invention to provide a novel storage device which can be configured with a smaller area with a smaller number of elements, an information reading method, an information writing method, and a manufacturing method of the storage device.

[0006]

In order to solve the above-mentioned problems, the invention according to claim 1 is based on the basic principle of a memory cell as shown in FIG. 1, and comprises a row address signal line (A _x ).
And a column address signal line (A _y1 , A _y1) composed of a pair of signal lines.
_y2 ) and a memory cell provided at the intersection of the row address signal line (A _x ) and the column address signal line (A _y1 , A _y2 ), wherein the memory cell Two elements (D ₁ , D ₂ ) connected in series in the forward direction between the lines (A _y1 , A _y2 ) and having the negative differential characteristic, and the two elements (D ₁ , D ₂ ) Is connected between the connection point (a) and the row address signal line (A _x ), and when a voltage exceeding the positive side and negative side threshold voltages (V _th1 , V _th2 ) is applied, And a threshold diode (D ₃ ) having a characteristic of flowing a current in both positive and negative directions.

The invention according to claim 2 relates to an improvement of an address signal line as shown in FIG. 2, and in the semiconductor memory according to claim 1, the column address signal line (A _y1 ,
A _y2 ), one of the address signal lines (A _y1 )
Are configured as a common ground wiring (GND).

According to a third aspect of the present invention, as shown in FIG. 14, a basic physical structure of a memory cell is shown, and two pairs of signals arranged in parallel with a row address signal wiring layer (Ax) are shown. Column address signal wiring layer consisting of wiring layers (Ay1, Ay2)
And a memory cell layer (MC) formed at the intersection of the row address signal wiring layer (Ax) and the column address signal wiring layer (Ay1, Ay2), and the memory cell layer (MC)
, The between the address signal wiring layer (Ax, Ay1, Ay2), to the row address signal wiring layer (Ax) side, a positive
Corresponding to the threshold voltages (Vth1, Vth2) on the negative side and the negative side
A threshold diode layer (D3) having a characteristic of flowing a current in both positive and negative directions is formed on one surface thereof in electrical contact with the row address signal wiring layer (Ax), and the threshold diode layer (D3) is formed. A negative differential diode layer (D1) is formed in electrical contact between the other surface of the column and one of the column address signal wiring layers (Ay1, Ay2). A negative differential diode layer (D2) is in electrical contact between the other surface of the threshold diode layer (D3) and the other of the column address signal wiring layers (Ay1, Ay2) (Ay2). To form a laminate.

According to a fourth aspect of the present invention, as shown in FIG. 7, the information reading method of the storage device according to the first aspect, wherein the two elements having the negative differential characteristics have two stable points. And the potential of one of the two stable points with reference to the interconnection point of the two elements is the same as the negative threshold voltage of the threshold diode. A voltage is applied to the row address signal line and the pair of column address signal lines so as to be out of a voltage range between the side threshold voltages.

According to a fifth aspect of the present invention, as shown in FIG. 7, there is provided a method of reading a storage device according to the first aspect,
At the time of reading the negative stable point (S ₁ ) of the two operating stable points generated by the elements (D ₁ , D ₂ ) having the negative differential characteristic, the negative threshold of the threshold diode is read. A high-level potential (High) is applied to the row address signal line (A _x ) so that the value voltage becomes higher than the voltage at the negative stable point, and the low-potential side column of the paired column address signal line is applied. A low level potential (Lo) is applied to the address line (A _y1 ).
w), when reading the stable point (S ₂ ) on the positive side of the operation stable point, the threshold voltage on the positive side of the threshold diode is set so that the voltage sequence of the positive stable point is also lowered. , A low-level potential (Low) is applied to the row address signal line (A _x ), and a high-level potential (High) is applied to the higher potential side column address signal line (A _y2 ) of the pair of column address signal lines. It is characterized by the following.

According to a sixth aspect of the present invention, as shown in FIGS. 10 and 11, there is provided a method of reading a memory device according to the first aspect, wherein the elements (D1, D2) having the negative differential characteristic are provided. when reading one of the stable points of the two stable operating points are generated (S1), the high-level potential (high) was added to a row address signal line (Ax), and the column address signal
Both issue lines (Ay1, Ay2) both, or the column address
A low-level potential (Low) is applied to one of the low-potential lines (Ay1) of the signal lines, and when the other stable point (S2) of the operation stable points is read, the row address signal line (Ax) is connected. A low level potential ( Low ) is applied, and both of the column address signal lines (Ay1, Ay2), or both
Any of the higher potential lines (Ay2) among the column address signal lines
A high level potential ( High ) is applied to one of them.

The invention according to claim 7 is as shown in FIG.
2. The information writing method for a storage device according to claim 1,
Thus, the two elements (D₁, D_Two) By two stable
Point (S ₁, S_Two) And one unstable point (S_n) Is generated
And the two elements (D₁,
D_TwoThe potential with respect to the interconnection point (a)
Threshold diode (D_Three) Negative threshold voltage and positive threshold voltage
The row address must be outside the voltage range between the threshold voltages.
Signal line (A_x) And a pair of column address signal lines
(A _y1, A_y2) Is characterized by applying a voltage.

According to an eighth aspect of the present invention, as shown in FIGS. 12 and 13, the writing method of the storage device according to the first aspect, wherein the elements having the negative differential characteristic (D ₁ , D ₂ )
When information is written to the negative stable point (S ₁ ) of the two operation stable points (S ₁ , S ₂ ) and the unstable point (S _n ) generated by the above, the potential of the unstable point (S _n ) (V _sn ) is the threshold voltage (V V) on the positive side of the threshold diode (D ₃ )
_th2 ) to be higher than the row address signal line (A _x ).
And a high-level potential (Hig) is applied to at least one of the column address signal lines (A _y2 ).
h), when information is written to the stable point (S ₂ ) on the positive side of the operation stable point, the potential (V _sn ) of the unstable point (S _n ) becomes negative with respect to the threshold diode (D ₃ ). side of the threshold voltage (V _{th 1)} is lower than the way row address signal line (a _x) to the high-level potential (high) was added, and the low one of the column address signal line (a _y1) It is characterized by applying a level potential (Low).

According to a ninth aspect of the present invention, as shown in FIG. 16, a row address signal line group (A _x1 ,
A _x2 ,...) And the row address signal line group (A _x1 , A _x2,.
), A column address signal line group (A _y11 , A _y12 ,..., A _y21 , A
_y22, ...) and said row address signal line group (A _x1, A _x2,
..) And column address signal line groups (A _y11 , A _y12,.
y21, and supplies a memory cell (MC) of the plurality of claim 1, wherein provided at each intersection, the row address signal line group _{(A x1, A x2, ...} ) in a row address signal of the A _y22) A row address decoder (1) and the column address signal line group (A
_{y11, A y12, ..., A} y21, A y22, ...) to a column address decoder for supplying a column address signal (2), the row address signal line group (A _x1, A _x2 ...) from the respective memory cell ( And a sense circuit (3) for detecting information stored in the memory (MC).

According to a tenth aspect of the present invention, as shown in FIG. 23, the storage device according to the eighth aspect further comprises: a storage unit that detects whether the storage information detected by the sense circuit (3) matches the search target information; A judgment circuit (4) for judging a mismatch or a degree of approximation.

The eleventh aspect of the present invention will be described with reference to FIGS.
11. A method of reading stored information from a storage device according to claim 10, wherein the first method is to provide one of the row address decoder (1) and the column address decoder (2) with search target information. And applying a voltage to the address signal line of the one address decoder corresponding to the data of logic "1" included in the search target information by one of the address decoders to which the search information is given, and A second step of applying a voltage to an address signal line of the other address decoder by an address decoder and detecting storage information output as a result by a sense circuit (3), and one address to which the search information is given The decoder supplies the address signal line of the one address decoder corresponding to the logical "0" data included in the search target information to the address signal line. Simultaneously applying the voltage, applying a voltage to the address signal line of the other address decoder by the other address decoder, and detecting stored information output as a result by the sense circuit (3); A fourth step of determining, by a determination circuit (4), a memory cell column that matches, does not match, or approximates the search target information based on the storage information detected by the sense circuit (3) in the second and third steps; , Is included.

According to a twelfth aspect of the present invention, as shown in FIG. 29, in the information reading method of the storage device according to the eleventh aspect, during the second and third steps, the address signal line of the other address decoder is provided. Is applied sequentially to each of the address signal lines.

According to a thirteenth aspect of the present invention, as shown in FIG. 28, in the information reading method of the storage device according to the eleventh aspect, the second step and the third step are performed for each of the other address lines. It is characterized in that it is performed in one cycle in terms of time.

According to a fourteenth aspect of the present invention, in the information reading method of the storage device according to the eleventh aspect, the determination in the fourth step is performed by a logical determination of data for each address line. .

According to a fifteenth aspect of the present invention, as shown in FIG. 26, in the information reading method of the storage device according to the eleventh aspect, the discrimination in the fourth step is performed by determining a sum of currents flowing through all the address lines. It is characterized in that it is determined and compared by comparing the total current.

FIG. 36 to FIG.
4. The method for manufacturing a semiconductor device according to claim 3, wherein the conductive layer (12), the conductive layer (13), and the threshold diode layer (D) are formed on the insulating substrate (11) by an epitaxial growth method. ₃ (14, 15)), a negative differential diode layer (D ₁ , D ₂ (16, 17, 18)), a conductor layer (19) and a good conductor layer (20) are laminated to form a semiconductor layer (100). A first step of forming the good conductor layer (2
0) A region (a) of the negative differential diodes D ₁ and D ₂ layers via a metal film (201) and an insulating film (202).
Using the mask corresponding to the negative differential diodes D ₁ and D _{1
A second} step of performing _two- layer patterning, and a third step of forming negative differential diode layers (D ₁ , D ₂ ) by semiconductor etching of the patterned semiconductor layer;
After growing the said third distance between the negative differential diode layer D ₁ and D ₂ formed by the process to fill the thickness of the insulating film (204), the threshold diode layer by anisotropic etching fifth forming a fourth step of patterning the (D _3), the threshold diode layer by a semiconductor etching the patterned semiconductor layer (D ₃₎
And then growing an insulating film (205) over the entire semiconductor layer, removing only the insulating film (205) existing in the laminating direction of the semiconductor layers by anisotropic etching, and removing the row address signal line layer (A _x1). , A _x2 ...)
, A seventh step of forming a row address signal line layer (A _x1 , A _x2 ...) On the patterned semiconductor layer by semiconductor etching, and a negative differentiation diode layer (D
₁ , D ₂ ) on the column address signal line layers (A _y11 , A _y12 ,
, A _y21 , A _y22 ,...).

[0022]

According to the first aspect of the present invention, a bistable state is realized by the characteristics of the two differentially connected negative diodes D ₁ and D ₂ . Be given to a row address signal line A _x and the column address signal line A _x1, A _x2 respectively voltage signals separately, to never break the bistable state, also it does not exist the current through the threshold diode D _3. However, when a predetermined voltage signal is simultaneously applied to each of the address signal lines A _x , A _y1 , A _y2, a current flowing through the threshold diode D ₃ is generated according to a stable state, that is, a storage state. In addition, it is possible to switch the stable state to another stable state. That is, when this circuit is arranged vertically and horizontally in parallel as a memory cell, a memory device capable of selectively writing and reading information only to a specific memory cell is configured. can do.

According to the second aspect of the present invention, by providing the common ground line GND, the address signal line can be shared, and since the signal line becomes thicker, a memory resistant to power supply noise can be realized. Becomes possible.

According to the third aspect of the present invention, a stacked memory is provided between a row address signal wiring layer (A _x ) and a pair of column address signal wiring layers (A _y1 , A _y2 ) crossing each other. A cell can be formed, and the memory cell can be realized by the sum of the area of two diodes and the area of a gap for separating the two diodes. Further, by arranging the row address signal line LX and the column address signal lines LY ₁ and LY _{2 so as} to intersect and arranging the three diodes therebetween, an area other than the memory cell arrangement is not required, That is, memory cells can be arranged at high density without requiring an area other than the memory cell itself and the gap between the memory cells.

According to the present invention, there are two stable points S ₁ , S _{2 in} an arbitrary combination of address signals.
Can read and write arbitrary storage information.

According to the ninth aspect of the present invention, the memory cell according to the first aspect is arranged at each intersection of the address signal lines arranged in a matrix in the matrix direction, and is selected by a row decoder and a column decoder. The stored information can be written to a specific memory cell to be read, and the stored information can be read through the sense circuit. That is, by integrating each element of the present invention, it is possible to realize a higher density SRAM.

According to the tenth aspect of the present invention, by supplying a row address signal or a column address signal corresponding to the information to be searched, storage information that matches, does not match, or approximates the address signal is stored in the memory cell.
One is arbitrarily or selectively can be retrieved from the stable point S _2, to allow implementation of associative memory that enables retrieval faster.

According to the invention described in claims 11 to 15,
It is possible to provide a reading method capable of driving the storage device according to claim 10 more effectively as an associative memory.

According to the sixteenth aspect of the present invention, since the use of the mask can be suppressed by utilizing the sidewall, the self-alignment process can be realized.

[0030]

Next, a preferred embodiment of the present invention will be described with reference to the drawings. [I] Memory Cell (i) Circuit Configuration of Memory Cell As shown in FIG. 1, the row address signal line A is arranged in the row direction (X).
_x , and two pairs of column address signal lines A _y1 and column address signal lines A _y2 are provided in a non-contact manner across the row address signal lines A _x . As shown, two negative differentiating diodes D ₁ and D ₂ are connected in series between the column address signal line A _y1 and the column address signal line A _y2 . Negative differentiating diode D ₁ and negative differentiating diode D ₂
Is connected to a threshold diode D ₃ is provided between the connection point a and the row address signal line A _x with. These negative differential diodes D ₁ and D ₂ and threshold diode D ₃ constitute a memory cell.

FIG. 2 shows an example in which one of the column address lines _Ay1 is used as the ground potential GND to share the column address line _Ay1 . (Ii) Operation principle of the memory cell FIG. 3 shows the current-voltage characteristics of the N-type negative differential diode.
As the N-type negative differential diode, for example, there are an Esaki diode and a resonance tunnel diode. The peak current I _p , the valley current I _v , the rise voltage is V _th , the peak voltage is V _p , the valley voltage is V _v , and the voltage at which the current flows again and the same current as the peak current flows is V
Defined as _p2 . (At this time, assuming that a resonant tunneling diode is used as the negative differential diode, V _p −V _th > V _v −V
_Although it is _p , it is easy to see that the essence of the following description does not change even if it is not the same, only by considering different voltages. In some structures, the rise of the post-valley current is small and does not reach the same level as the peak current. In this case, V _p2 is assumed to be infinite. FIG. 5 shows the current-voltage characteristics of the threshold diode.
A current suddenly flows in a region of a voltage lower than the threshold value V _{th1 and} a voltage higher than the threshold value V _th2 .

Here, the threshold voltages V _th1 and V _th2 of the threshold diode D ₃ and the valley voltages V _v of the negative differential diodes D ₁ and D ₂ are in a relationship of | V _th1 −V _th2 |> V _v Having.

As shown in FIG. 4 (a), two N-type negative differentiating diodes D ₁ and D ₂ (the characteristics of both diodes are assumed to be the same for easy understanding of the description) are connected in series. bonded though not towards terminal to a column address signal line a _y1 of (D ₁ side) for connecting the column address signal line a _y2 (D ₂ side). In FIG. 4B, the vertical axis represents diodes D ₁ , D
_{2 The} current I flowing through each of them, the horizontal axis is diodes D ₁ , D
₂ shows a voltage with reference to a connection point a with ₂ . Diode D
₁ shows the characteristics of the N-shape as the potential at point a becomes higher, the diode D ₂ shows the characteristics of the N-shape as the potential at point a becomes lower than V _a. As you apply a voltage between the two address signal lines, while the applied voltage is up to 2V _p is one stable point (Figure 4 (b)). However, when a higher voltage is applied, two stable points are obtained (FIG. 4).
(C)). This could voltage the voltage applied to the D ₁ is applied to the D ₂ less than the peak voltage is higher than the valley voltage, since there are two states of reverse, this state is that it is stable. Therefore, it can be stored in which of these two states.

To use the circuit unit shown in FIG. 4 as a memory cell, as shown in FIG. 1, a junction point a of two negative differential diodes D ₁ and D ₂ connected in series and another row address signal line A connecting the threshold diode D ₃ between the _x.
Here, A _x corresponds to a bit line, and A _y1 and A _y2 correspond to a word line pair.

Next, FIG. 6 shows conditions for the memory cell shown in FIG. 1 to store information, FIG. 7 shows conditions for reading the information stored in the memory cell, and FIG. 8 are shown in FIG.

In FIGS. 6, 7, and 8, the column address signal line A
_y1, a column address signal line A _y2, when defining the potential of the row address signal line A _x, with respect to the potential of the junction point a, the diode D
₁ is a diagram showing what kind of current flows through the D _2, D _3. The positive direction of D ₁ is the current flowing from the contact a to A _y1 direction, D _2, D ₃ and D ₂ + D ₃ in the positive direction is the contact a
Represents the current flowing into the Therefore, D ₁ and D ₂
+ Intersection of line D ₃ is the operation point.

FIG. 6 shows how to retain the memory of the cell.
So, two stable points S₁, S_TwoExists and then
D_ThreeA so that no current flows through_x1, A_y1, A_y2Each potential
Must be applied. Also, the stable point S₁Write information to
FIG. 7 (a) shows whether or not the
Thus, there are two stable points, and the stable point S₁Information is written
D when it's busy_ThreeCurrent flows at the stable point S
₁When no information is written to the_TwoInformation is written on the side
Sometimes D)_ThreeTo prevent current from flowing through
A_x, A_y1, A_y2It is necessary to apply each potential to. Further
Stable point S₁As shown in FIG. 8 (b),
As shown, the stable point is S_TwoA so that there is only_x1,
A_y1, A_y2Need to be applied to each of them.
Furthermore, the stable point S _TwoWhether information is written to
In order to read out, as shown in FIG.
Point exists, S_TwoD when no information is written to_Three
No current flows through the_TwoWhen information is written to
Is so that the current flows_x, A_y1, A_y2Mark each potential on
Need to be added. On the other hand, S₁To write information to
As shown in FIG. 8A, the stable point is S₁So that there is only
A_x, A_y1, A_y2Need to be applied.

(Iii) Storage and readout of information At the time of storage, it is necessary to be in the state shown in FIG. 6 as described above.
In addition, since the power consumption is suppressed when the current does not flow as much as possible, it is desirable that the two stable points are in the valley. FIG. 9 shows this. In FIG. 9, a characteristic in which the threshold value is symmetrical between + and − is considered. However, when the threshold value is different, an offset that sets the intermediate potential to 0 may be considered. Further, the characteristics of the threshold diode are not sharply raised as used in the above description so as to be close to the characteristics of the threshold diode, but the essence is the same. The same applies to the following figures.

In the read operation, only the memory cells at the intersection of a certain row address signal line _Ax and a certain row address signal line _Ay among the memory cells arranged in a matrix must be read. and when applying a signal only to the row address signal line a _x, when only plus signals to the row address signal line a _y is in the state of FIG. 6, FIG. 7 (a), the or when both plus signal ( It must be in the state of b). Here, adding a signal means changing the potential of the address signal line. At this time, if the threshold value differs between + and-, it is sufficient to consider an offset for setting the intermediate potential to 0 in the following description. Therefore, a symmetric characteristic is considered in the description.

S₁In the reading of, as shown in FIG.
The row address signal line A_xHigh, column address signal
Line A_y1Is added Low. A_xHigh signal
When applied, the threshold diode D_ThreeThe characteristics of FIG.
As shown in FIG._Ax+ V_th1Potential of
Goes up. On the other hand, V_Ay1Is set to Low, FIG.
D as in (b)₁Characteristic shifts to the left and V_s1No electricity
The rank goes down. The magnitude of the signal at that time is A_xOr A_y1Horse
If only one of them is still V_Ax+ V_th1<V_s1Sand
In the state of FIG. 6, when both are added, A_x+ V_th1
> V_s1That is, it is determined that the state shown in FIG.
If both row address signal lines A_xAnd column address signal line A
_y1Only the memory cell located at the cross point of is selected
The information is read out. like this
In FIG. 10, (a) shows the row address signal line A _xOnly in
(B) shows the column address signal line A when High is applied._y1
(C) shows the row address signal line when only
A_xHigh, column address signal line A_y1Add Low to
Shows when.

[0041] In the read S _2, as shown in FIG. 11, the row address signal line A _x Low, the column address signal line A _y2 added High. The row address signal line A _x and a column address signal line A _y2 when nothing, and it is in a state of A _x + V _th2> V _s2 i.e. 6 because it is maintained state. When the row address signal line A _x in Low, 11
As shown in (a), the characteristic of D ₃ shifts to the left and A _x +
The potential of V _th2 drops. On the other hand, when V _{Ay2 is set} to High, the characteristic of D ₂ shifts to the right and the potential of V _s2 increases.
In this case, the magnitude of the signal is still A _x + V when only one of the row address signal line A _x or the column address signal line A _y2 is used.
_th2> V located _s2 i.e. the state of FIG. 6, be determined when both were added so that the state of the A _x + V _th2 <V _s2 i.e. FIG. 7 (b), the both of the row address signal lines A _x column address so that the only memory cells that cross the signal lines a _y2 is read out. In this way 11, when the plus High only when (a) was added Low only the row address signal line A _x, the column address signal line A _y2 is (b),
(C) indicates a time obtained by adding a High to a row address signal line A _x Low, the column address signal line A _y2.

For reading S ₁ , (A _x : Hi)
gh, A _y1 : Low) instead of (A _x : High,
A _y1 , A _y2 : Low) and reading of S ₂ are as follows.
_{(A x: Low, A y2} : High) instead of,
_{(A x: Low, A y1} , A y2: High) can potential set so as to satisfy the above conditions a combination of.

In the above description, the initial state of the reading operation is the same as the holding state. (This is due to the fact that the holding state is usually designed to minimize power consumption and that there is no need to set another potential.) However, since the above conditions only need to be satisfied, the initial state Need not be the same as the holding state.

(V) Writing of Information The writing operation is performed by a row address signal _Ax and a row address signal line _Ay among the memory cells arranged in a matrix.
Because of must be only written memory cells at the cross, and when only plus signals to the row address signal line A _x, when applying a signal only to the row address signal line A _y is 6 or FIG. In the state 7 (a) or (b), when signals are applied to both, the state must be as shown in FIGS. 8 (a) and 8 (b). Here, adding a signal means changing the potential of the address signal line. At this time, if the threshold value differs between + and-, it is sufficient to consider an offset for setting the intermediate potential to 0 in the following description. Therefore, a symmetric characteristic is considered in the description.

[0045] In the writing of S _1, to the use shown in FIG. 12, the row address signal line A _x Low, added High to the column address signal line A _y2. Here, S ₂ shown in FIG.
Also, in the case of reading, A _x = High, and a potential having the same polarity as the writing of S ₁ is applied. However,
11 and 12 differ in the magnitude of the applied potential. That is, in the case of writing, as shown in FIG.
Instability point When S _n V _Ax + V _th2 <so as to satisfy V _sn A _x, but a voltage is applied to the A _y2, in the case of the read _{S 2, V Ax + V th2} > voltage so as to satisfy V _sn It should be noted that By the way, when nothing is added to A _x and A _y2 , it is in the state of FIG. 6 since it is in the holding state. Or to some extent A _x is low and A _y2 is high
The state shown in FIG. 7B in which the voltage h is applied may be used. From the holding state to the Low row address signal lines A _x, characteristics of D ₃ as shown in FIG. 12 (a) is shifted to the left,
The potential of A _x + V _th2 decreases. On the other hand, when the V _y2 High, the shift characteristics of the D ₂ is to the right as in FIG. 12 (b), the potential of V ₂ increases. The magnitude of the signal at that time is
In the case of only one of them, V _Ax + V _th2 > V _sn is still in the state of FIG. 6 or FIG. 7B, and when both are added, V _Ax + V _th <V _sn , in the state of FIG. , Both row address signal lines A _x , A _y
Has only _one stable point S ₁ and the stable point has the same property as S ₁ because the voltage applied to D ₁ is lower than the peak. Be returned to the holding state of the source both address signal lines, a stable point because the S _1, can be written S _1. Thus, FIG.
So when the plus Low only (a) the row address signal lines A _x, only the column address signal lines A _y2 (b) Hig
when the addition of h, (c) is a row address signal line A _x Lo
w, when High is applied to the column address signal line A _y2 .

S_TwoIs written as shown in FIG.
The row address signal line A_xHigh, column address signal
Line A_y1Add Low. Row address signal line A_xas well as
Column address signal line A_y1When not adding anything
In the state shown in FIG. Or row address signal
Line A_xHigh, column address signal line A_y1Low
The state shown in FIG. 7B in which a certain amount of voltage is applied cannot be achieved. line
Address signal line A_xIs Low, FIG. 13A shows
D as shown_ThreeCharacteristic shifts to the right and V_Ax+ V _th1of
Potential rises. On the other hand, V_y1Is set to Low, FIG. 13
D as shown in (b)₁Characteristic shifts to the left, V_S1
Potential drops. The magnitude of the signal at that time is determined by the row address.
Signal line A_xOr column address signal line A_y1If only one of
In the state of FIG. 6 or FIG.
When added, S_n<V_Ax+ V_th1And the stable point is S
_TwoRow address signal line A_xAnd column address signal
Line A_y1Only the memory cells that cross each other have one stable point.
And its stable point is D_TwoVoltage applied to
S because it is low_TwoOf the same nature as Both sides
If the original state of the dress signal line is restored, the stable point becomes S_TwoWhen
So S_TwoCan be written. Thus, FIG.
(A) shows the row address signal line A_xAdd High only to
(B) shows the column address signal line A_y1Just Low
(C) shows the row address signal line A_xTo High,
Column address signal line A_y1Shows when Low is added to
You.

S₁(A)_x: Lo
w, A_y2: (High) instead of (A)_x: Low, A
_y1, A_y2: High), (A_x: Low, A_y1: Hig
h), only X and Y alone are A_x+ V
_th2<V_snA if you work both _x+ V_th2<V_snThe condition
Potential can be set to satisfy.

For writing S ₂ , (A _x : Hi
gh, A _y1 : Low, instead of (A _x : High, A
_{y1, A y2: Low),} (A x: High, A y2: Lo
w), A _x + V with only X and only Y
_th1 <V _sn, in both A _x + V _{th 1>} can be a potential set so as to satisfy the condition of V _sn.

In the above description, the initial state of the writing operation is the same as the holding state. (This is due to the fact that the holding state usually minimizes power consumption and that there is no need to set another potential.) However, since the above conditions only need to be satisfied, the initial state Need not be the same as the holding state.

(Vi) Physical Structure of Memory Cell FIG. 14 shows a three-dimensional structure of the memory cell. As shown in FIG. 14, the row address signal wiring layer A _x is disposed, the column address signal wiring layer A _y1, A _y2 is disposed consisting of parallel signal wiring layer with two pair to cross the row address the intersection of the signal wiring layer a _x column address signal wiring layer a _y1, a _y2 memory cell layer MC is formed.

The memory cell layer MC has a characteristic that a current flows between the address signal wiring layers A _x , A _y1 and A _y2 at predetermined threshold voltages V _th1 and V _{th2 toward} the row address signal wiring layer A _x. threshold diode layer D ₃ is formed in electrical contact with the row address signal wiring layer a _x in one surface thereof, the other face of the threshold diode layer D ₃ column address signal wiring layer a _y1 having, negative differential diode layer D ₁ between one of the wiring layers a _y1 of a _y2 is formed in electrical contact and the other surface of said threshold diode layer D ₃ and the column address signal negative differential diode layer D ₂ is formed in layers in electrical contact between the other wiring layers a _y2 of the wiring layer a _y1, a _y2.

FIG. 15A shows a sectional structure of a semiconductor layer (resonant tunnel diode) 100 of a memory cell. As shown in the figure, a semi-insulating or insulating substrate (SI, Ga
As) 11, a good conductor layer (n ⁺⁺ GaAs) 12,
Conductive layer (n ⁺ GaAs) 13, threshold diode D ₃
Layer (i-AlGaAs) 14, conductor layer (n ⁺ -GaAs)
s) 15, negative differential diode D _1, i-AlAs layer 16 to form the D ₂ layer, i-GaAs layer 17, i-Ala
The s layer 18, the conductor layer (n ⁺ -GaAs) 19, and the good conductor layer (n ⁺⁺ GaAs) 20 are formed in a laminated shape.

FIG. 15B is an energy band diagram of the resonant tunnel diode in FIG. Note that by that must be noted, as is apparent from FIG. 14, D ₁ and the direction of current flow in the same layer configuration with the D ₂ is that it is reversed. Therefore, in manufacturing the memory cell, D ₁ and D ₂ show the negative differential characteristics so that the tunnel barrier layers 16 and 18 and the quantum well layer 17 show the same regardless of the current flowing from the top to the bottom or the bottom to the top. It is necessary to select the material film pressure appropriately.

[II] SRAM FIG. 16 shows an SRA constructed using the memory cells of FIG.
An example of M is disclosed. As shown in FIG. 16, row address signal line groups A _{x1 to} A _x5 are arranged in the row direction, and a pair of two pairs each of which intersects row address signal line group LX in a non-contact manner. Column address signal line groups A _{y11 to} A _y52 are arranged. At each of the intersections, a memory cell MC including negative differential diodes D ₁ and D ₂ and a threshold diode D ₃ is formed. Each memory cell MC is shown in FIG.
The description will be referred to since it has the configuration shown in FIG.

Row address signal line group A_xAt one end of the line
Decodes the row address data and responds to the data content
Row address decoder 1 for applying the
Have been. Row address signal line group A_xAt the other end of the line
Represents each column address signal line A_x1~ A _x5Detect current flowing through
Sense circuit 3 for reading information in memory cell MC
Is connected.

[0056] the line end of the column address signal line group A _x is a column address decoder 2 for applying a voltage corresponding to the data contents by decoding the column address data are connected. Writing of data to the memory cell MC is performed by supplying necessary row address data and column address data to the row address decoder 1 and the column address decoder 2 to select an address to be stored. Row address signal lines A _x and the column address signal line A _y1 in each memory cell MC, and shown in FIGS. 13 and related description for operation during mode and write voltage application to the column address signal line A _y2 Therefore, the description is omitted.

Reading of data from the memory cell MC is performed as follows.
Necessary row address data and column address data are supplied to row address decoder 1 and column address decoder 2 to select a read address, and a row address signal line A
_This is performed by detecting the current appearing at _{x1 to Ax5} by the sense amplifier 3.

As described above, since each memory cell MC has address selectivity, data can be written to or read from the memory cell MC at an arbitrary address. FIG. 17 shows an SRAM using the memory cell shown in FIG.
FIG. 3 shows a circuit diagram in the case of configuring. As can be seen from FIG. 17, one of the column address signal lines A _y11 , A _y11
Ay51 ,... _Ay51 may be connected to GND and commonly connected to the ground potential.

FIG. 18 shows an example of the three-dimensional structure of the SRAM. Figure
As shown in FIG. 18, the row address signal line layer A_x1~ A_x4But
Are formed in the row direction in parallel with the row address signal.
Wire layer A_x1~ A_x4Crosses at a predetermined interval δ between
Column address signal line layer A in the direction _y11~ A_y22Are parallel to each other
Is formed.

On each row address signal line layer A _{x1 to} A _x4 , a pair of column address signal line layers (A _y11 and A _y12 , or A _y11
y21 and thresholds diode layer D ₃ having a length of distance across the A _y22) is formed. In electrical contact with the one surface of the threshold diode layer D ₃ and the row address signal line A _x. Moreover, the negative differential diode layer D ₂ is interposed between the other surface of the one end side and the column address signal line A _{y n2} threshold diode layer D _3, the threshold diode layer D ₃ of the other side It is interposed negative differential diode layer D ₁ between the other end and a column address signal line a _{y n1,} negative differential diode layer D ₂ column address signal line a _{y n2,} negative differential diode layer D It is electrically connected by the contact hole CH and ₁ column address signal line a _{y n1.}

[0061] Thus, the row address signal line A _x column negative differential as sandwiched both lines at the intersection of the address signal line A _y diodes D _1, D ₂ to each other crossing the threshold since the formation of the value diode D ₃ in layers, FIG. 20
As shown in (1), one memory cell MC can be formed with an area of about two negative differential diodes, and high density can be achieved.

FIG. 19 is a plan view of the SRAM shown in FIG. FIG. 20 is a diagram showing the state of FIG. 17 using the memo cell of FIG.
FIG. 2 is a perspective view showing a three-dimensional structure of a RAM. FIG. 21 is a plan layout view thereof. In FIG. 20, A _x11 and A _{x21 of} FIG.
Are commonly connected to the GND wiring.

[0063] Figure 22 is a SRAM basically the same structure shown in FIG. 20, an example of forming the width of the threshold diode D ₃ to the same width as the negative differential diode D _1, D _2. [III] Associative memory FIGS. 23 to 28 show an embodiment of an associative memory using the memory cell of FIG. Recently, devices have been devised to provide the storage element itself with an intelligence function. For example, in pattern recognition or the like, there is a so-called associative memory that compares a pattern stored in a storage element with an input pattern and outputs the closest pattern.

As conventional associative memory elements, there are an associative memory element in which a storage portion and a comparison portion are independently provided, and an associative memory element in which a comparison circuit is provided for each memory cell. In the former case, it takes time to exchange data between the comparison circuit and the storage circuit. In the latter case, the area of the memory cell increases, and the degree of integration does not increase. There is a demand for associative memory elements to read out necessary information as quickly as possible from among as much information as possible. However, no device was satisfactory in speed and integration degree.

The biggest reason why the degree of integration does not increase is that DRA
In both the M and the SRAM, the conventional storage element only determines which information of 0 or 1 is stored in each memory cell, and has no function of comparing with the input information. Circuit had to be added. The comparison circuit is a so-called exclusive OR circuit, and it has been quite difficult to realize it with a small number of elements.

However, according to the present invention, the memory cell MC has a comparison function in the memory cell itself, as will be described later, and the row address signal line A _x , the column address signal line A _y1 , the column address signal By changing the signal applied to the line A _y2 , the storage information corresponding to the search target information can be selectively output, and the memory cell can be realized with an area of about two diodes. A speed associative memory element can be realized.

That is, as shown in FIG. 10, in order to read whether or not information has been written to the stable point S ₁ in a specific memory cell, A _{x of the} selected memory cell is read.
The High, the A _y1 to Low, the current flows into the D ₃ if information S ₁ is written, when the information on S ₁ is not written no current flows to the D _3. Further, as also shown in FIG. 11 to read whether the information in a stable point S ₂ is written, the read want memory cell A _x
Is set to Low and A _{y2 is set} to High.

Here, when the stable point S _{1 is associated} with the information “0” and the stable point S _{2 is associated} with the information “1”, the decoder determines whether or not the memory cell has the information “0”. , And whether or not it has the information "1", and the MC can output the answer to each of the above. This means that the MC has a function of comparing the comparison information held by the decoder with the information stored in the MC itself. On the other hand, in the case of the conventional PRAM and SRAM, the decoder has only the function of selecting the memory cell to be read, and unless the information held by the memory cell is taken out of the memory cell area,
It is not possible to check whether the information of the comparison target and the information of the MC match.

Next, the structure of the associative memory of the present invention will be described. First, as shown in FIG. 23, the configuration of the memory cell of the associative memory itself is the same as that of the first embodiment (FIG. 1), and the configuration of the entire device is the same as the configuration shown in FIG. 3 is provided with a judgment circuit 4 for judging whether or not the stored information detected by step 3 matches the search target information or the degree of approximation. However, an important point in order to function as an associative memory is that the polarity of an address signal applied by the memory cell MC to the row address signal line A _x and the column address signal line A _yi for the information stored in the memory cell MC ( Or the potential difference) has the characteristic that it can be read only when it is changed in a predetermined direction (positive or negative). In other words, even when accessing the same memory cell, A _x : High and A _y1 :
When it is set to Low, and A _x : Low, A as shown in FIG.
_{When y2 is} High, the memory of the present invention has the characteristic that the output from the MC is different.

Next, a function for functioning as an associative memory is described.
The reading method will be described. Now, threshold
Do D_ThreeIs the row address signal line A_xThe negative differential diode
D₁, D_TwoIs the column address signal line A_yiIs also connected
And The stable point is S ₁Is stored as information "0"
State, S_TwoIs a state in which information “1” is stored.

[0071] (A) where, in order to omit the illustration in FIGS. 23 30, the column address lines A _y1i, A _y2i
... A _y5i is shown. Here, i = 1 or 2, so, for example, when the column address line _rises positively, A _y1i → A _y12 is read and the negative differential diode D ₂ is read.
Means that the potential of the column address line A _y12 connected to is set to a high state. Further, when pulled down the column address lines to the negative, A _y1i → A _{y1 1} and reading, negative differential diode D
_This means that the potential of the column address line _Ay11 connected to ₁ is set to the low state. Hereinafter, other column address lines A _y2i ,
The same _{applies to} the notation of A _y3i ... A _y5i .

When a series of data for pattern recognition is stored in a memory cell connected to a common row address signal line _Ax (FIG. 23). FIG. 23 shows a state in which memory cells of 5 rows × 5 digits store information of “0” or “1”, respectively. This memory cell is specifically 5
Memorize two data. That is, DATA on A _x1
1 (10110), DATA ₂ (01101), A on A _x2
DATA ₃ (11111) on _x3 , DATA ₄ (010 on A _x4
01) and DATA ₅ (11000) on _Ax5 . The associative memory can be determined whether the search target information, for example (10010) is most similar to any of the information DATA ₁ ~DATA _5. Hereinafter, a method of the determination will be described. <1> First method (see FIG. 24) First, in step 1, search target information (10010)
Of the, to find whether or not the first digit of "1" and the fourth digit of the "1" data DATA ₁ ~DATA ₅ each have.
In this case, A to memory cells selected because it is read stable point _{S 2 x: Low, A y} : when a High, it is checked whether the output current is output.

First, all of V _{Ax1 to} V _Ax5 are set to Low.
Next, _{assuming that} only V _Ay1 is High at the time, five memory cells on the column address signal line A _y1 are selected, and when information “1” is written in each memory cell, each memory cell is output current flows to the sense circuit 3 via a corresponding row address signal lines a _x. In this example, since current flows through A _x1 , A _x3 and A _x5 , the data
The first digit of DATA ₁ , DATA ₃ , and DATA ₅ is “1”, which indicates that it matches the first digit of the search target information. Next, V
To Low only A _ya the time in a state in which the _ax1 ~V _Ax5 kept at Low. At this time, since a current flows through A _x1 and A _x3 , the fourth digit of data DATA ₁ and DATA _{3 is} the fourth digit of the search target information.
It can be seen that it matches the digit.

Next, in step 2, the search target information (1
"0010" in the second, third and fifth digits of the data
₁~ DATA_FiveTo find out if you have. This place
If stable point S₁Memory to select
A for the cell_x: High, A_y: Apply Low
And check whether the output current flows from each memory cell.
Just do it. During step 2, V_Ax1~ V_Ax5Is Hi
gh, and in this state the column address signal
Line A_y2If only Low is set, data DATA₁~ DATA _Fiveof
Row address corresponding to data whose second digit information is 0
Signal line A_x(In this case, A_x1Only).
Similarly, for the 3rd and 5th digits of the search target information,
₁~ DATA_FiveCan be checked for a match or mismatch.

At the time in step 1 and the time in step 2, nothing is checked with respect to the data stored in the memory. As described above, in this method, there is a time when no search is performed.
Row address signal line A
_The voltage applied to _x can be fixed.

[0076] then calculated matching degree between the search target information and the data DATA ₁ to Data ₅ in step 3. That is,
Regarding the data DATA ₁ , two pulse currents indicating the coincidence in step 1 and two pulse currents indicating the coincidence in step 2 are output, so that it is understood that up to four digits of the five-digit information match the search target information. . Remaining data DATA _{2 to} DA
It can be seen that the degrees of coincidence for TA ₅ are also 0, 2, 1, and 3, respectively. And, from this result, five data DATA
Of ₁ to Data _5, the data DATA ₁ is clear that similar to the search target information.

Finally, as shown in step 4, the specific contents of the information of the data DATA ₁ closest to the search target information are output. In this case, when _{Ax1 is set} to Low and each row address signal line _{Ay is set} to High sequentially, for example, at the time, it is searched whether or not the memory cell at the upper left of FIG. 24 has "1" information. Memory cell is "1"
, And outputs a current to A _x1 . In the same manner, finally, information of data DATA ₁ (10110)
Is output. <2> In the second method (see FIG. 26) Step 1, of the data DATA ₁ to Data _5, 1 digit and the fourth digit is looking for those "1". That is, A
all _x1 to A _x5 and Low, further Hig the A _y1 and A _y4
h. At this time, a total of 10 cells of five memory cells on five memory cells and A _y4 on A _y1 are simultaneously selected, for example, a one-numbered memory cells from the top of the A _x1 4
Since th cell information with regard to "1" is stored, the current magnitude of 2I to A _{x1 0} is output.
On the other hand, one second from the top of the A _x5 and fourth As for the memory cell information "1" stored in that since only one of the first memory cell on A _x5 half in the case of I ₀ (A _x1 ) Current flows. As described above, data DATA _{1 to} DA
It can be seen that the degree of coincidence of “1” with the search target information of TA ₅ is 2,0,2,0,1 respectively.

In the next step 2, data DATA _{1 to} DATA ₅
Of the second, third and fifth digits are "0".
At this time, A _{x1 to} A _x5 : High, A _y1 , A _y3 , A _y5 are L
ow, five memory cells on A _y2 , five memory cells on A _y3 , and five memory cells on A _y5 are simultaneously selected, and the coincidence is checked with “0”. Result is data DA
Since the _{first and} second digits of TA ₁ are _0, a current of 2I ₀ flows through A _x1 , and the data DATA ₂ does not flow through A _x2 because all the _second , third, and fifth digits are not zero. Hereinafter, A _x3 , A _x4 , and A _x5 are 0, I ₀ , and 2I ₀ .

Next, at step 3, each of the data DATA ₁ to DATA
The degree of matching between DATA ₅ and the search target information is checked. In this case, the coincidence of the data DATA ₁ is A _x1
2I flowing in A _x1 when the of 2I ₀ and Step 2 flowing
By adding ₀ , it is found that it is 4. Hereinafter, the same applies for the data DATA ₂ ~DATA _5.

Finally, in step 4, the content of the information of the data DATA ₁ most similar to the information to be searched is output. <3> Third Method (see FIG. 25) In the first and second methods, the matching degree of the search target information for “1” and the matching degree for “0” are checked in different steps. In the method 3, the matching degree for “1” and the matching degree for “0” are searched simultaneously in step 1.

That is, each time of FIG.
A_x1~ A_x5Are high and low, respectively.
With a bell. And at time A_y1Is High
Then A_y1Of the five selected memory cells above
From the memory cell storing the information "1",
A to respond_x1~ A_x5Output current. In this case A_y1Up
Of the first, third and fifth memory cells from the left
So A_x1, A_x3And A _x5Current flows through Next time
At A_y2When is set to Low, A_y2Top 5 Selected
Of the memory cells that store information "0"
From the recell, the corresponding A_x1~ A_x5Output current
Is done. In this case A_x1Only the current is output. As well
The third digit of the search target information (10010) is "0".
At time A_y3Is Low and data DATA₁~ DATA_Fiveof
From among them, search for the one whose third digit is “0”.

Next, as can be seen from current I in FIG. 25, the direction of current flow is reversed depending on whether the information stored in the memory cell is "1" or "0". Is a bipolar pulse. Therefore, in step 2, curren
t I is converted into a unipolar pulse current I ′. Here, in Current I ′, the number 4 of pulses appearing in A _x1 represents the degree of coincidence of data DATA _{1 with} the search target information. Therefore, this curre
From nt I ′, it can be seen that DATA ₁ among the data DATA ₁ to DATA ₅ is most similar to the search target information.

Finally, in step 3, the most
Data similar to search target information ₁Output the contents of
I have. FIG. 27 clearly shows the data in comparison with FIG.
Data₁~ DATA_FiveAre each advanced in the horizontal direction.
ing. That is, data DATA₁~ DATA_FiveAre (10
101) (01111) (11100) (10100)
(01110), and these data and search target information
(00111) and the most of the five data
Associative memory for selecting data similar to search target information
It is a block diagram of. In the case of the configuration of FIG.
The first method and the third method are also applicable to this example.
It is possible to apply the second method to this configuration.
Can not. This is the data column direction (horizontal
Direction, A_yDirection), there is no current sensing circuit.
Cause.

FIG. 28 shows a fourth method for the associative memory having the configuration shown in FIG. 27, and corresponds to the third method described above. First, in step 1, each data DATA _{1 to} DA
We are examining the degree of coincidence between TA ₅ and the search target information. Five memory cells on A _y1 by providing a signal of High-Low to A _y1 at first time, that is, the data DATA
A data string of ₁ is selected. At this time, High is applied to A _x1 and A _{x2 and} Low is applied to A _x3 , A _x4 and A _x5 . Applying High to A _x1 and A _x2 is equivalent to data DA
1 digit of TA _1, 2 digit means that searching for whether each "0", the third digit of the data DATA ₁ that applies the Low to A _x3 ~A _x5 ~ This means that whether or not the fifth digit is “1” is being searched. As a result of the search, the first and fourth digits of the data DATA _{1 do} not match the search target information.
It is clear that the third and fifth digits are in agreement therewith. This can be understood from the fact that pulses appear at A _x2 , A _x3 and A _x5 at the current I time. Therefore, the degree of coincidence of the data DATA ₁ is 3. Similarly, the degree of coincidence of the data DATA ₂ to DATA ₅ is calculated as 4, based on the number of current I pulses at
1, 2, and 3. However, in terms of circuit, c
A bipolar pulse such as current I cannot be superimposed as it is,
After converting ent I into unipolar current I ′, the number of pulses at each time is counted.

Finally, it was most similar to the search target information.
Data DATA_TwoRead the information of (01111) in step 3
Protruding. FIG. 29 shows the structure of the associative memory shown in FIG.
5 shows a fifth method. This method is based on the first method
It corresponds to the law. That is, first, in step 1,
The third to fifth digits of the search target information (00111)
“1” indicates each data DATA₁~ DATA _FiveStore in 3-5 digits of
Search for matches to the information
You. At this time, each data DATA₁~ DATA_FiveIn the first and second digits of
Does not search. Curre of step 1
As is clear from the nt part, the data DATA₁Is that
The third and fifth digits are "1" and the data DATA_TwoIs 3
It can be seen that all of the fifth to fifth digits are "1", and so on.
Next, in step 2, of the search target information,
"0" in the digit is each data DATA₁~ DATA_FiveIn the first or second digit of
Search for matches with stored information
I have. At this time, search is performed for the third to fifth digits of each data.
is not. From the current result of step 2,
Data DATA₁The second digit matches the search target information,
Data_TwoMatches the first digit, and the data DATA_ThreeIs 1 or 2 digits
It can be seen that the eyes do not match. And step
The degree of coincidence of each data in step 1 with "1"
Add the degree of coincidence of each data to "0" in step 2.
By doing each data DATA₁~ DATA_FiveSearch for
The degree of coincidence with the information can be obtained. This result
Data DATA_TwoIs most similar to the search target information
Understand. Finally, in step 3, this most similar
Data DATA_TwoIs output to the outside.

[IV] Manufacturing Method (i) Manufacturing Process A FIGS. 30 to 33 show an embodiment of the present invention. This embodiment discloses a method of manufacturing the above-described SRAM and the like.

The manufacturing process is roughly divided into the semiconductor layers 10
0, two negative differential diodes D ₁ and D ₂ are formed so as to have a predetermined connection by passivation by etching or ion implantation, and a threshold diode D
₃ and formation, and formation of the row address signal line A _x, formation of the row address signal lines A _y, consists of steps.

The semiconductor layer 100 uses an epitaxial growth method. That is, as shown in FIG. 15A, a good conductor layer (n ⁺⁺ GaAs) 12 and a conductor layer (n ⁺ GaAs) 12 are sequentially formed on a semi-insulating or insulating substrate (SI, GaAs) 11.
s) 13, the threshold diode D _3-layer (i-AlGaAs
s) 14, a conductor layer (n ⁺ -GaAs) 15, an i-AlAs layer 16 forming negative differential diodes D ₁ and D ₂ layers,
i-GaAs layer 17, i-AlAs layer 18, conductor layer (n
⁺ -GaAs) 19, and a good conductor layer (n ⁺⁺ GaAs)
Grow 20.

Next, a series of processes will be described step by step with reference to FIGS. 30 and 31, the drawings in the left column are II-II cross-sectional views in FIG. 19, and the drawings in the right columns are II-II 'cross-sectional views in FIG.

First, as shown in FIG.
A resist 101 is applied on the good conductor layer 20 on the layer 100
And the negative differential diode D₁, D_TwoTo form a
Turn. Next, as shown in FIG.
Negative differential diode D₁, D _TwoThe etching by putter
Formed. Next, as shown in FIG.
Closely patterned negative differential diode D₁,
D_TwoEach as one block by the resist 102
At this time, the width of the resist 102 is changed to a negative differential diode.
Do D₁, D_TwoThreshold diode to be formed below
Do D_ThreeOf the width. Next, FIG.
As shown in FIG._Three
Is formed. Next, as shown in FIG.
A resist 103 is applied to the surface, and a row address signal line A_xTo
The corresponding portion is patterned. Then, FIG.
As shown in (6), the good conductor layer 12 is formed by etching.
Shaved, independent row address signal line A_xForm a layer. Next
Next, as shown in FIG. 31 (7), a resist (lower layer) 10
5. Apply two-layer resist of resist (upper layer) 106
You. Next, as shown in FIG. 31 (8), the row address signal
Line A_yThe patterning of FIG.
As shown in FIG. 31 (10).
As shown in FIG.
And each address signal line A_x, A_yIs formed.

Here, as shown in the right side of FIG.
As shown in FIG.
Layer 105) and the column address signal
Line A _yHas an air bridge structure. This air
-Bridge structure, between adjacent memory cells,
The void 109 is formed. The gap has a dielectric constant ε = 1.
More parasitic than the state where the resist (lower layer) 105 is filled.
The capacity is reduced.

The S formed by the above manufacturing process A
FIG. 32 shows a three-dimensional structure of the RAM. FIG. 33 shows an example in which one of the column address lines A _y11 , A _y21 ... _Is shared by the GND lines.

(Ii) Manufacturing Process B This embodiment is a modification of the manufacturing process A shown in FIGS. Since the manufacturing process B is the same as FIGS. 30 and 31 from FIG. 30 (1) to FIG. 30 (5), illustration and description thereof are omitted.

In FIG. 35 (7), after the polyimide 110 is applied to the entire surface, the polyimide 110 is removed as shown in FIG. 35 (8), and flattening is performed. Next, FIG.
As in (9), a resist 111 is applied, and the row address signal line _Ay is patterned. Next, FIG.
As in the case of 0), the metal film 112 is deposited. Next, FIG.
As shown in (11), the resist 11 is lifted off.
1 and the metal film 112 thereon are removed to form a row address signal line _Ay .

(Iii) Manufacturing Process C FIGS. 36 to 40 show a manufacturing process c of the present invention. This embodiment provides a manufacturing method that reduces the use of a mask used for patterning and achieves high density by self-alignment.

[0096] destination, as described in FIG. 14 or FIG. 18, the row address signal line A _x column address signal lines A _y1 crossing the memory cell MC, and sandwiched in sandwiched between the column address signal line A _y2 and, two negative differential diode D ₁ and the memory cells MC on the threshold diode D _3,
By having a structure in which to place the D _2, the memory cell MC
As other necessary areas, only the area of the gap for separating the memory cells MC from each other is required, so that the degree of integration of the memory can be improved.

However, in order to pattern each element, according to the conventional manufacturing method, it is necessary to use a mask, and not only the basic areas of the negative differential diodes D ₁ and D ₂ but also the threshold diode. all to determine the position of the position row address signal line a _x of D ₃ must be used masks. Furthermore, the total area must be increased in consideration of the mask positioning error. As described above, in the conventional patterning method using a mask, a mask is required for most of each region, so that the process becomes complicated and there is a limit in reducing the area.

Therefore, the present embodiment realizes a self-alignment process by using a minimum mask, determines the area of each region by the thickness of the sidewall regardless of patterning rules, and efficiently increases the density. It is intended to provide a manufacturing method capable of achieving the following.

For this purpose, in this embodiment, first, FIG.
As shown in (1), the positional relationship between each diode and the address signal line of the adjacent memory cell is defined as follows. a: region of negative differential diode D _1, D ₂ b: negative differential diode D _1, the area for the D ₂ mutual separation c: negative differential diode D _1, D ₂ threshold diode D ₃ below D: a region for the mask positioning margin when forming the mask d: a region for separating the memory cells on the same address signal line A _{x from} each other e: a region for forming the address signal line A _x below the memory cell Area for positioning margin of mask f: Area for separating address signal lines A _{x from} each other A: Distance between negative differential diodes D ₁ and D ₂ B: Memory adjacent to same address signal line A _x negative differential diode D ₁ constituting the cell, D ₂ mutual spacing of the shortest C: negative differential diode constituting the memory cells on adjacent address lines a _x D _1, D ₂ mutual shortest distance d _1: the thickness of the insulating film 204 d _2: thickness d ₃ of the insulating film 205: a thickness of the insulating film 206 and defines the magnitude of the respective values as follows.

A <2d ₁ <B <2 (d ₁ + d ₂ ) <C <
2 (d ₁ + d ₂ + d ₃ ) The positional relationship of each part is defined based on such a relationship, and the process of the manufacturing process c described below is performed according to this definition.

Next, the present embodiment will be described with reference to FIGS.
Will be described. First, the semiconductor layer 100 is etched.
Growing it up in pitch. About the configuration of the semiconductor layer 100
Please refer to FIG. Next, FIG.
A metal film 201 is deposited on the good conductor layer 20 as shown in FIG.
Further thereon, an insulating film 202 is grown as shown in FIG.
After that, as shown in FIG.
Negative differential diode D ₁, D_TwoIs performed.
Next, as shown in FIG. 37 (4), etching is performed,
The insulating film 202 between the resists 203 is removed. Next
Next, as shown in FIG. 37 (5), the etching of the metal film 201 is performed.
And stripping of the resist 203 is performed.

Next, as shown in FIG.
Is etched. At the same time, negative differential diode
D₁, D_TwoIs formed. Next
Then, as shown in FIG. 38 (7), the negative differential diode D
₁And negative differential diode D_TwoInsulation that fills the gap
The film 204 is grown. Next, as shown in FIG.
Then, the insulating film 202 is etched by performing anisotropic etching.
Performing This process allows the threshold diode
D_ThreeIs performed. Then figure
As shown in FIG.
And the threshold diode D_ThreeThe pattern formed
It is. Next, as shown in FIG.
205, and then as shown in FIG.
The insulating film 205 is anisotropically etched to form an insulating film 2
05 and the row address signal line A _xPatterning
Do. Then, as shown in FIG.
The row address signal line A_xPatter
Is formed. Next, as shown in FIG.
After the insulating film 206 is entirely grown, FIG.
The insulating film 206 grown in (13) as in 4) is etched.
Remove by ching. Next, as shown in FIG.
As described above, the insulating film 207 is removed, and the row address signal line A_y
Is performed. Then, as shown in FIG.
After the insulating film 202 is removed by etching as described above,
A metal film 208 is deposited thereon as shown in FIG.
You. Next, as shown in FIG.
Is performed, the row address signal line A_yIs formed
You.

As described above, since the etching is performed using the own side wall for patterning, it is possible to efficiently and accurately form the memory cell MC without using a mask. Also, there is no need to allow for a marginal dimension due to the positioning accuracy of the mask, and no unnecessary area is taken, so that high density can be achieved.

In the above embodiment, the memory cell MC is formed of a GaAs semiconductor. However, the present invention is not limited to a semiconductor, but may be formed of a memory cell containing metal. For example, the row address signal line A _x, a metal such as nickel aluminum, it is possible to configure the combined memory cell and the semiconductor need this. The use of metal for the row address signal line _Ax has the effect of reducing adverse effects (such as hindering high-speed operation) due to resistance loss of the signal line. Alternatively, the resonance tunnel diode as the negative differential diode can be formed using an appropriate metal (nickel aluminum or the like), and the same applies to the threshold diode.

[0105]

As described above, according to the present invention, it is possible to provide a semiconductor memory comprising a novel memory cell which can be configured with a small area with a smaller number of elements.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of a memory cell of a storage device according to the present invention.

FIG. 2 is an equivalent circuit diagram of another memory cell according to the present invention.

FIG. 3 is a static characteristic diagram of a negative differential diode.

FIG. 4A is a series circuit diagram of a negative differentiating diode,
(B) and (c) are dynamic characteristic diagrams of the negative differentiating diode.

FIG. 5 is a static characteristic diagram of a threshold diode.

FIG. 6 is a characteristic diagram showing storage holding conditions of a memory cell.

7A is a characteristic diagram showing conditions for reading a stable point S ₁ of a memory cell, and FIG. 7B is a characteristic diagram showing conditions for reading a stable point S ₂ of a memory cell.

8A is a characteristic diagram showing a condition for writing a stable point S ₁ of a memory cell, and FIG. 8B is a characteristic diagram showing a condition for writing a stable point S ₂ of a memory cell.

FIG. 9 is a characteristic diagram at the time of holding data stored in a memory cell;

10 is a characteristic diagram showing a read operation stable point S ₁ of the memory cell.

11 is a characteristic diagram showing a read operation stable point S ₂ of the memory cell.

12 is a characteristic diagram showing the write operation stable point of the memory cell S _1.

13 is a characteristic diagram showing the write operation stable point S ₂ of the memory cell.

FIG. 14 is a perspective view showing a three-dimensional structure of a memory cell.

15A is a cross-sectional view showing a cross-sectional structure of a memory cell, and FIG. 15B is an energy band diagram of a resonant tunnel diode.

FIG. 16 is a block diagram of an SRAM circuit according to the present invention.

FIG. 17 is a block diagram of another SRAM circuit according to the present invention.

18 is a perspective view showing a three-dimensional structure of the SRAM shown in FIG.

FIG. 19 is a plan layout view of the SRAM of FIG. 17;

FIG. 20 is a perspective view showing a three-dimensional structure of the SRAM of FIG. 18;

21 is a plan layout view of the SRAM of FIG. 18;

FIG. 22 is a perspective view showing a three-dimensional structure of another SRAM.

FIG. 23 is a block diagram illustrating a method of reading data from an associative memory.

FIG. 24 is a time chart showing an associative memory and its reading method.

FIG. 25 is a time chart showing a method of reading data from an associative memory.

FIG. 26 is a time chart showing a method of reading data from an associative memory.

FIG. 27 is a block diagram illustrating a method of reading from the associative memory.

FIG. 28 is a time chart showing a method of reading data from an associative memory.

FIG. 29 is a time chart showing a method of reading data from an associative memory.

FIG. 30 is a process chart showing a manufacturing process A (1) of the memory device manufacturing method according to the present invention.

FIG. 31 is a process chart showing a manufacturing process A (part 2).

FIG. 32 is a perspective view showing an example of an SRAM formed by a manufacturing process A.

FIG. 33 shows another SRA formed by the manufacturing process A.
It is a perspective view which shows the example of M.

FIG. 34 is a process diagram showing a manufacturing process B (part 1) of another manufacturing method of the storage device according to the present invention.

FIG. 35 is a process chart showing a manufacturing process B (part 2).

FIG. 36 is a view illustrating the principle of a manufacturing process C of another manufacturing method of the storage device according to the present invention.

FIG. 37 is a process chart of a manufacturing process C (part 1).

FIG. 38 is a process chart of the manufacturing process C (part 2).

FIG. 39 is a process chart of a manufacturing process C (part 3).

FIG. 40 is a process chart of a manufacturing process C (part 4).

[Explanation of symbols]

CH ... contact hole D ₁ ... negative differential diode D ₂ ... negative differential diode D ₃ ... threshold diode GND ... ground potential line A _x ... row address signal line A _y ... row address signal line A _y1 ... first column Address signal line A _y2 ... second column address signal line MC, MC ₁ , MC ₂ , MC ₃ , MC ₄ ... memory cell S ₁ ... first operating point S ₂ ... second operating point V _Ax ... X address voltage V _Ay , V _Ay1 , V _Ay2 ... Y address voltage V _th ... threshold voltage V _th1 ... threshold voltage V _th2 ... threshold voltage V _p1 , V _p2 ... peak voltage V _v ... valley voltage 1 ... row address decoder 2 ... column address recorder 3 ... sense circuit 4 ... determination circuit 100 ... semiconductor layer 101 ... resist 102 ... resist 103 ... resist 104 ... conductive layer for X address lines 105 ... resist (lower layer) 106 ... resist ( Layer) 107 ... metal film 109 ... void 110 ... Polyimide 111 ... resist 201 ... metal film 202 ... insulating film 203 ... resist 204: insulating film 205: insulating film 206 ... resist 207 ... resist 208 ... metal film

──────────────────────────────────────────────────続 き Continuing on the front page (51) Int.Cl. ⁷ identification code FI H01L 27/10 481 (58) Investigated field (Int.Cl. ⁷ , DB name) G11C 11/41-11/419 H01L 27 / Ten

Claims (16)

(57) [Claims] A row address signal line, a column address signal line including a pair of signal lines, and a memory cell provided at an intersection of the row address signal line and the column address signal line. memory cell includes a element with two negative differential characteristics which are connected in series in the forward direction between the column address signal lines, the mutual connection point of the two element and the row address signal lines < connected between br />, and the threshold diode having a characteristic of current flow in the positive and negative directions in correspondence to it when the voltage exceeds the threshold voltage of positive and negative is applied, A storage device characterized by comprising: 2. The semiconductor memory according to claim 1, wherein
Wherein among the column address signal line, a storage device, characterized in that the one of the address signal lines and the common ground wiring. Wherein the row address signal wiring layer and the column address signal wiring layer consisting of parallel arranged signal wiring layer on two pairs
And the row address signal wiring layer and the column address signal wiring layer
Anda memory cell layer formed on the intersection between the memory cell layer, said have you <br/> to each address signal wiring layers, to the row address signal wiring layer side, the positive and negative threshold diode layer having a property of passing a current to the positive and negative directions in correspondence to <br/> threshold voltage side is formed in electrical contact with the row address signal wiring layer at one side thereof, Another side of the threshold value die layer and the column address signal wiring
Negative differential diode layer between one wiring layer of the layers
There are formed in electrical contact, and negative differential diode layer in electrical contact between the other wiring layers of the other surface and said column address signal wiring layers of said threshold diode layer A storage device characterized in that the storage device is formed in a stack. 4. The information reading method for a storage device according to claim 1, wherein two stable points can be constituted by said two elements having negative differential characteristics, and said two stable points are configured. The potential of any one of the points with reference to the interconnection point of the two elements is outside the voltage range between the negative threshold voltage and the positive threshold voltage of the threshold diode. As described above, a voltage is applied to the row address signal line and the pair of column address signal lines, and a reading method of the storage device is provided. 5. A method of reading memory device according to claim 1, when reading of the negative side of the stable points of the two stable operating points more generated element having a negative differential characteristics , the threshold voltage of the negative side threshold diodes, to be higher than the voltage of the negative side of the stable point, the electric position of the high level in addition to the row address signal lines and the pair column address signal lines the electric position of the low-level addition to the column address line of the low potential side, the operation at the time of reading of the positive side of the stable points of the stable point, the threshold voltage of the positive side threshold diode of the positive side of the stable points as the voltage column also decreases, and wherein the addition of high levels of conductive position to the column address signal line of the high potential side of the row address signal line electrodeposition position of the low-level addition to and a pair of column address signal lines A method for reading a storage device. 6. A method of reading memory device according to claim 1, the reading of one of the stable points of the two stable operating points generated I by the element having the negative differential characteristics sometimes, the electric position of the high level in addition to the row address signal lines, and both the column address signal lines, or among the column address signal lines
The electric position of the low-level addition to one of the low potential line, the operation at the time of reading of the other stable points of stable point, the electric position of the low-level addition to the row address signal lines, and the column address signal lines Both, or higher among the column address signal lines
Reading method of a storage device characterized by adding a conductive position of high level to one of the lines of electric potential. 7. The data writing method of a storage device according to claim 1, and as the two more two stable points element and one point of instability is created, the unstable point the potential based on interconnection point between 2 Tsunomoto child is to be outside the voltage range between the negative threshold voltage and the positive threshold voltage of the threshold diode, the row of Address signal
Write method of the memory device and applying a voltage to Sen及 beauty pair of column address signal lines. 8. A write method of a storage device according to claim 1, stability of the negative side of the two stable operating point and an unstable point that more generated element having a negative differential characteristics during information writing to the point, electrostatic position of the unstable point the threshold diode
Positive side of the electric position of the high level in addition to at least hand of the electric position of the low-level added and the column address signal lines to the row address signal line to be higher remote by threshold voltage, the stable operation point of When writing information to the positive stable point of
The electric position of the high level in addition to the row address signal lines as conductive position of the unstable point is lower remote by threshold voltage of the negative side of the threshold diode, and the column address signal lines writing method of a storage device characterized by adding a low-level electric position in hand. 9. A row address signal line comprising a plurality of signal lines
And the group, provided at each intersection between the row address and a signal line column address signal line group comprising a pair of signal lines disposed in a direction crossing the group, the row address signal lines and the column address signal line group a plurality of the claims 1 Memorise le according, and the row address signal line row address decoders for supplying row address signals to the groups, and a column address decoders for supplying a column address signal to the column address signal line group was, memory device characterized by comprising a sense circuits for detecting the row address signal line group or al the storage information of each Memorise Le. 10. The storage device according to claim 8, further comprising:
Storage device, characterized in that it comprises a determination circuits determines coincidence or discrepancy or similarity between the sense circuits to thus detected stored information and the search target information. 11. A reading method stored information from the storage device according to claim 10, wherein the row address decoders also properly gives search target information to either <br/> column address decoders A first step of applying a voltage to an address signal line of the one address decoder corresponding to data of logic “1” included in the search target information by one of the address decoders to which the search information is given; a voltage is applied to the address signal lines of the other address decoders by the other address decoder, a second step of detecting from <br/> stored information that is the result output to the sense circuitry, wherein the search information is given A voltage is applied to the address signal line of the one address decoder corresponding to the logic “0” data included in the search target information by the one address decoder. Then simultaneously, the voltage is applied to the address signal lines of the other address decoders by the other address decoder, and a third step of detecting from <br/> stored information that is the result output to sense circuitry, the first in second and third step based on a more detected stored information in the sense circuitry, match or mismatch or determining circuits of memory cell columns which approximates the search target information
Fourth step and the information reading method of a storage apparatus which comprises a to more judgments. 12. The information reading method for a storage device according to claim 11, wherein during the second and third steps, a voltage is applied to an address signal line of the other address decoder for each of the address signal lines. A method of reading information from a storage device, which is performed sequentially. 13. The information reading method for a storage device according to claim 11, wherein the second step and the third step are temporally performed in one cycle for each of the other address lines. To read information from a storage device. 14. The information reading method for a storage device according to claim 11, wherein the determination in the fourth step is performed by a logical determination of data for each address line. . 15. The information reading method for a storage device according to claim 11, wherein the determination in the fourth step is performed by obtaining a sum of currents flowing through all the address lines and comparing the sum of the currents. Method for reading information from a storage device. 16. A method of manufacturing a semiconductor device according to claim 3, conductor layer by epitaxial growth on an insulating base plate,
Conductive layer, threshold diode layer, negative differential diode
Layer, a first step of forming a semiconductor layer by laminating the conductive layer contact and a good conductor layer, through a metal film Contact and insulating film corresponding to the realm of the negative differential diode layer on the conductor layer a second step of patterning the negative differential diode layer using the mask, a third step of forming a negative differential diode layer by a semiconductor etching of the patterned semiconductor layer, by the third step Negative differential diode layer formed
A fourth step of performing anisotropic etching to pattern the threshold diode layer after growing an insulating film having a thickness that fills the gap between the semiconductor layer and the patterned semiconductor layer. A fifth step of forming a threshold diode layer by semiconductor etching, and then, an insulating film is grown on the entire semiconductor layer, and then an insulating film existing in the laminating direction of the semiconductor layer by anisotropic etching.
A seventh step of forming a sixth step of patterning the row address signal line, a row address signal line by semiconductor etching the patterned semiconductor layer is seen the removal of the negative differential diode layer An eighth step of forming a column address signal line layer thereon, a method for manufacturing a semiconductor device.