JP3148712B2 - Logic verification device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic verification device for performing a simulation operation of a logic circuit at high speed.

[0002]

2. Description of the Related Art With the advance of semiconductor technology, the degree of integration of a logic LSI has been improved year by year, and a large-scale system can be integrated on one chip.
It is becoming possible to construct a system such as an electronic device with I. However, when evaluating the validity of the logic when designing the logic circuit, when verifying the function of a large-scale logic, for example, an LSI including 100,000 gates or more or an entire system including the LSI, it is necessary to evaluate the function at an application level. Unless the functions are verified, improvement in design quality cannot be expected. In a simulation using software using a workstation (hereinafter, referred to as “EWS”) or the like, the number of steps is extremely large when executing an image or communication-related application, which is practically impossible in terms of processing time. It is possible. Further, it is difficult to make software models of general-purpose components such as CPUs, and it is difficult to faithfully simulate the entire system. Therefore, as a means for verifying a large-scale LSI or an entire system and evaluating the validity of the logic, a logic verification apparatus that executes a program at a machine language level and simulates the operation of another computer has attracted attention. .

[0003] The logic emulation is realized by an emulator composed of a logic device (Field Programmable Gate Array, hereinafter referred to as "FPGA") in the LSI part, and mounting general-purpose components such as a CPU and a memory on a printed circuit board. The logic circuit is verified by connecting the emulator to the printed circuit board and operating the circuit at an operation speed close to the actual logic circuit. Incidentally, Japanese Patent Application Laid-Open No. 8-772
No. 16, JP-A-7-296020, JP-A-6-296
JP-A-348786 and JP-A-4-15578 disclose an FPGA that constitutes a logic and an F that connects between the FPGAs.
A system for configuring a logic emulation by a PID is disclosed.

FIG. 27 shows the configuration of such a logic emulation system. In FIG. 27, reference numeral 11 denotes EW
S and 12 are emulators, 13 is an FPGA mounted on the emulator 12, and 14 is a switch array element (Field Programmable Interface) mounted on the emulator 12.
ct Device, hereinafter referred to as “FPID”), 15 is a printed circuit board, and 16 is a CP mounted on the printed circuit board 15.
U and 17 are memories mounted on the printed circuit board 15, 18
Is an ASIC mounted on the printed circuit board 15, 21 is design data of an LSI to be developed, and 22 is design data of a system. The emulator 12 has an FPGA 13 and an FP
A plurality of IDs 14 are mounted. Then, the emulator 12 is connected to the LSI section of the printed circuit board 15 to perform emulation. FIG. 28 is a process explanatory view showing the procedure of logic emulation. In FIG. 28, reference numeral 23 denotes a compiler, 24 denotes a download unit, 25 denotes program data of the FPGA 13, and 26 denotes an FPID 14.
Is the program data.

Next, the operation will be described. In FIG. 27, EWS11 is the design data 2 of the LSI to be developed.
1, 22 are converted to machine language and the emulator 12
Send to The emulator 12 stores the design data 21 and 2
The simulation operation of the LSI is performed as described below on the basis of No. 2. That is, as shown in FIG. 28, the compiler 23 reads the LSI design data 21 and generates program data 25 to be programmed in the FPGA 13 and program data 26 to be programmed in the FPID 14 for connecting the FPGAs. The generated program data 25 and 26 are transmitted to the emulator 12 by the download unit 24,
The program is executed by the FPGA 13 and the FPID 14.

[0006]

Since the conventional logic verification device is configured as described above, even if the emulation target is the entire system, only the LSI is actually realized by the emulator. The circuit is the same as the prototype board using a conventional breadboard, etc.
The logic change inside I can be realized by changing the design data and reprogramming the FPGA or FPID. The emulator 12 itself can be verified using another logic circuit. However, as for the printed circuit board 15, when the capacity of the memory is changed or the input / output terminal of the LSI is changed, for example, the other board cannot be diverted.
5 has to be repaired, and in some cases, the printed circuit board 15 must be re-manufactured for each logic circuit, and there has been a problem of solving these points.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem. Even if a printed circuit board is not manufactured for each product, emulation is performed not only on an LSI but also on an entire system. It is an object of the present invention to obtain a logic verification device which can easily change the logic of the logic verification. It is another object of the present invention to provide a logic verification apparatus capable of observing a waveform at the time of logic verification and improving the efficiency of logic emulation.

[0008]

A logic verification device according to the present invention comprises a logic circuit including a logic device whose logic can be changed by a program and a motherboard mounted with a connector wired from a logic connection element; And a connector wired from the logic circuit, and a daughter board mounted on the motherboard with the connector connected to the connector of the motherboard.

In the logic verifying apparatus according to the present invention, the motherboard may include a first wiring passing through the mounted logical connection element, a second wiring not passing through the logical connection element, and the first wiring and the second wiring. Switching means for switching between the wirings.

A logic verification device according to the present invention has a connector for connecting to a motherboard, and a waveform observation device I / F board wired to connect a waveform observation device for confirming a logic operation to the motherboard. It is provided.

In the logic verification device according to the present invention, the waveform observation device I / F board includes a connector connected to the daughter board, a second logic connection element connected to a signal line on the circuit by applying a program, Waveform observation device and second
And a signal observation probe connected to the logical connection element.

[0012] In the logic verification device according to the present invention, the motherboard includes control means for storing a program applied to the logic device and the logic connection element and controlling the logic device and the logic connection element.

A logic verification device according to the present invention includes an oscillator for generating a clock signal on a daughter board or a motherboard. The daughter board includes a clock signal generated from an oscillator mounted on the motherboard or the daughter board;
It is configured to switch between an external clock signal input from an external device.

In the logic verifying apparatus according to the present invention, the logic connection element is configured such that a plurality of signal lines are grouped and connected to a bus line having a predetermined number of bits.

A logic verification device according to the present invention connects a logic connection element to a terminal fixed component mounted on a daughter board and having a predetermined signal input / output terminal, and responds to the terminal fixed component connected to the logic connection element. It has program means for determining input / output terminals of a logical device and connecting a plurality of logical devices to one logical connection element.

A logic verification device according to the present invention includes a joint board for connecting a plurality of motherboards by wiring without changing the connection configuration of logic connection elements mounted on the motherboard.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a configuration diagram of a logic verification device according to a first embodiment of the present invention. In FIG.
S (program means), 102 is an emulator for actually executing emulation, 111 is emulator 10
Reference numeral 112 denotes a daughter board mounted on the motherboard 111. Also, 12
Reference numeral 1 denotes an FPGA (logical device) mounted on the daughter board 112, and 122 denotes a C mounted on the daughter board 112.
PU and 123 are memories mounted on the daughter board 112, and the FPGA 12 mounted on the daughter board 112.
1 and the CPU 122, the memory 123, etc., constitute a logic circuit. Reference numeral 131 denotes an FP mounted on the motherboard 111 for connecting the daughter boards 112 to each other.
ID (logical connection element), and the EWS 101 is an FPGA mounted on the motherboard 111 or the daughter board 112.
The program data is transmitted to 121 or FPID 131. Note that reference numeral 210 denotes LSI design data, and 211 denotes system design data.

FIG. 2 is a plan view of the motherboard 111. In FIG.
A control unit (control means) for programming in A121;
133 is a bus switch (switching means) composed of a semiconductor device or the like, 141A is a connector for connecting to the daughter board 112, and 141B is a daughter board 11
2, a connector mounted on the motherboard 111 for mounting the daughter board 112, and a connector 141P mounted on the motherboard 111 also for mounting the daughter board 112,
Reference numeral 42 denotes an I / O connector for connecting to an external device.

In this example, the connector 141A, the connector 141B, and the connector 141P
12 in each, 36 in total, 6 in FPID 131
And 12 I / O connectors 142. FIG. 3 is a side view when the daughter board 112 is mounted on the motherboard 111.

The connector 141A is for logical connection between the FPID 131 and the bus switch 133.
Is for logical connection between all signals and the FPID 131, and the connector 141P is for supplying power to the daughter board 112 and the like mounted on the motherboard 111 and the FPGA 1 mounted on the daughter board 112 except for logical connection information.
It is used for transmitting and receiving a configuration signal, a reset signal, a clock signal, etc. However, the connectors 141A, 141B, 141P may be integrated into one, and the number of connectors is not limited to the first embodiment.

FIG. 4 shows an example in which input / output terminals and components of an LSI mounted on the daughter board 112 are connected by programming the FPID 131. In this figure, 320 signal lines can be connected to the FPID 131 by a program, and the FPID 131 has a total of 96 signals, 4 signals each to the connector 141B.
1A, 4 signals each to the bus switch 133 for a total of 96
Book, 18 I / O connectors 142, 11 other FPs
Each of the IDs 131 is connected to a total of 110 of the ten IDs.

The connector 141A of the daughter board 112,
The connector 141A and the connector 141 of the other daughter board 112 from the connector 141B via the FPID 131.
B. The connection of the connector 141A, the connector 141B, the I / O connector 142, and the bus switch 133 is performed by a program by the EWS 101. Note that the two daughter boards 112 are basically connected via only one FPID 131.

As described above, according to the first embodiment, when the logic inside the LSI such as the CPU 122 mounted on the daughter board 112 is changed, the daughter board 11
The FPGA 121 mounted on the motherboard 111 only needs to be reprogrammed. If other logical changes are made, for example, the input / output terminal of the LSI or the connection between components is changed, the FPGA ID 131 mounted on the motherboard 111 is reprogrammed. By doing so, the logic of the LSI or system can be easily changed. Also, when the parts used in the system are changed or the number of parts is increased or decreased, the daughter board 1
This can be dealt with by exchanging, adding, or deleting 12, and the work of repairing the printed circuit board and remanufacturing the printed circuit board can be omitted. Furthermore, even when the target logic circuits are completely different, the same emulation system can be used, and the cost can be reduced.

Embodiment 2 FIG. FIG. 5 is a diagram showing the second embodiment, in which the connector 141A and the connector 1 on the motherboard 111 are changed by logically changing the FPID 131.
41B shows another connection example in which a connector 141P is connected. The overall configuration is the same as that of the first embodiment shown in FIG. 1 except for the connection configuration. In this figure, a connector 141 is attached to each of the FPIDs 131-1 to 131-12.
A total of 48 signal lines are connected from B to four each. Further, from the connector 141A, each FPID 131
, And a total of 36 signal lines are connected to the bus switch 133, and 12 signal lines are connected to the bus switch 133. 151 is a bus line,
The bus line 151 includes six 12-bit signal lines connecting the daughter boards 112 without passing through the FPID 131, and is composed of a total of 72-bit signal lines. The bus line 151 is used for a high-speed bus or the like. The signal from the FPID 131 and the signal from the connector 141A are switched by the bus switch 133 and connected to the bus line 151.

As described above, according to the second embodiment, F
By changing the logic of the PID 131, all signals can be connected via one FPID 131 without changing or increasing / decreasing parts, or the daughter boards 112 can be connected via the bus line 151 without passing through the FPID 131. can do. Therefore, when not passing through the FPID 131, it is possible to operate at the actual operating frequency of the final product without reducing the operating frequency of emulation.

Embodiment 3 FIG. FIG. 6 shows the third embodiment, and shows an example in which the motherboard 111 is connected to an external device. In FIG. 6, reference numeral 103 denotes an external device.
The external device 103 is connected to the I / O connector 142.
There are 12 I / O connectors 142 and each FPID 131
From each other are connected. 12 I / O
By connecting the connector 142 in parallel with a cable or the like, it is also possible to use the connector 142 as the 18-bit bus 152.

As described above, according to the third embodiment, by programming the FPID 131, it is possible to easily connect to the external device 103 without changing or increasing or decreasing parts or the like. Then, the logic verification can be performed not only with the emulation system but also with the actual device or system.

Embodiment 4 FIG. 7 shows the fourth embodiment and shows an example in which the motherboard 111 is connected to a clock line. In this figure, 104 is a crystal oscillator (oscillator) mounted on the motherboard 111 or the daughter board 112, 153 is an external clock line, and 154 is an internal clock line. If the clock line is connected via the FPID 131 or the bus switch 133 in the same manner as a general signal line such as data, problems such as a waveform distortion and an increase in skew between the daughter boards 112 occur. For this purpose, a dedicated clock line is provided. There are two types of clock lines, an external clock line 153 output from the crystal oscillator 104 and an internal clock line 154 output from the daughter board 112. The clock signal line is connected from the motherboard 111 to the daughter board 112 through the connector 141P. Switching of the clock is performed on the daughter board 112.

As described above, according to the fourth embodiment, by programming the FPID 131, the FPID 131 can be easily selectively connected to the external clock line 153 and the internal clock line 154 without changing or increasing or decreasing parts or the like. can do.

Embodiment 5 8 and 9 show the fifth embodiment, and show an example in which a logic analyzer for waveform observation is connected. In FIG. 8 which is a plan view of the logic analyzer I / F board, 105 is a logic analyzer (waveform observation device) for observing a waveform, and 113 is a logic analyzer I / F board for connecting the logic analyzer 105 to the motherboard 111. (Hereinafter, referred to as a “logicana I / F board”), 131-13 are FPIDs (second logical connection elements) mounted on the logicana I / F board 113, and 143 is a logic analyzer 105 and a logicana I / F board. This is a connector for connecting the H.113.

A signal observation probe (not shown) is connected to the FPID 131-13 so that all signal waveforms on the circuit can be observed. Also, Logiana I /
As shown in FIG. 9 which is a side view when the F board 113 is mounted on the motherboard 111, the logic analyzer I / F board 113 is connected between the daughter board 112 and the motherboard 111, and the connector 1 on the logic analyzer I / F board 113 is connected.
Connect to the logic analyzer 105 via 41P.
FID 131 and F on the logic analyzer I / F board 113
The program of the PID 131-13 is executed by the EWS 101, and the program signal of the FPID 131 is input from the connector 141P.

As described above, according to the fifth embodiment, the logic analyzer I / F board 113 is replaced with the daughter board 112.
FPID 131 connected to the motherboard 111 and the FPID 131-1 on the logic analyzer I / F board 113.
By programming 3, the logic analyzer 105 can be easily connected without changing or increasing or decreasing parts or the like. Further, since the logic analyzer I / F board 113 is provided with a probe, all signal waveforms on the circuit can be easily observed.

Embodiment 6 FIG. FIGS. 10 and 11 show the sixth embodiment, and show an example in which motherboards are connected to each other. 10, reference numeral 114 denotes a motherboard 111
-1, 111-2 to connect each other.
A, 141B, and 141P are arranged on a joint board. As shown in FIG. 11 which is a side view, two motherboards 111-1 and 111-2 are arranged, and a joint board 114 is mounted thereon. -1,
111-2 is connected. Daughter boards 112-1, 11
2-2 is mounted on the joint board 114. Since the connection of the connector 141P is reversed on the joint board 114, the motherboards 111-1 and 111-2 are connected by two.
FPID 131 and daughter board 112-
1, 112-2 (connector 141A, connector 141
The connection configuration of B) is wired so as not to be changed, and the signal lines on the daughter boards 112-1 and 112-2 are connected to all the FPIDs 131.

As described above, according to the sixth embodiment, by providing the joint board 114, the two motherboards 111-1 and 111-2 can be easily connected by the joint board 114 to expand the system. be able to.

Embodiment 7 FIG. 12 to 20 are diagrams showing pin arrangements according to the seventh embodiment. FPID131
Is basically determined inevitably from the pin arrangement of a pin fixing component (a terminal fixing component such as the CPU 122 and the memory 123, in which signal input / output pins are fixed in advance) for an arbitrary signal. FPGA12 with variable input / output pins
One pin is determined by a pin connected to the same FPID 131. FPID1 with multiple pin fixing components
31, the pins of the FPGA 121 are also connected to the same FPID 131, and when a plurality of pin-fixed parts are connected to different FPIDs 131, the priority order of the pins is specified by the daughter board connection information described later, and FPGA1 is assigned to the higher priority FPID131 of the pin.
Twenty-one pins are connected. In addition, a plurality of FPGAs 121
Are connected, the plurality of FPGAs 121 are all assigned to the same FPID 131. As described above, when the number of the pin fixing parts is one, the connection is made with one FPID. This connection is performed by being programmed by the EWS 101.

The connection structure will be described with reference to FIGS. In FIG. 12, three FPGAs 121-1 to 121-1
An example in which 121-3 is connected to one FPID 131 is shown. In FIG. 13, reference numeral 124 denotes a pin fixing component (hereinafter, referred to as “PFIX” in the drawing) in which signal input / output pins are fixed in advance.
1-1 and 121-2 are connected to one FPID 131. The pins of the FPGA 121 are determined according to the pin fixing parts 124.

In FIG. 14, two pin fixing parts 124-
1 and 124-2 are connected to the same FPID 131, and the pins of the FPGA 121 are pin fixing parts 124-1,
124-2 is determined. 15 and 16, three pin fixing parts 124-1 to 124-3 are connected to different FPIDs 131-1 to 131-3, respectively. Priorities are set for the pin fixing parts 124-1 to 124-3, and the pin arrangement information of the FPGA 121 is based on the FPI to which the pin fixing parts 124 having higher priorities are connected.
It is determined according to D131.

17 to 20, one FPID 13
One or more FPGAs 121 or one or more pin fixing parts 124 are connected to
The example which connected PID131 is shown. As described above, according to the seventh embodiment, any connection can be handled by programming the FPID 131 from simple wiring to complicated wiring.

Embodiment 8 FIG. FIG. 21 is a process explanatory diagram showing a logic construction procedure according to the eighth embodiment of the present invention.
In this figure, 210 is LSI design data, 211 is system design data indicating connection between components, 212 is motherboard connection information indicating the connected motherboard 111,
213, daughter board connection information indicating the connected daughter board 112; 214, user definition information for defining a board, a device name, etc .; 215, FPID connection information for specifying a physical connection of the FPID 131;
FPGA pin arrangement information designating pin arrangement of No. 1, 217
Is FPID pin arrangement information for designating the pin arrangement of FPID 131, 218 is logical change information, 219 is FPID 13
1 is a net list, 220 is FPGA program data for setting the wiring of the FPGA 121, 221 is an FPGA ID 1
FPID program data for setting 31 wiring, 22
2 is waveform observation definition information.

Reference numeral 201 denotes a design data input unit for reading LSI design data 210 and system design data 211; 202, a library information input unit for reading user definition information 214; 203, FPGA 121 and FPID1;
31 is a pin information generation unit that determines the pin arrangement, 204 is a logic change unit that reads the logic change information 218 during debugging and temporarily changes an arbitrary signal to a predetermined value, and 205 is an F
FPGA tool for generating PGA program data, 2
06, an FPID tool for generating FPID program data; 207, a download unit for downloading program data to the FPGA 121 / FPID 131;
A waveform observation unit 8 generates and downloads program data of the waveform observation FPID 131.

FIG. 22 shows an example of the user definition information 214.
23 shows an example of the connection information 212 of the motherboard 111, FIG. 24 shows an example of the connection information 213 of the daughter board 112, FIG. 25 shows an example of the logical change information 218, and FIG. 26 shows an example of the waveform observation definition information 222. Show.

In FIG. 22 showing the user definition information 214, reference numeral 301 designates the designation of the motherboard, 302 designates the device definition arranged on the daughter board 112, 303 designates the device arrangement definition of the defined device, and 304 designates the bus line 1
A bus line use definition indicating whether or not 51 is used;
Is a bus line signal name definition, 306 is an I / O connector signal name definition, and 307 is a waveform observation device connection definition.

In FIG. 23 showing the connection information 212 of the motherboard 111, 311 is a device definition, and 312 is F
Connection definition between PID 131 and each connector, 313 is FP
A connection definition between IDs, 314 is a connection definition between the FPID 131 and the I / O connector 142, 315 is a bus line 151
Is a connection definition between the device and each connector.
FPID1 mounted on the motherboard 111
31, a connector 141A, a connector 141B, and an I / O connector 142 are defined.
The physical connection between D131 and the connectors 141A and 141B is defined. The connection definition 315 defines a physical connection between the bus line 151 and the connector 141A.

In FIG. 24 showing the connection information 213 of the daughter board 112, the parts mounted on the daughter board 112 are FP
The description indicates whether the GA 121 is a general-purpose pin-fixed part, and the names and priorities of the respective terminals are described.

In FIG. 25 showing the logical change information 218, the value of the designated signal (SINGNAL_NAME) is set to "LOW" and "HI
"GH" or "open". In FIG. 26 showing the waveform observation definition information 222, a signal name and a probe N connected to observe the signal are shown.
o is described.

Next, the procedure will be described with reference to the flowchart of FIG. First, in the design data input unit 201, L
The SI design data 210 and the system design data 211 are fetched, and the library information input unit 202 fetches the user definition information 214. 24, the motherboard designation 301 is described in the user definition information 214, and the library information input unit 202 replaces the motherboard 111 designated here with the motherboard connection information 212.
Take in as. From the motherboard connection information 212, the FPID 131, the number of connectors, and wiring information can be obtained. Next, the library information input unit 202 specifies the type of the daughter board 112 to be used according to the device definition 302, and fetches the specified daughter board 112 as daughter board connection information 213.

Then, it is recognized in which connector the daughter board 112 is arranged according to the device arrangement definition 303. Next, the presence / absence of use of the bus line 151 is recognized according to the bus line use definition 304, and the signal name to be connected to the bus line 151 and the pin arrangement of the FPGA 121 are determined in the daughter board 112 equipped with the FPGA 121 according to the bus line signal name definition 305. In accordance with the I / O connector signal name definition 306, the I / O connector 142
Is recognized, and the presence or absence of connection of the logic analyzer I / F board 113 is recognized in accordance with the waveform observation device connection definition 307.

Then, the library information input unit 202 outputs the daughter board 112 and the FPID1 on the motherboard 111.
Then, FPID connection information 215 indicating the physical connection of the F.31 is generated. In the pin information generation unit 203, the FPGA pin arrangement information 216 and the FPI
D pin arrangement information 217 is generated.

When the logical change is made, the logical change unit 204 changes the netlist 219 of the FPID 131 with respect to the system design data 211, the FPID connection information 215 and the FPID pin arrangement information 217 according to the logical change information 218. .

The FPGA tool 205 compares the FPGA pin arrangement information 216 generated by the pin information
By processing the I design data 210, the FPGA program data 220 for determining the wiring to the FPGA 121 is generated. In addition, the FPID tool 206 includes the pin information generation unit 2
F that determines the wiring of the FPID 131 by processing the FPID pin arrangement information 217 generated in step 03 and the netlist 219 of the FPID 131 corrected by the logical change unit 204
The PID program data 221 is generated.

The download unit 207 stores the generated FP
According to the GA program data 220 and the FPID program data 221, FPID1 on the motherboard 111
The wiring of 31 is programmed, and the logic of the FPGA 121 on the daughter board 112 is changed.

When the logic analyzer 105 is connected, the waveform observing section 208 transmits the F on the logic analyzer I / F board 113 based on the waveform observing apparatus connection definition 307.
Generates a netlist of PID 131-13, and creates an FPID
The program to 131-13 is performed. Thus, the connection between the connectors 141A and 141B and the logic analyzer 105 can be easily changed by a program, and an arbitrary signal can be observed.

As described above, according to the eighth embodiment, F
By generating the PGA program data 220 and the FPID program data 221, a logical change can be performed. Note that not only can the programs of the FPGA 121 and the FPID 131 be downloaded from the EWS 101, but also the generated FPGA program data 2
20 and the FPID program data 221 can be stored in a memory built in the control unit 132 of the motherboard 111. Once stored in the memory, even if the EWS 101 is not present when the power is turned on, it can be downloaded from the memory. It becomes possible.

[0054]

As described above, according to the present invention, a logic verification device including a logic device for building logic by a program and a logic connection element for building a connection configuration of a logic circuit including the logic device by the program. A motherboard mounted with the logical connection element and a connector wired from the logical connection element, and a connector mounted with the logic circuit and the connector wired from the logic circuit, and the connector and the connector of the motherboard are connected and mounted on the motherboard. With a daughter board, it is possible to verify the entire system, easily change the logic not only inside the logic circuit elements, but also change the system components, and use programmable logic connection element stages. Can be minimized, and the efficiency of logic verification can be improved. In addition, there is no need to repair a printed circuit board or re-manufacture a printed circuit board in accordance with a logical change. Further, even when the target logic circuits are completely different, the same emulation system can be used, thereby reducing costs. be able to.

According to the present invention, the motherboard includes the first wiring passing through the mounted logical connection element, the second wiring not passing through the logical connection element, and the first wiring and the second wiring. And a switching unit for switching the operating frequency, it is possible to prevent a decrease in the operating frequency.

According to the present invention, there is provided a waveform observation device I / F board which has a connector for connecting to the motherboard and which is wired so as to connect the waveform observation device for confirming the logical operation to the motherboard. Therefore, the waveform observation signal can be changed.

According to the present invention, the waveform observation device I / F board includes a connector connected to the daughter board, a second logical connection element connected to a signal line on the circuit by applying a program, and a waveform observation device. And a signal observation probe connected to the second logic connection element, so that all signal waveforms on the circuit can be easily observed.

According to the present invention, the motherboard includes the control means for storing the program applied to the logic device and the logic connection element and controlling the logic device and the logic connection element. Logic verification can be performed immediately without downloading a program.

According to the present invention, the daughter board or the mother board includes an oscillator for generating a clock signal. The daughter board includes a clock signal generated from an oscillator mounted on the mother board or the daughter board and an external clock signal input from an external device. , The operating frequency can be prevented from lowering.

According to the present invention, since the logical connection element is configured to connect a plurality of signal lines to a bus line of a predetermined number of bits as a set, it is possible to easily connect to an external device. Become. Then, the logic verification can be performed not only by the logic verification device but also by combining with an actual device or system.

According to the present invention, the logic connection element is connected to the terminal fixing component mounted on the daughter board and having predetermined signal input / output terminals, and the logic device is connected to the logic connection device in accordance with the terminal fixing component. Determine the input and output terminals,
Since there is provided program means for connecting a plurality of logic devices to one logical connection element, when one terminal fixing component is used, connection can be made with one logical connection element.

According to the present invention, since the joint board for connecting a plurality of motherboards by wiring without changing the connection configuration of the logical connection elements mounted on the motherboard is provided, the system can be easily connected to the motherboard. Can be extended.

[Brief description of the drawings]

FIG. 1 is a diagram of a configuration logic verification device according to a first embodiment of the present invention.

FIG. 2 is a plan view of a motherboard built in the logic verification device of FIG. 1;

FIG. 3 is a side view when a daughter board is mounted on the motherboard of FIG. 2;

FIG. 4 is a detailed view of the first embodiment showing an example in which devices and the like mounted on a daughter board are connected.

FIG. 5 is a detailed diagram showing a connection example of a connector according to a second embodiment of the present invention.

FIG. 6 is a detailed diagram showing a connection example of an external device according to a third embodiment of the present invention.

FIG. 7 is a detailed diagram showing a connection example of clock lines according to a fourth embodiment of the present invention.

FIG. 8 shows a logic analyzer I / according to a fifth embodiment of the present invention.
It is a top view of an F board.

FIG. 9 shows a logician I / according to a fifth embodiment of the present invention.
It is a side view which shows the example of a connection of F board.

FIG. 10 is a plan view of a joint board according to Embodiment 6 of the present invention.

FIG. 11 is a side view showing a connection example of a joint board according to a sixth embodiment of the present invention.

FIG. 12 is a configuration diagram for explaining a pin arrangement determination process according to a seventh embodiment of the present invention.

FIG. 13 is a configuration diagram for describing a pin arrangement determination process according to a seventh embodiment of the present invention.

FIG. 14 is a configuration diagram for describing a pin arrangement determination process according to a seventh embodiment of the present invention.

FIG. 15 is a configuration diagram for describing a pin arrangement determination process according to a seventh embodiment of the present invention.

FIG. 16 is a configuration diagram for describing a pin arrangement determination process according to a seventh embodiment of the present invention.

FIG. 17 is a configuration diagram for describing a pin arrangement determination process according to a seventh embodiment of the present invention.

FIG. 18 is a configuration diagram for describing a pin arrangement determination process according to a seventh embodiment of the present invention.

FIG. 19 is a configuration diagram for explaining a pin arrangement determination process according to a seventh embodiment of the present invention.

FIG. 20 is a configuration diagram for describing a pin arrangement determination process according to a seventh embodiment of the present invention.

FIG. 21 is a flowchart showing a procedure when actually connecting a device or the like according to the eighth embodiment of the present invention.

FIG. 22 is a diagram of a program showing an example of the user definition information of FIG. 21.

FIG. 23 is an explanatory diagram showing an example of a program of motherboard connection information of FIG. 21.

FIG. 24 is an explanatory diagram showing an example of a program of the daughter board connection information of FIG. 21.

FIG. 25 is an explanatory diagram showing an example of a program of the logical change information of FIG. 21.

FIG. 26 is an explanatory diagram showing an example of a program of the waveform observation definition information of FIG. 21.

FIG. 27 is a configuration diagram of a conventional logic verification device.

FIG. 28 is a flowchart showing a conventional logic verification procedure.

[Explanation of symbols]

101 EWS (program means), 104 crystal oscillator (oscillator), 105 logic analyzer (waveform observation device), 111 motherboard, 112 daughter board,
114 Joint board, 121 FPGA (logical device), 131 FPID (logical connection element), 131
-13 FPID (second logical connection element), 132 control unit (control means), 133 bus switch (switching means), 141A, 141B, 141P, 143 connector, 151 bus line.

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Tatsuya Kimijima 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Inside Mitsubishi Electric Corporation (72) Inventor Kazuo Chiba 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric JP-A-4-198777 (JP, A) JP-A-8-221164 (JP, A) JP-A-6-110722 (JP, A) JP-A-5-88801 (JP, A) A) JP-A-10-10196 (JP, A) JP-A-7-287720 (JP, A) "Study of Flexible Hardware Design Method for ATM Node System", IEICE Technical Report, 1997 2 Mon., SSE 96-165, p. 17-22 "Educational RISC Microprocessor DLX-FPGA and Rapid System Prototyping", IEICE Technical Report, April 1995, CPS Y95-20, p. 71-78 (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 11/22-11/277 G01R 31/28-31/30 G06F 17/50

Claims (9)

(57) [Claims] 1. A logic verification device comprising: a logic device for building logic by a program; and a logic connection element for building a connection configuration of a logic circuit including the logic device by the program, wherein the logic connection device and the logic connection device A motherboard on which a wired connector is mounted; and a daughter board mounted with the logic circuit and a connector wired from the logic circuit, the connector being connected to the connector of the motherboard and mounted on the motherboard. Logic verification device. 2. A switching means for switching between a first wiring passing through a mounted logical connection element, a second wiring not passing through a logical connection element, and the first wiring and the second wiring. The logic verification device according to claim 1, further comprising: 3. A waveform observation device I / F board having a connector connected to the motherboard and wired to connect a waveform observation device for confirming a logical operation to the motherboard. The logic verification device according to claim 1 or 2. 4. A waveform observation device I / F board includes a connector connected to a daughter board, a second logical connection element connected to a signal line on a circuit by applying a program, a waveform observation device, and a second logic connection element. 4. The logic verification device according to claim 3, further comprising a signal observation probe connected to the logic connection element. 5. The motherboard further comprises control means for storing a program applied to the logic device and the logic connection element and controlling the logic device and the logic connection element. The logic verification device according to claim 1. 6. The daughter board or the mother board includes an oscillator for generating a clock signal. The daughter board switches between a clock signal generated from an oscillator mounted on the mother board or the daughter board and an external clock signal input from an external device. The logic verification device according to any one of claims 1 to 5, wherein the logic verification device is configured. 7. The logical connection element connects a plurality of signal lines to one.
7. The logic verification device according to claim 1, wherein the logic verification device is configured to be connected to a bus line having a predetermined number of bits. 8. A logic connection element is connected to a terminal fixing component mounted on a daughter board and having a predetermined signal input / output terminal, and an input / output terminal of a logic device is connected in accordance with the terminal fixing component connected to the logic connection element. 8. The logic verification apparatus according to claim 1, further comprising program means for determining and connecting a plurality of logic devices to one logic connection element. 9. A joint board for connecting a plurality of mother boards by wiring without changing the connection configuration of logical connection elements mounted on the mother board. The logic verification device according to claim 1.