JP3141247B2 - Sampling rate converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sampling rate converter for converting sampling frequencies when the mutual frequency relationship is not at an appropriate least common multiple.

[0002]

2. Description of the Related Art A sampling rate converter having an output digital filter is used for sampling an input signal at a predetermined first sampling frequency and converting a digital signal obtained as a result to an arbitrary second sampling frequency. ing.

As a specific example, SMPTE D-1 in a digital video tape recorder (DVTR) has been proposed.
The sampling frequency of the component digital video signal based on the (625/50) format is D-2 (PA
L) There is a case where the sampling frequency is converted to a sampling frequency corresponding to the PAL composite digital video signal based on the format.

[0004] The relationship between the two sampling frequencies described above is from a sampling frequency of 13.5 (MHz) to 17.734475 (MHz).
In this case, the ratio of the sampling frequency is 540,000 to 709,379, which is not a small integer ratio. In the sampling rate conversion having such a relationship, when directly obtaining the sample value after the sampling rate conversion, 709,379 filter coefficients are required per tap of the FIR filter.

[0005]

In the case where there is no appropriate relationship between the integer ratios as described above, the use of 709,379 filter coefficients increases the circuit configuration and the like. However, in order to avoid this, a configuration is used in which the number of filter coefficients is limited and the sampling frequency is 13.5 (M
Hz) to the sampling frequency 17.734475 (MHz), the value at the sampling point at the target position in the frame may not be obtained. That is, since the mutual sampling frequencies do not have an appropriate integer ratio, the converted sample value may be an output value near the sample point at the target position. Therefore, the sample value at the sample point near the target position has a deviation (or conversion error) from the sample value after the sampling rate conversion to be obtained.

In a screen composed of sample values based on such an approximate output value, a certain amount of conversion error included in the sample values after the sampling rate conversion has the same position every frame, that is, the time axis. When viewed in the direction, an error appears at a fixed (or fixed) position, or the amount of the conversion error periodically increases or decreases in one screen. Would.

As described above, when the relationship between the sampling frequencies of the sampling rate conversion does not have an appropriate integer ratio relationship and the order of the sampling rate conversion filter cannot be set to a necessary and sufficient value, the operation word length of the circuit in the apparatus is reduced. If the length cannot be sufficiently long and if both of the above cannot be obtained at the same time, it is very difficult to make the conversion error with respect to the time axis error inconspicuous.

In view of the above circumstances, the present invention compensates for a constant conversion error at a fixed point in a screen or cancels a periodic rate conversion error appearing in a screen with a simple configuration by the sampling rate conversion. It is an object of the present invention to provide a sampling rate conversion device that makes it inconspicuous.

[0009]

A sampling rate conversion device according to the present invention includes a sampling filter having a coefficient generating means for generating a coefficient to be applied to a weighting means in accordance with a coefficient address. A sampling frequency of the digital signal sampled at the second sampling frequency is converted to a second sampling frequency whose mutual frequency relationship with the first sampling frequency is not the least common multiple. A coefficient address generator for designating a coefficient address for obtaining a value at a sample point corresponding to the vicinity of the coefficient address and supplying the coefficient address to the coefficient generator, and a random number generator for generating a random number. Means for supplying a coefficient address signal from the random number generation means. By controlling the coefficient is varied in accordance with a random number, to solve the problems described above.

[0010]

The sampling rate conversion device according to the present invention comprises:
Even if the rate is converted to the second sampling frequency, the conversion error at this sample point is appropriately changed to cancel the error.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a sampling rate converter according to the present invention will be described with reference to FIG. In the case where the order of the rate conversion filter cannot be set to a necessary and sufficient value, the case where the operation word length of the circuit in the device cannot be obtained sufficiently, and the case where both of the above cannot be obtained simultaneously at the same time, the sampling rate conversion device is , And is basically constituted by a block circuit having a simple configuration as shown in FIG.

An input signal to be rate-converted is supplied to an input terminal 11.
Is supplied via This input signal is supplied to a rate conversion filter 12 including a sampling filter having a coefficient generating means for generating a coefficient to be applied to the weighting means according to the coefficient address. The rate conversion filter 12 receives an input signal by sampling a clock CK1 that is a first sampling frequency.

The rate conversion filter 12 includes a timing adjustment circuit and a sampling filter. The rate conversion filter 12 outputs a coefficient address signal generated by specifying a coefficient address corresponding to the vicinity of the target position of the second sampling frequency after the sampling rate conversion from the coefficient address specifying circuit 13 which is a coefficient address generating means. Is entered. As a result, the sample value of the sampling rate conversion is converted to an approximate value corresponding to the coefficient address signal by the second sampling frequency clock CK2.
Is resampled and output.

The coefficient address specifying circuit 13 adds a coefficient address, a correction value of the coefficient address, and a random number supplied from the outside, and supplies the result to the rate conversion filter 12 as a coefficient address signal. The random number supplied from outside is a random number (random) signal generator 14 which is a random number generating means.
It has been generated in. In this example, the random number signal is generated based on M-sequence random number generating means. The rate conversion filter 12 is supplied with the coefficient address signal fluctuating according to the supply of the above-described M-sequence random number signal. When the sample point of interest location of the sampling rate conversion as shown in FIG. 2 to be described later and the time t _A, a position which varies in this neighborhood,
For example, time t _B , t _C ,... Are sampled.

As described above, the sample value at the sample point t _B obtained by the rate conversion with respect to the sampling at the target position causes a conversion error between the sample value at the target position and the sample value at the sample point t _B. By sampling at a position corresponding to the variation of the conversion error, the conversion error can be made random, and the pattern of the conversion error generated by periodically increasing and decreasing can be canceled to avoid the appearance of the conversion error on the screen.

Next, the principle of converting the sampling rate by using the basic sampling rate converter shown in FIG. 1 will be described with reference to FIG. For example, the virtual analog signal S is input using a FIR (Finite Impulse Response) type sampling filter. This virtual analog signal S, the first sampling frequency CK1, namely the time t ₀ to the first sampling every period, t _1, · · ·, t _5, the input digital signal level sampled at · · · a _0, a ₁ , ...,
a ₅ ,...

Subsequently, the FIR in the rate conversion filter 12
The output digital signal level output from the type of sampling filter is, for example, a time t ₂ shown in FIG.
The output digital signal in the section between t and t ₃ will be described.
Here, the output digital signal obtained by the sampling rate conversion of the target position theoretically truly obtained is the output digital signal S _A at the time t _A. As described above, FIG.
The coefficient address designating circuit 13 outputs an output digital signal based on a coefficient address signal to be described later and a coefficient address signal changed according to a random number supplied from the outside.

[0018] If the coefficient address signal is generated only by the coefficient address by filtering the actual sampling rate conversion, the sample values S of the position of the time t _B as the best approximation to the time t _A of the target position
_B is output. For this reason, there is a conversion error (S _B -S _A ) between the output digital signal S _A that is theoretically desired to be truly obtained and the output digital signal S _B. That is,
This conversion error (S _B -S _A ) is the first on the frame screen.
Is always included as a conversion error of a fixed signal level in the output signal when the interpolated output is performed between the sample points at the sampling frequency of the sampling frequency conversion according to the second sampling frequency.

In the arithmetic processing using a set of filter coefficients having only limited dividing points as described above, generally only an approximate value at the best approximate point with respect to the target position can be obtained. For this reason, for example, when the input signal is an image signal with little variation in a still image, for example, the same position is always selected as the optimal approximation of the target position, and is output as a fixed fixed point.

When the output digital signal including the conversion error of the determined signal level is output, the conversion error as the difference of the signal level on the frame screen becomes conspicuous, for example, fixed at a determined position.

Therefore, the coefficient addressing circuit 13
Is a rate conversion filter 12 as a coefficient address signal obtained by newly changing a conventional coefficient address signal according to a random number.
Output to By including this random number signal, the output digital signal is not for example of between times t ₂ and t ₃ only output digital signal S _B in the vicinity of the output digital signal S _A theoretically obtained is always selected, The output digital signals S _C ,... Of each sample point at times t _C ,.

The output signals near the target position, such as the randomly selected output digital signals S _B S _C ,.
At the sampling frequency CK2, and output to the output terminal 15. Therefore, by receiving fluctuation coefficient address signal corresponding to the random number signal, the output digital signal is random output digital signal S higher signal level than _A S _B or low signal level S _C of the target position in each frame screen It looks like a signal in which the conversion error has been canceled by the output. With such a simple configuration, it is possible to output without a conversion error due to the sampling rate conversion being fixed on the screen.

If the order of the sampling rate conversion filter cannot be set to a necessary and sufficient value (that is, the signal level cannot be within the error range at the sample point to be obtained), the operation word length of the circuit in the apparatus In the case where the length is not sufficiently long and the case where both of the above are not sufficiently obtained at the same time, by using the above-described configuration, a fixed conversion can be performed by the output in the vicinity of the random output digital signal that is truly desired. A periodic pattern due to an error or a conversion error can convert the sampling rate without being canceled and displayed on the screen.

A more specific sampling rate converter based on the above operation principle will be described with reference to FIG. As shown in FIG. 3, the input signal is supplied to the timing circuit 22 in the rate conversion circuit 21 via the input terminal 20. The rate conversion circuit 21 is a timing circuit 22
And an FIR type sampling filter 23. The timing circuit 22 is a D flip-flop 2
It consists of 4 and 25. The D flip-flop 24
The input signal is latched and taken in at the rising edge of the clock CK1 of the first sampling frequency, and the next clock C
Input signal is input to D flip-flop 25 at the rise of K1.
To supply.

Here, in order to adjust the timing in the sampling rate conversion, the D flip-flop 25
Latches the supplied input signal at the rising edge of the clock CK2 of the first sampling frequency and captures it.
The input signal is sent to the sampling filter 23 at the next rising edge of the clock CK2. That is, the D flip-flop 25 outputs the data delayed by one clock. The sampling filter 23 outputs an output digital signal via an output terminal 37 in accordance with the coefficient address signal supplied from the coefficient address designating circuit 26. Details of the sampling filter 23 will be described later.

The coefficient addressing circuit 26 comprises a coefficient address generator 27 and an adder 28 having a pair of input terminals. The adder 28 has a coefficient address signal having one input terminal subjected to the correction processing from the coefficient address generator 27 and a random number (random) signal from a random number (random) signal generator 29 for generating a random number to be described later. ) Signal. The other input terminal of the adder 28 shown in FIG. 3 is supplied with a random number signal from a random number (random) signal generator 29 which is means for generating a random number.

The random number signal generator 29 cascade-connects three D flip-flops 30A, 30B and 30C, and comprises two multipliers 31A and 31B and an adder 32. In this configuration, the D flip-flop 30
The output of B is supplied to the input terminal of the adder 32 by ₁ × k by the multiplier 31B supplies a signal to the D flip-flop 30C. Similarly, the D flip-flop 30
C is supplied to the other input terminal of the adder 32 by k ₀ times multiplier 31A. The adder 32 adds the supplied signals and returns the result to the D flip-flop 31A.

With this configuration, the M-sequence random number signal outputs a random number corresponding to the equation based on x ³ + k ₁ x + k ₀ from the D flip-flop 30C. By choosing various coefficients k ₁ and k ₀ used in this equation,
For example, x ³ + 4x + 10, x
^{3 + 3x + 5, x 3} + 8x + 3, x 3 + 10x + 10 3 -order polynomial that like can be used the applied configure.

The adder 28 fluctuates according to the coefficient address signal from the coefficient address generator 27 and the random number signal from the random number signal generator 29 as described above, and outputs the added output signal to the sampling filter 23 as a coefficient address signal. As a supply. The coefficient address signal is the one shown in FIG.
It is supplied to coefficient generators 35A to 35K in the FIR type sampling filter 23 having one tap. The coefficient values output from the coefficient generators 35A to 35K are supplied to one ends of a pair of input terminals of the multipliers 34A to 34K, respectively. Each coefficient generator 35A~35K outputs ROM or coefficient values C ₀ -C ₁₀ according to the coefficient address signal supplied constituted by RAM,.

An input signal is cascaded from the above-described timing adjustment circuit 21 to each of the D flip-flops 33A to 33J. Each D flip-flop 33A-
33J, each D flip-flop delays by one clock (here, the clock used for delay is clock CK2) and outputs it by the timing of clock CK2. The delay output signal of each stage is output to each of the multipliers 34A to 34A.
34J are supplied to the other input terminals and multiplied by respective coefficient values corresponding to the coefficient address signal. Each adder 36A ~
This output signal is supplied to the input terminal of 36J, and the output from the previous adder is supplied to the other input terminal. However, the signals supplied to the input terminals of the adder 36A are both output signals from the multipliers 34A and 34B.

The adder 36J outputs the signal via the output terminal 37 when the sampling rate is converted to the second sampling frequency. As described above, the FIR type sampling filter 23 interpolates the sampling rate to the sample value at the sample point at the second sampling frequency based on the sample value (input signal) at the sample point at the first sampling frequency. Output.
With the above configuration, it is possible to provide a screen in which a conversion error always generated at a predetermined position in the screen and a rate conversion error periodically appearing in the screen, which are caused by the sampling rate conversion, are inconspicuous.

Further, the coefficient address generator 27 will be described with reference to FIGS. Generally, the coefficient address generator 27 is supplied with a clock CK1 as a first sampling frequency, a clock CK2 as a second sampling frequency, and a reset signal RS for resetting to an initial state (see FIG. 3). . The coefficient address generator 27 is provided by the present applicant on February 1, 1990.
The address generator of the earlier application dated 9th can be used, and this block configuration will be schematically described.

The coefficient address generator 27 comprises a counter circuit 40, a correction number counter circuit 41, a correction value multiplication circuit 42, a coefficient address generation circuit 43, an adder 44, a coefficient adjustment circuit 45, and a shift control circuit 46. I have.
The counter circuit 40 supplies, via the input terminal 38, the maximum value of both counters of the input digital signal before conversion and the output digital signal after conversion as the maximum value of the counter in accordance with the respective sampling periods. 2
Is cyclically counted at the sampling frequency (clock CK2). Thus, the counter circuit 40 counts the output clock signal for one frame and sends the count data to the coefficient address generation circuit 43. Further, the counter circuit 40 supplies a carry signal to the correction number counter circuit 41 every time the value exceeds the maximum value.

In the prior application, the reset signal RS supplied from the outside via the input terminal 39 inputs a frame pulse corresponding to each frame to the reset terminal of the counter circuit 40 and the reset terminal of the correction counter 41. ing. The coefficient address generation circuit 43 generates a coefficient address and shift data according to the supplied count data. This coefficient address and shift data are
The signals are sent to the adder 44 and the shift control circuit 46, respectively. The shift control circuit 46 includes the timing adjustment circuit 2
1 and the shift control data to the sampling filter 23 via an output terminal 48.

Further, the coefficient address generation circuit 43 counts a carry input during one frame, generates correction number data, and supplies the data to the correction value multiplication circuit 42. The correction value multiplying circuit 42 uses, as a correction value, a time difference between both sample points that are closest to each other in accordance with each sampling cycle of the input digital signal before conversion and the output digital signal after conversion, and uses this correction value as the correction value. Number counter 4
The correction frequency data supplied from 1 is multiplied to obtain the multiplied data as correction data corresponding to the coefficient address.

The adder 44 adds the correction data and the coefficient address and supplies the result to a coefficient adjusting circuit 45. FIG.
A coefficient adjustment circuit 45 in the coefficient address generator 27 shown in FIG.
Generates coefficient address data and outputs it to one input terminal of the adder 28 shown in FIG.

The overflow data generated by the coefficient adjusting circuit 45 detects a delay of one cycle of the coefficient address data as an overflow and supplies the overflow to the shift control circuit 46.

The shift control circuit 46 detects the timing of a sample point requiring a phase shift based on the input shift data and overflow data, and outputs a shift control signal via the output terminal 48 to the rate conversion filter 1.
The signal is supplied to a timing adjustment circuit 24 and a sampling filter 25 in FIG. In this way, under the control of the shift control signal together with the coefficient address signal, the sampling filter 25 outputs the output digital signal whose sampling rate has been converted.

A case where a luminance signal and a color difference signal are separately supplied by using a sampling rate converter based on the above-described configuration will be described with reference to FIG. 5 and, if necessary, FIG. . The luminance signal is supplied to the sampling rate conversion circuit 56 via the input terminal 51. The color difference signal 1 is supplied to a sampling rate conversion circuit 57 via an input terminal 52, and the color difference signal 2 is supplied to a sampling rate conversion circuit 58 via an input terminal 53. The sampling rate conversion circuits 56 to
Reference numeral 58 denotes a circuit configuration excluding the random number signal generator 29 of the sampling rate converter shown in FIG.

In this case, the part of the random number signal generator 29 is provided outside, and the random number signal 1 for the luminance signal and the color difference signal 1,
The random number signal 2 for two is supplied to the sampling rate conversion circuits 56 to 58 via input terminals 54 and 55, respectively. In the luminance signal sampling rate conversion circuit 56, the adder 62 adds the luminance signal so as to include the random number signal 1 and supplies the coefficient address signal to each of the built-in coefficient generators (not shown). The converted luminance signal is output via the output terminal 59. Also,
In the sampling rate conversion circuits 57 and 58 for color difference signals, adders 63 and 64 add the signals so as to include the random number signal 2 for color difference signals, and add coefficient address signals to built-in coefficient generators (not shown). The color difference signal 1 and the color difference signal 2 which have been supplied and subjected to sampling rate conversion are output to output terminals 60 and 61.
Output via.

A sampling rate conversion can be performed by supplying a random number signal for each of the separated signal components. As an example, the sampling frequency 13.5 (MHz) of the component digital video signal based on the SMPTE D-1 (625/50) format described above is changed to D-2 (PAL).
When converting to a sampling frequency of 17.734475 (MHz) in accordance with a PAL composite digital video signal based on a format, the mutual period is matched for each frame, so if this sampling rate conversion is repeated, conversion errors will be displayed repeatedly. . However, the above-described sampling rate conversion device cancels out the periodic rate conversion error appearing in the screen, and also exhibits an effect on the overlap of the conversion error when performing the conversion repeatedly, thereby conspicuous the image error. Can be eliminated.

[0042]

As is clear from the above description, according to the sampling rate conversion apparatus of the present invention, when the coefficient address signal contains a random number to control the rate conversion filter and does not have an appropriate integer ratio relationship. By using a simple configuration for the sampling rate conversion, the conversion error that appears in a fixed position in the screen or the conversion error that appears periodically in the screen in the past can be randomized to make the screen inconspicuous in error. Can be.

[Brief description of the drawings]

FIG. 1 is a basic block circuit diagram of one embodiment of a sampling rate conversion device according to the present invention.

FIG. 2 is a diagram showing an operation principle of the sampling rate conversion device of the block diagram shown in FIG.

FIG. 3 is a block circuit diagram of a more specific sampling rate converter.

FIG. 4 is a block circuit diagram showing a specific configuration of a coefficient address generator for converting a sampling rate shown in FIG. 3;

FIG. 5 is a block circuit diagram in a case where an input signal is separated into a luminance signal and a color difference signal, and random number signals are separately supplied to perform sampling rate conversion.

[Description of Signs] 11 Input Terminal 12 Rate Conversion Filter 13 Coefficient Address designation circuit 14 Random number generation circuit 15 Output terminal

Continuation of the front page (58) Fields investigated (Int. Cl. ⁷ , DB name) H03H 17/00 621 JICST file (JOIS) Practical file (PATOLIS) Patent file (PATOLIS)

Claims (1)

(57) [Claims] A sampling filter for generating a coefficient to be applied to the weighting means in accordance with the coefficient address, wherein the sampling frequency of the digital signal sampled at the first sampling frequency is set to the first sampling frequency . Mutual frequency relationship with sampling frequency
In a sampling rate conversion device for converting a second sampling frequency into a second sampling frequency that is not the least common multiple, a sampling address conversion is performed by designating a coefficient address for obtaining a value at a sampling point corresponding to a vicinity of a sampling position of the second sampling frequency. A coefficient address generating means for supplying the coefficient generating means; and a random number generating means for generating a random number. The coefficient address generating means varies a coefficient address signal according to the random number supplied from the random number generating means. Controlling the sampling rate.