JP3138912B2 - Pulse detection circuit and radio-controlled clock - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse detection circuit and a radio-controlled timepiece.

[0002]

2. Description of the Related Art At present, in Japan, a time code is superimposed and transmitted on a long-wave standard radio wave under the jurisdiction of the Ministry of Posts and Telecommunications. This signal is January 1 with one minute as one frame.
The time data from the cumulative number of days to the hour and minute is sent out serially in binary code. Specifically, one bit is a 1-Hz rectangular pulse (hereinafter, referred to as a 1-second signal), and the weights of “1” and “0” are each set to a pulse width of 5
It is represented by 00 ms and 800 ms, and a pulse of 200 ms is used as a position marker, and 40 kHz is used as a carrier.

In a clock that corrects the time by using this signal,
The reception is performed for a predetermined time, for example, 5 minutes continuously from the relation of power consumption, and the time information is read to correct the time.

More specifically, the demodulated time code is continuously sampled for several minutes, and when sampling is completed, bit determination is performed based on all the sampled data, and time information is obtained from the bit determination result. The time was being adjusted.

[0005]

In the above method, the demodulated rectangular pulses are all sampled from the start to the end of one cycle to determine the bit.

For this reason, when noise is mixed, the influence is surely received, and there is a high risk of erroneous determination.

[0007]

According to the present invention, there is provided a receiving means for receiving a signal including information defined by a pulse width of a rectangular pulse having a constant period, and a receiving means for receiving a signal having a higher frequency than the rectangular pulse. A pulse detection circuit including a control unit for sampling a rectangular pulse and reading information on the rectangular pulse based on the sampling result, wherein the information on the rectangular pulse has passed a first predetermined time from the start of one cycle. When it is possible to specify by the pulse width of the rectangular pulse in a time domain from a time point to a time point that is a second predetermined time before the end point of the one cycle, the control unit reads the information of the rectangular pulse when reading the information of the rectangular pulse. Sampling is performed in the time domain in one cycle, and the information of the rectangular pulse is read based on the sampling result. Since the sampling data of the unnecessary part is not used when reading the information of the rectangular pulse, even if noise is mixed in the unnecessary part, it is not affected, and the influence of the noise is not taken. Can be reduced.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present application is a receiving means for receiving a signal containing information defined by the pulse width of a rectangular pulse having a constant period, and a clock pulse having a higher frequency than the rectangular pulse. The pulse detection circuit includes a control unit that samples the received rectangular pulse and reads information on the rectangular pulse based on the sampling result.
The pulse width of the rectangular pulse in a time domain from a point in time when a first predetermined time has elapsed from the start point of the cycle to a point in time before the end point in the one cycle and a second predetermined time has passed, and the control means When reading the information of the rectangular pulse, sampling is performed in the time domain in the one cycle, and the information of the rectangular pulse is read based on the sampling result.

According to a second aspect of the present invention, there is provided a display means for displaying a current time, a receiving means for receiving a signal including time information based on information defined by a pulse width of a rectangular pulse having a constant period, The received rectangular pulse is sampled by a clock pulse having a frequency higher than that of the rectangular pulse, the information of the rectangular pulse is read based on the sampling result, the time information is detected from the read information, and the detected time is detected. A control means for correcting the display time of the display means based on the detected time information when the information is determined to be valid. The rectangular region in the time domain from the time point when the first predetermined time has elapsed from the time point to the time point when the second predetermined time has elapsed before the end point of the one cycle When the control means reads the information of the rectangular pulse, the control means performs sampling in the time domain during the one cycle, and converts the information of the rectangular pulse based on the sampling result. In addition to reading, when the detected time information is determined to be invalid, the time region for performing the sampling is extended.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below based on embodiments shown in the drawings.

In FIG. 1, reference numeral 1 denotes an oscillation circuit which outputs a reference clock signal. 2 is a receiving circuit constituting a receiving means, which comprises an antenna, a detecting circuit, a demodulating circuit, etc., receives a signal in which a time code is superimposed on a long-wave standard radio wave under the jurisdiction of the Ministry of Posts and Telecommunications, shapes the waveform, It demodulates and serially outputs a rectangular pulse (hereinafter, referred to as a second signal) representing a time code. Note that, in this example, the operation time of the receiving circuit 2,
That is, the reception time is set from AM0: 58 to AM1: 06. This operation time is set by a cam (not shown) that rotates in conjunction with the time hands of the time display unit 3 and a detection switch (not shown). The time display unit 3 constitutes display means and displays the current time. Reference numeral 4 denotes a control circuit constituting a control means, which comprises a CPU, a ROM, a RAM, and the like, and controls various operations. The control circuit 4 divides the reference clock input from the oscillation circuit 1 and divides the reference clock by the same cycle as the second signal, that is, a 1-second clock pulse having a 1-second cycle and a sampling clock pulse (1 ms cycle) for sampling the second signal. And generate. Reference numeral 5 denotes a second signal synchronous clock pulse output circuit, which synchronizes with the second signal and outputs a synchronous clock pulse having the same cycle as the second signal. Reference numeral 6 denotes a differential data memory, which is composed of a RAM or the like, and stores a plurality of delay times of a second signal with respect to a one second clock pulse. Reference numeral 7 denotes an offset value memory, which is composed of a RAM or the like, and stores an offset value for synchronizing a one-second clock pulse with a second signal. Reference numeral 8 denotes a sampling data memory, which comprises a RAM or the like, and stores sampling data of a second signal. 9 is an aggregation memory,
It comprises a RAM or the like and stores a duty ratio based on sampled data. 10 is a data memory,
It is composed of a RAM or the like, and stores the bit determination result of the second signal. 11 is a marker counter. Reference numeral 12 denotes a data rearrangement memory, which is composed of a RAM or the like, and rearranges and stores a plurality of stored bit determination results so that the results can be handled as BCD time-series data. 13 is a decode data memory,
It consists of AM and the like and stores decoded time information.
14 is a general-purpose timer. Next, the operation will be described with reference to FIGS. Note that the marker counter 11 has been cleared, and the memories 6, 7, 8, 9, 1
It is assumed that 0, 12, and 13 have been initialized.

When the display time of the time display section 3 becomes AM 0:58 and the receiving circuit 2 starts operating, the control circuit 4 outputs a synchronous clock pulse synchronized with the second signal from the second signal synchronous clock pulse output circuit 5. (Step 2a).

The specific operation of step 2a will be specifically described with reference to FIG.

When the second signal is input to the control circuit 4 by the operation of the receiving circuit 2, the control circuit 4 measures the delay time (shift of output timing) of the second signal with respect to the one-second clock pulse a plurality of times (for example, about 10 times). Then, the shift of the output timing (hereinafter, shift) is stored in the difference data memory 6 (step 3a).

The average value of the deviation is within a predetermined range (in this example, 20
It is between 0 ms and 800 ms. ) (Step 3b), that is, if the deviation is small,
When fluctuations occur in the second signal, it is determined that it is difficult to achieve accurate synchronization, and the generation timing of the one-second clock pulse is delayed by 500 ms (specific time), and the average deviation is in the range of 200 ms to 800 ms. (Step 3c), the difference data memory 6 is initialized, the process returns to step 3a, and the same operation as described above is performed. Here, the fluctuation of the second signal will be described. In many cases, the signal on which the second signal is superimposed temporarily fluctuates in the time direction due to the direction of the receiving antenna, the state of the outside world, and analog elements around the receiving circuit, for example, electromagnetic waves output from a microwave oven or the like. For example, at the time of transmission, although a rectangular pulse is transmitted at a cycle of 1 second,
Upon reception, a rectangular pulse may be temporarily detected with a period shorter than 1 second, or may be detected with a period longer than 1 second. Such a state is hereinafter referred to as fluctuation of the second signal.

The average value of the deviation is from 200 ms to 800 ms
If the difference is within the range (step 3b), it is determined that the deviation value stored in the difference data memory 6 can absorb the fluctuation of the second signal by taking its average value. The average value is calculated, and the offset value based on the calculated value is stored in the offset value memory 7 (step 3d). Then, a signal synchronized with the second signal can be output by delaying the generation timing of the one-second clock pulse by a time corresponding to the offset value. The control circuit 4 outputs the synchronized signal (hereinafter referred to as a synchronous clock pulse) from the second signal synchronous clock pulse output circuit 5 to the control circuit 4 (step 3e).

The reason why the average value of the deviation is set in the range of 200 ms to 800 ms will be described. FIG.
As shown by 5c, the shift from the rising of the clock pulse of 5a to the rising of the rectangular pulse is t3 (200
ms <t3 <800 ms), even if t4 (t4> t3) occurs due to fluctuations in the cycle T1,
The relationship between the rise of the rectangular pulse and the rise of the clock pulse does not reverse. That is, as shown in 5b, the rectangular pulse is slightly ahead of the clock pulse while the rectangular pulse is slightly behind the clock pulse due to the fluctuation, and the leading and trailing relation of both pulses is reversed. There is no. Therefore, even if there is fluctuation, the fluctuation of the shift due to it is only that much,
It does not appear as a large variation as in FIG. 5b.

As described above, when synchronizing the second signal with the one-second clock pulse, if the deviation is small and the second signal may be significantly affected by the fluctuation, the area is not greatly affected by the fluctuation. Since the generation timing of the one-second clock pulse is shifted, the influence of fluctuation can be reduced when synchronizing.

Returning to FIG. 2, step 2 as described above
a, the synchronous clock pulse synchronized with the second signal is output to the second signal synchronous clock pulse output circuit 5.
, The bit information is read from the second signal in synchronization with the generation timing of the synchronous clock pulse (steps 2b and 2c).

Before specifically describing the specific operation of step 2c with reference to FIG. 4, the bit determination will be described.

The bit information of the second signal described above is defined as "1", "0", and "marker" according to the pulse width in a one-second cycle. The determination can be made based on the pulse width in the region. More specifically, as described above, the second signal is weighted with “1” and “0” with a pulse width of 500 m, respectively.
s, 800 ms, and 2 as a position marker
Since a pulse of 00 ms is used, a “marker” is used when the pulse width in the time domain is small or nonexistent around 500 ms after the rise of the pulse.
Can be determined as “0” when the pulse width is large, and “1” when the pulse width is intermediate. For example, in the case where a second signal having no fluctuation can be accurately detected, in a time region from 500 ms to several ms before and after, a “marker” where no pulse exists and a duty ratio of 1 /
It can be determined as “1” for about two pulses and “0” for all pulses. If there is no fluctuation, the second signal is the first 20 bits of any bit information.
0 ms becomes “1”, and the last 200 ms becomes “0”. The operation of step 2c described below utilizes these characteristics.

The control circuit 4 samples the second signal by the sampling clock pulse (1 ms cycle) from the time when 250 ms has elapsed after the generation of the synchronous clock pulse to the time when the next synchronous clock pulse is generated. Store in sampling memory 8 (step 4
a, 4b, 4c, 4d). That is, when there is no fluctuation or noise, sampling is started except for the first 200 ms which is all "1".

When the sampling is completed, a correction for removing a desired portion (in this example, 200 ms) after the sampled data is performed (step 4e), the corrected data is totalized, a duty ratio is obtained, and the totaling is performed. It is stored in the memory 9 (step 4f). That is, when there is no fluctuation or noise, the last 20 that becomes “0”
The duty ratio is obtained by removing the sampling data in the 0 ms portion.

The control circuit 4 makes a bit judgment by comparing the stored duty ratio with a predetermined ratio (step 4g). In this example, the ratio of determining as a “marker” in consideration of fluctuation and noise is set to 0 to 0.1,
The ratio for judging "1" is 0.4 to 0.5, and the ratio for judging "0" is 0.9 to 1.0. If the ratio does not correspond to these, it is judged as "error".

The bit decision result is composed of 2 bits, and is divided into four types of "1", "0", "marker", and "error" as described above and stored in the data memory 10 (step 4h).

As described above, when performing the bit determination, the sampling data of a portion that is not necessary for the bit determination is deleted. Therefore, even if noise is mixed in the deleted portion, the noise is not affected. Can be reduced.

In addition, since the sampling data in a time region longer than a time region of 500 ms before and after several ms from which bit determination can be performed when there is no fluctuation is used, the influence of the fluctuation can be reduced.

Returning to FIG. 2, step 2 as described above
When the operation of c is completed, that is, when the reading of the bit information of the second signal is completed, if the read bit information is “marker”, the marker counter 11 is incremented,
When a "marker" is input for two consecutive seconds, the marker counter 11 is cleared (steps 2d, 2e, 2f, 2).
g). One minute is set to 1 by clearing the marker counter 11.
The storage of the time code of the time information as a frame is started.

When the time information of one frame (one minute) is stored by repeating the operation from step 2c to step 2g (step 2h), the one-minute bit information stored in the data memory 10 is stored in the BCD mode. The data is rearranged in the data rearrangement memory 12 so that it can be treated as sequence data, decoded, and the decoding result is stored in the decoder data memory 13 (step 2i).

When the above operation is repeated and time information for two consecutive minutes is stored in the decode data memory 13 (step 2j), it is determined whether or not the time difference between the continuous time information is one minute (step 2k). If it has reached one minute, the elapsed time is added to the decoded time to obtain a new current time (step 2m), and the display time of the time display unit 3 is corrected based on the current time (step 2m). Step 2n).

In step 2k, if the time difference between the continuous time information is not 1 minute, it is determined that the reception has not been correctly performed due to fluctuations or the like, and if not more than 6 minutes have elapsed since the start of the reception. (Step 2p), reduce the removed part of the sampling data (Step 2q)
Returning to step 2c, the same operation as described above is performed. In addition,
In this example, as a specific operation of step 2q, the part to be removed is changed from the last 200 ms to the last 190 ms,
Every time Step 2q is repeated to the last 180 ms, the removal area is reduced by 10 ms. Needless to say, the comparison value of the duty ratio for determining the bit information is changed according to the size of the used portion of the sampling data.

In step 2p, if six minutes or more have elapsed since the start of reception, it is determined that accurate reception cannot be performed even if reception is performed any longer, and the operation is terminated.

When reception cannot be performed accurately as described above, by increasing the sampling area, the influence of fluctuation can be reduced and accurate reception becomes possible.

In the above description, the operating time of the receiving circuit 2 is A
Although set from M0: 58 to AM1: 06, this can be changed as appropriate.

In the above description, the time series contents of two consecutive frames are used to determine whether the time information has been correctly received. However, this is not limited to two minutes, and may be changed as appropriate. It is possible.

In the above description, when the average value of the delay time of the second signal with respect to the one-second clock pulse is out of the predetermined range (200 ms to 800 ms in this example), the generation timing of the one-second clock pulse is set to 500 ms.
The delay time is set to fall within the predetermined range, but the delay time is not limited to 500 ms, and may be changed as appropriate as long as the time falls within the predetermined range. Also, 2
The predetermined range from 00 ms to 800 ms can be appropriately changed.

In the above description, the ratios for initially performing bit determination are 0 to 0.1, 0.4 to 0.5,
The ratio is set to 0.9 to 1.0, but this ratio can be changed as appropriate.

When the time information cannot be received correctly, the sampling data removal area is reduced by 10 ms, but this amount can be changed as appropriate.

[0039]

According to the present invention, when reading information of a rectangular pulse, sampling data of an unnecessary portion is not used, so that even if noise is mixed into this unnecessary portion, it is not affected. , The probability of being affected by noise can be reduced.

Further, when detecting time information from the read information, if the detected time signal is invalid, the time region for sampling is extended, so that the influence of fluctuation can be reduced and accurate time correction can be performed. Becomes

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing an embodiment of the present invention.

FIG. 2 is a flowchart for explaining the operation of FIG. 1;

FIG. 3 is a flowchart for explaining the operation of FIG. 1;

FIG. 4 is a flowchart for explaining the operation of FIG. 1;

FIG. 5 is an explanatory diagram for explaining a problem due to fluctuation.

[Explanation of symbols]

 2 receiving means 3 display means 4 control means

Claims (2)

(57) [Claims] 1. A receiving means for receiving a signal containing information defined by a pulse width of a rectangular pulse having a constant period, and sampling the received rectangular pulse by a clock pulse having a frequency higher than that of the rectangular pulse; A pulse detecting circuit for reading information on the rectangular pulse based on a result, wherein the information on the rectangular pulse is determined from a point in time when a first predetermined time has elapsed from a start point in one cycle to an end point in the one cycle. It can be specified by the pulse width of the rectangular pulse in the time domain up to a point in time before the second predetermined time, the control means, when reading the information of the rectangular pulse,
A pulse detection circuit for performing sampling in the time domain in the one cycle and reading information of the rectangular pulse based on a result of the sampling. 2. A display means for displaying a current time; a receiving means for receiving a signal including time information based on information defined by a pulse width of a rectangular pulse having a constant period; and a clock having a higher frequency than the rectangular pulse. The received rectangular pulse is sampled by a pulse, the information of the rectangular pulse is read based on the sampling result, the time information is detected from the read information, and it is determined that the detected time information is valid. In this case, in the radio-controlled timepiece provided with control means for correcting the display time of the display means based on the detected time information, the information of the rectangular pulse is obtained when a first predetermined time has elapsed since the start of one cycle. From the end of the one cycle to the end of the one cycle before the second predetermined time by the pulse width of the rectangular pulse. Are those capable of, said control means, when reading the information of the rectangular pulse,
Sampling is performed in the time domain of the one cycle, the information of the rectangular pulse is read based on the sampling result, and the time domain in which the sampling is performed when the detected time information is determined to be invalid is lengthened. A radio-controlled timepiece characterized by the following.