JP3137311B2 - Test method for line corresponding parts such as ATM exchanges - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an ATM (Asynchronous
Transfer Mode) relates to a method for testing a line corresponding unit such as an exchange.

[0002]

2. Description of the Related Art Conventionally, in an ATM communication device such as an ATM switch, various functions such as cell counting and header conversion are performed for each of a plurality of logical channels, interposed between one ATM multiplex line and a switch unit. When testing a line corresponding unit, a test apparatus having a test cell generating unit and a test cell checking unit is connected to the line corresponding unit via an ATM multiplex line, and the test cells are conducted for each channel. Was.

FIG. 2 shows an example of the above-mentioned conventional test method. In the figure, reference numeral 1 denotes a test apparatus having test cell generating means 2 and test cell collating means 3;
Is a line corresponding unit having cell counting means 6 for executing cell counting for each of a plurality of logical channels, a header conversion circuit 7 for executing header conversion for each of a plurality of logical channels, etc., 8 is a switch unit, and 9 is a line corresponding unit 5. And an ATM switch including a switch unit 8.

[0004]

By the way, the number of logical channels, that is, the multiplicity, of the line-corresponding unit usually reaches several thousand channels. Therefore, the conventional test method described above has a problem that a continuity test for each channel needs to be performed several thousand times in order to test all the logical channels, and a large test time is required. Further, in order to conduct a continuity test of the line corresponding section using the maximum cell rate specified in the line corresponding section, for example, a test cell flow corresponding to the maximum cell rate specified at the point A in FIG. It is necessary to prepare a test device that can be generated, and there is a problem that the speed of the test device must be increased in accordance with the increase in the speed of the line corresponding unit. Further, when one ATM exchange simultaneously accommodates a plurality of line corresponding parts having different speed types, various test devices are prepared to test the line corresponding parts of the one ATM exchange. There was a problem that had to be done.

[0005] A first object of the present invention is to test all logical channels of a line corresponding unit in one test,
An object of the present invention is to provide a test method that can significantly reduce the test time.

A second object of the present invention is to provide a test method which can test all logical channels of a plurality of line corresponding parts in one test and can greatly reduce the test time. is there.

A third object of the present invention is to provide a test method capable of realizing a test of a line corresponding unit using a maximum cell rate specified in the line corresponding unit by using a test apparatus having a lower cell generation speed. Is to provide.

It is a fourth object of the present invention to provide a test system which can test a plurality of line corresponding units having different speed types by using one type of test equipment.

[0009]

According to the present invention, in order to achieve the first object, a test apparatus having a test cell generating means and a test cell collating means is connected to a switch section, and a test cell is connected to a line corresponding section. Test cell folding mechanism
Each time one test cell passes through the line corresponding unit, the VPI / VCI value in the one test cell is changed to a plurality of each of the line corresponding units.
A header conversion circuit that changes sequentially according to the logical channel is provided.

In order to achieve the second object, a test apparatus having a test cell generating means and a test cell collating means is connected to a switch section, and each of the plurality of line corresponding sections is
Line a VPI / VCI value of the in one trial <br/> test cell each time a test cell loopback mechanism and one trial <br/> test cell wrap test cell passes through the line interface of the plurality of Multiple topics in the corresponding section
A header conversion circuit that changes sequentially according to the physical channel is provided.

Further, in order to achieve the third object, a plurality of test cells are continuously transmitted from a test apparatus.

Further, in order to achieve the fourth object, a plurality of test cells are continuously transmitted from the test apparatus, and the number of times of passage of the test cells is changed for each line corresponding unit.

[0013]

According to the present invention, a VPI / VPI / VPI / VPI / VPI / VPI generated by the test cell generating means of the test apparatus and corresponding to a predetermined logical channel.
The test cell having the VCI value is sent to the line corresponding unit via the switch unit, and is returned by the test cell return mechanism. The folded test cell is supplied with V by the header conversion circuit.
The PI / VCI value is converted and transmitted again to the line corresponding unit via another logical channel. By repeating this, the test cell passes through all the logical channels, is returned to the test apparatus, and is collated by the test cell collating means. If there is no bit error or the like, it is determined that all the logical channels of the line corresponding unit are normal. .

Further, according to the present invention, a test cell having a VPI / VCI value corresponding to a predetermined logical channel, generated by a test cell generating means of a test apparatus, is connected to one line corresponding unit via a switch unit. It is sent out and folded by the test cell folding mechanism. The returned test cell is transmitted to another line corresponding unit via the switch unit, and returned by the test cell return mechanism in the same manner as described above. In the process, the VPI / VCI value is converted by the header conversion circuit, The data is again transmitted to the one line corresponding unit via another logical channel. This is repeated, and the test cell passes through all the logical channels, is returned to the test apparatus, is collated by the test cell collation means, and if there is no bit error or the like, it is determined that all the logical channels of the plurality of line corresponding units are normal. judge.

Further, according to the present invention, a plurality of test cells continuously transmitted from the test apparatus are multiplexed on a loop formed by the switch section and the line corresponding section, and apparently at a high speed, for example, in the line corresponding section. Is input to the line corresponding unit as a cell flow having the maximum cell rate specified in the above.

Further, according to the present invention, a plurality of test cells continuously transmitted from the test apparatus are multiplexed on a loop formed by the switch section and the line corresponding section, and apparently have a high-speed cell flow. However, since the number of passes differs for each line corresponding unit, a cell flow having a speed corresponding to the speed type of the line corresponding unit is input to each line corresponding unit.

[0017]

FIG. 1 shows a first embodiment of the system of the present invention. In the drawing, the same components as those of the conventional example are denoted by the same reference numerals. That is, 4 is an ATM multiplex line, 8 is a switch unit, 1
Reference numeral 0 denotes a continuity test circuit in a communication path, and reference numeral 11 denotes a line corresponding unit.

The intra-channel continuity test circuit 10 is a test device having a test cell generating means and a test cell collating means (both not shown), and is connected to the switch unit 8 having a one-sided configuration. In addition, the line handling unit 11 together with the cell counting unit 6
A test cell return mechanism 1 for returning test cells generated by the intra-channel continuity test circuit 10 and output from the switch unit 8
2 and the VPI / VCI value in the test cell
A header conversion circuit 13 is provided, which changes sequentially each time the signal passes through 1.

The test cell folding condition in the test cell folding mechanism 12 may be a case where only test cells are folded by performing filtering at a cell level, or a case where all cells are physically folded. Is applicable in any case. Also, a cable return may be provided on the ATM multiplex line 4 side from the line corresponding unit 11 to realize physical return, and the test cell return mechanism may be substituted. Furthermore, the test cells may be turned back by a test cell turning mechanism of an external device (not shown) connected to the line corresponding unit 11 via the ATM multiplex line 4.

FIG. 3 shows a modification of the first embodiment of the present invention. Here, an example of application to an ATM switch provided with a header conversion circuit in a switch section is shown. That is, in the figure, reference numeral 8a denotes a switch unit, and a header conversion circuit 13 is provided for each physical input terminal. Note that reference numeral 11a denotes a line corresponding unit, which is the same as the line corresponding unit 11 except that the header conversion circuit 13 is not provided.

As will be described later, in the present invention, it is essential to periodically conduct the test cells by combining the functions of the test cell folding mechanism and the function of the header switching circuit. Not dependent. Further, since the effect of the present invention is not related to the generation part and the verification part of the test cell, the continuity test circuit in the communication path does not necessarily need to be connected to the switch unit.

FIG. 4 shows another modification of the first embodiment of the present invention. Here, an application example of an intra-channel continuity test circuit to an ATM switch provided in a line corresponding section is shown.
That is, in the figure, reference numeral 11b denotes a line corresponding unit, which is provided with the intra-channel continuity test circuit 10 together with the above-described cell counting means 6, test cell return mechanism 12, and header conversion circuit 13.

FIG. 5 shows an example of a header conversion in the first embodiment of the present invention. Hereinafter, the present invention will be described with reference to FIGS.

As described above, the line handling unit 11 includes the cell counting means 6 and the header conversion circuit 13, which are set to operate individually for each logical channel. Therefore, in order to confirm that the functions of the line corresponding unit 11 operate normally, it is necessary to conduct a test for each channel by making the test cells conductive for all logical channels.

Conventionally, a test device having a test cell generating means and a collating means is connected to the ATM multiplex line side of the line corresponding section 11 to conduct test cells for each channel and verify the connection. The test was performed by transmitting test cells from the network and conducting the test cells individually for each channel. However, in the present invention, the test cells are periodically switched between the line corresponding unit 11 and the switch unit 8. By conducting while changing, all the logical channels are tested in one test.

In order to execute this test, the conversion table 14 in the header conversion circuit 13 is set as shown in FIG. In the figure, A to Z are VPI (Virt) of the cell.
ualPath ID) / VCI (Virtual Channel ID) value. When a test cell having the value A arrives in the conversion table 14, the VPI /
The VCI value is converted to B, and the values of B to Z after conversion are also set on the input side of the conversion table 14 except for Z used for collecting test cells.

Under this condition, one test cell having a VPI / VCI value of A is transmitted from the intra-channel continuity test circuit 10 and the routing tag in the switch is set so as to reach the output terminal # 1 of the switch section 8. Is set, the test cell is input to the line corresponding unit 11 after passing through the output terminal # 1. Here, the routing tag is information for indicating the position of the output terminal of the switch unit 8, and is set using an extension bit or the like assigned to a test cell in the ATM exchange.

The test cell input to the line corresponding unit 11 is
The logical channel A of the execution unit for the cell counting means 6 and other functions (not shown) which is folded back by the test cell folding mechanism 12
, And then input to the header conversion circuit 13.
The VPI / VCI value of the test cell is converted from A to B based on the conversion table 14 of the header conversion circuit 13. At this time, the destination of the routing tag is the output terminal # 1 as described above.
Set to. As a result, the test cell is routed in the switch unit 8 to reach the output terminal # 1 and is again input to the line corresponding unit 11, so that the test cell goes around the route shown by the thick line in FIG.

By repeating this operation, the test cell becomes VPI
While the / VCI value is periodically changed from A to Y, each logical channel set in the line corresponding unit 11 is repeatedly passed. The total value from A to Y is the line corresponding unit 11
In the case of the maximum number of channels that can be set to, the test of all logical channels is completed in one test.

Finally, the VPI / VC
By converting the I value from Y to Z and setting the routing tag to the output terminal #N of the switch unit 8 to which the intra-channel continuity test circuit 10 is connected, the test cell is connected to the intra-channel continuity test circuit 10. Collected. Telecommunication test circuit 10
Then, the normality of the test for all the logical channels of the line corresponding unit 11 is confirmed by checking the collected test cells and confirming that there is no bit error or the like.

As described above, according to the present embodiment, the number of tests required for testing all the logical channels of the line corresponding unit 11 can be reduced to one. The test time can be greatly reduced as compared with the test method of (1).

[0032]

Embodiment 2 In the first embodiment described above, a test system using one test cell has been described. In the second embodiment, a test system in which a plurality of test cells are continuously transmitted will be described. . The device configuration is the same as in the first embodiment.

As shown in the first embodiment, since the test cells go around one physically closed loop, when a test cell is generated at a low speed and transmitted to the test route, a plurality of test cells are generated. As a result, the cell stream can be created at a speed higher than the cell sending speed. However, since there is a limit to the amount of information that can exist on one physically closed loop, when performing a test using a plurality of test cells, the transfer rate of cells on the loop is taken into consideration. It is necessary to transmit the test cell that has been set.

When N logical channels are set in the header conversion circuit 13 in the line corresponding unit 11, a maximum of N VCs (Virtual Channels) are multiplexed in the line corresponding unit 11. If there is no limit on the test cell transmission time from 10, the upper limit of the test cell transmission speed R is given by R ≦ (1 / N) Rmax (1) Here, Rmax means the maximum cell rate defined in the line handling unit 11.

On the other hand, when a certain condition is set for the continuous cell sending time T from the intra-channel continuity test circuit 10, it is possible to use R larger than the condition of the equation (1). FIG.
Is the maximum amount of information existing on a physically closed loop, Rmax is the time required for cell transfer in one round of the loop.
Since To, the condition for defining the maximum value of T is as follows: RT ≦ Rmax To (2) From the equation (2), T ≦ (Rmax / R) To (3)

Therefore, when a test using a plurality of test cells is carried out in the present invention, the continuity test circuit in the communication path at a speed of 0 <R ≦ (1 / N) Rmax unless the limiting condition of T is provided. 10 to transmit a test cell, and (1 /
N) When a test cell is transmitted at a rate of Rmax <R ≦ Rmax, T ≦ (Rmax / R) with respect to the continuous cell transmission time T
A condition of To is provided.

By satisfying this condition, a test using a plurality of test cells can be performed without cell loss due to congestion of the test cells in the ATM exchange.
At the same time, a test of the line corresponding unit 11 using the maximum cell rate Rmax specified in the line corresponding unit 11 is performed by a test apparatus having a cell transmission rate R lower than that, here, the continuity test circuit 10 in the communication path. It can be carried out.

[0038]

[Embodiment 3] FIG. 6 shows a third embodiment of the system according to the present invention, in which a case is examined in which a line-corresponding portion of an ATM exchange having a two-sided switch section is tested. That is, in the figure,
4-1, 4-2, and 4-3 are ATM multiplex lines, 10 is a continuity test circuit in a communication path, 11-1, 11-2, and 11-3 are line corresponding units, and 15 is a switch unit.

Line handling units 11-1, 11-2, 11-3
Are basically the same as the line corresponding unit 11 in the first embodiment, and are respectively ATM multiplex lines 4-1, 4-2 and 4-.
3 and the switch unit 15. The switch unit 15 is a two-sided switch unit, and includes a plurality of switch units, for example, two switch units.
By constructing a physically closed loop as shown by the bold line in FIG. 6 by using the line-corresponding units 11-1 and 11-2, the test of all logical channels of each line-corresponding unit is performed once. Tests can be performed. It should be noted that simultaneous testing of a plurality of line corresponding units is possible even when the switch unit has a single-sided configuration, and is not limited to a two-sided configuration.

FIG. 7 shows an example of the header conversion in the third embodiment of the present invention. Utilizing the function of the test cell loopback mechanism and the function of the header conversion circuit, the test cells are made to conduct while periodically changing the logical channels between the line corresponding unit and the switch unit. The test is performed in the same manner as in the first embodiment, but it is necessary to pay attention to the setting of the conversion table because there are a plurality of header conversion circuits on a physically closed loop. The purpose of the present invention is to test all of the plurality of logical channels defined in the line corresponding unit in one test, so that the test cell periodically changes the logical channel while changing over the physically closed loop. Set the conversion table so that it is transferred.

For example, as shown in FIG.
Conversion table 14- in the header conversion circuit 13-1
1, the VPI / VCI value is not converted, and is transmitted with the same value as at the time of input. The conversion table 14-2 in the header conversion circuit 13-2 of the line corresponding unit 11-2 is the first embodiment. If the same conversion is performed, the test of all the plurality of logical channels is completed by one test. Finally, the header conversion circuit 13 of the line corresponding unit 11-2
VPI / VCI value in conversion table 14-2 in -2
Is converted into Z, and the routing tag is set to the output terminal of the switch unit 15 to which the intra-call continuity test circuit 10 is connected.

The setting of the conversion table shown in FIG. 7 is an example, and does not limit the present invention.

FIG. 8 shows another example of the header conversion in the third embodiment of the present invention. In this case, three line corresponding sections 11-1, 11-2, and 11-3 are provided. An example corresponding to a case where a physically closed loop is configured by using the above is shown. In the case where a test is performed using three or more line corresponding units as shown in this figure, by adjusting the number of test cells passing through each conversion table, F1, F1 in FIG.
It is possible to realize different test cell transfer speeds at points F2 and F3.

The three line handling units 11-1 and 11 in FIG.
−2, 11-3 header conversion circuits 13-1, 13-2,
Conversion tables 14-1, 14-2, 14- in 13-3
The number of VC conversions set to 3 is N1, N2, N3 (however,
N1 + N3 = N2), and by setting a test route as shown in FIG. 8, the transfer ratio R1, R2, R3 of the test cells at the points F1, F2, F3 is: R1: R2: R3 = N1 : N2: N3 (4)

By using the above equation (4), it is possible to carry out a test even for an ATM exchange in which line-corresponding parts having different test cell transfer rates coexist. Even when the transmission speed of the test cell of the intra-call continuity test circuit 10 is R <Rmax2, the maximum load test of the line corresponding unit 11-2 is performed by setting the number of VC conversions to N1, N3 <N2. (However, Rmax2 is the line corresponding unit 11-
2 is the maximum cell rate specified in 2. ).

[0046]

[Embodiment 4] FIG. 9 shows a fourth embodiment of the system according to the present invention, in which a continuity test circuit in a communication path, that is, a case where a line-corresponding portion of an ATM switch having no test device is tested. . That is, in the figure, 1 is a test apparatus, 4 is an ATM multiplex line, 8 is a switch unit, and 11c is a line corresponding unit. The line handling unit 11c performs filtering at the cell level together with the cell counting means 6 and the header conversion circuit 13 as in the case of the first embodiment, so that only the test cells generated by the test apparatus 1 and output from the switch unit 8 are output. Has a test cell turn-back mechanism 12a.

In the above configuration, the test cells generated by the test apparatus 1 and input to the line corresponding unit 11c via the ATM multiplex line 4 form a physically closed loop similar to that of the first embodiment. The logical channel is circulated while being periodically changed, and all logical channels are tested. At this time, the setting of the conversion table in the header conversion circuit 13 is the first.
Lastly, when the VPI / VCI value is converted from Y to Z, the routing tag is changed from #N to # 1, and the test cell is transferred to the line corresponding unit 11c again.

Then, the test cell return mechanism 12a excludes the cells having the VPI / VCI value of Z from the test cells so that the test cells are transmitted to the test apparatus 1 without being turned back. Then, the collected test cells are collated to confirm that there is no bit error or the like, thereby confirming the normality of the test for all the logical channels of the line corresponding unit 11c.

[0049]

Fifth Embodiment FIG. 10 shows a fifth embodiment of the system according to the present invention. In this embodiment, a continuity test circuit in a communication path, that is, a case where a plurality of line-corresponding portions of an ATM switch having no test device are tested. Is shown. That is, in the figure, 1 is a test device,
4-2, 4-3 are ATM multiplex lines, 11c-1, 11-
Reference numerals 2 and 11-3 denote line corresponding units, and 15 denotes a switch unit.
The line corresponding section 11c-1 is generated by the test apparatus 1 by performing filtering at the cell level together with the cell counting means 6-1 and the header conversion circuit 13-1 similar to the case of the third embodiment, and is generated by the switch section 15. A test cell return mechanism 12a-1 for returning only the output test cells is provided.

In the above configuration, the line corresponding unit 11c-generated by the test apparatus 1 and transmitted via the ATM multiplex line 4-1.
The test cell input to 1 circulates through a physically closed loop similar to that of the third embodiment while periodically changing its logical channel.
Tests of all logical channels 2, 11-3 are performed. At this time, the setting of the conversion table in the header conversion circuits 13-1 to 13-3 conforms to the third embodiment, but finally, the VPI / VCI value is converted from Y to Z in the line corresponding unit 11-2. In this case, the routing tag is to the line corresponding unit 11c-1 to which the test apparatus 1 is connected, and the test cell is transferred to the line corresponding unit 11c-1 again.

The test cell folding mechanism 12a-1
By excluding the cells having a VPI / VCI value of Z from the test cells, the test cells are sent to the test apparatus 1 without being folded, and the test apparatus 1 checks the collected test cells, By confirming that there is no bit error or the like, the line handling units 11c-1, 11-
The normality of the test for all logical channels 2, 11-3 is confirmed.

As in the case of the third embodiment, it is also possible to carry out a test on an ATM exchange in which line-corresponding parts having different test cell transfer rates coexist. Also, when the transmission rate of the test cell of the test apparatus 1 is equal to or less than the maximum cell rate specified in the line corresponding unit 11-2, the VC
By setting the number of conversions as N1, N3 <N2, it is possible to perform a maximum load test of the line corresponding unit 11-2.

[0053]

As described above, according to the present invention, a line corresponding unit intervening between one ATM multiplex line and a switch unit and performing various functions such as cell counting for each of a plurality of logical channels. in the test mode of the line interface such as an ATM switching system to be tested, and the test device with a test cell generating means and the test cell checking means connected to the switch unit, the line interface unit, folding back the test cell test cell loopback mechanism and 1 Pieces
Each logical test cell of the plurality of line interfaces the VPI / VCI value of the in one of the test cells for each passing該回line corresponding unit
The provision of a header conversion circuit that changes sequentially according to the channel makes it possible to test various functions such as cell counting and header conversion of the line corresponding section over all logical channels in one test, and the test time Can be greatly reduced as compared with the conventional case.

Further, according to the present invention, an ATM switch intervening between one ATM multiplex line and a switch unit for testing a line corresponding unit for executing various functions such as cell counting for each of a plurality of logical channels. In the test method of the line corresponding part such as
A test device having a test cell generating means and a test cell collating means is connected to a switch section, and a test cell return mechanism and one test cell return means for returning a test cell to each of a plurality of line corresponding sections.
The one every time the test cell passes through the line interface of the plurality of
The VPI / VCI value in the test cell of
Since a header conversion circuit that changes sequentially in correspondence with each logical channel is provided, various functions such as cell counting and header conversion of a plurality of line corresponding sections can be tested over all logical channels in one test. This makes it possible to significantly reduce the test time as compared with the conventional case.

Further, according to the present invention, since a plurality of test cells are continuously transmitted from the test apparatus, the test of the line corresponding section using the maximum cell rate specified in the line corresponding section is performed. It can be realized by using a test apparatus having a lower cell generation rate.

Further, according to the present invention, since a plurality of test cells are continuously transmitted from the test apparatus and the number of times of passage of the test cells is changed for each line corresponding unit, a plurality of lines having different speed types are supported. The unit can be tested using one type of test apparatus.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the method of the present invention.

FIG. 2 is a configuration diagram showing an example of a conventional test method.

FIG. 3 is a configuration diagram showing a modification of the first embodiment of the system of the present invention.

FIG. 4 is a block diagram showing another modification of the first embodiment of the present invention.

FIG. 5 is an explanatory diagram showing an example of a header conversion according to the first embodiment;

FIG. 6 is a configuration diagram showing a third embodiment of the system of the present invention.

FIG. 7 is an explanatory diagram showing an example of a header conversion according to the third embodiment;

FIG. 8 is an explanatory diagram showing another example of the header conversion in the third embodiment.

FIG. 9 is a configuration diagram showing a fourth embodiment of the method of the present invention.

FIG. 10 is a configuration diagram showing a fifth embodiment of the method of the present invention.

[Explanation of symbols]

1 ... test equipment, 4,4-1 to 4-3 ... ATM multiplex line,
6,6-1 to 6-3 ... cell counting means, 8,8a, 15 ...
Switch part, 10: Continuity test circuit in communication path, 11, 11
a, 11b, 11c, 11-1 to 11-3, 11c-1
... Line corresponding unit, 12, 12a, 12-1 to 12-3, 1
2a-1: Test cell folding mechanism, 13, 13-1 to 1
3-3: Header conversion circuit, 14, 14-1 to 14-3 ...
Conversion table.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-4-207544 (JP, A) JP-A-5-30128 (JP, A) JP-A-4-124936 (JP, A) JP-A-7- 74749 (JP, A) JP-A-3-71751 (JP, A) JP-A-6-268668 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 12/28 H04L 12 / 26 H04L 12/56

Claims (8)

(57) [Claims] An ATM switch or the like which intervenes between one ATM multiplex line and a switch unit and tests a line corresponding unit which executes various functions such as cell counting for each of a plurality of logical channels. In the test method, a test device having a test cell generating means and a test cell collating means is connected to a switch section, a test cell return mechanism for returning a test cell to a line corresponding section, and one test cell passes through the line corresponding section. said every time
Double the VPI / VCI values in one test cell of the line corresponding unit
2. A test method for a line-corresponding unit such as an ATM switch, comprising a header conversion circuit for sequentially changing the number corresponding to each logical channel . 2. An ATM switch or other line-corresponding unit for testing a line-corresponding unit interposed between one ATM multiplex line and a switch unit and performing various functions such as cell counting for each of a plurality of logical channels. In the test method, a test device having a test cell generating means and a test cell collating means is connected to a switch unit, and a test cell return mechanism for returning a test cell and one test cell are connected to a plurality of line corresponding units, respectively. The VPI / VC in the one test cell each time the signal passes through the line corresponding unit
A test method for a line-corresponding unit such as an ATM switch, comprising a header conversion circuit for sequentially changing an I value in correspondence with each of a plurality of logical channels of the line-corresponding unit. 3. The circuit corresponding to an ATM switch according to claim 2, wherein only one of the plurality of header conversion circuits sequentially changes the VPI / VCI value in the test cell. Test method. 4. A test method for a line-corresponding section such as an ATM switch according to claim 1, wherein a header conversion circuit is provided in the switch section. 5. The test method for a line-corresponding part such as an ATM switch according to claim 1, wherein the test apparatus is provided in the line-corresponding part. 6. The ATM exchange according to claim 1, wherein a test cell generated by an external device connected to the line side from the line corresponding unit and inserted into the line corresponding unit is used. Test method of the line corresponding part of 7. The test apparatus according to claim 1, wherein a plurality of test cells are continuously transmitted from the test apparatus.
A test method for a line-corresponding part such as an ATM switch described in any of the above. 8. The ATM switch according to claim 2, wherein a plurality of test cells are continuously transmitted from the test apparatus, and the number of times of passage of the test cells is changed for each line corresponding unit. Test method for the line corresponding part.