JP3136309B2 - Local area network carrier detection method and apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

This invention relates to a local area network (LA) in which a plurality of stations communicate with another station via a transmission medium for transmitting digital data.
N).

[0002]

2. Description of the Related Art Local area network networks in which a plurality of network stations are interconnected by cables have become widespread. However, wired LANs have the disadvantage of requiring a large amount of cable for interconnecting the stations. Providing such a cable is generally inconvenient and inflexible when trying to change the physical location of the station. Therefore, it has been proposed to use a wireless radio link for a LAN. However, the use of radio communication links has several problems. In particular, LANs used in indoor environments have this problem. One of the problems is multipath attenuation. This is mitigated with spread spectrum communication technology.

[0003]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a local area network station which employs spread spectrum coding for data communication and can achieve fast and reliable carrier detection.

[0004]

SUMMARY OF THE INVENTION Accordingly, the present invention is an analog / digital converter for providing a digital representation of a received signal in a local area network station that receives data symbols encoded on a spread spectrum code and transmitted on a wireless channel. A digital converter, a correlator device coupled to the analog / digital converter for providing a plurality of signal samples, and an integrator and storage device including a plurality of storage registers for storing integral values of the plurality of signal samples; ,
A peak value determining device for determining a maximum value stored in the plurality of storage registers; a total value determining device for determining a total value of the values stored in the plurality of storage registers; the maximum value and the total value A local area network station including a spike quality determining device for providing a quality value signal representing the quality of the received signal so as to be independent of the value, and a carrier detecting device for providing a carrier detection signal in response to the quality value signal. give.

The present invention also provides an apparatus for receiving a signal representing a data symbol encoded in a spread spectrum code and transmitted on a wireless communication channel, comprising: (a) converting the received signal to a digital representation; (B) correlating the digital representation to provide a plurality of signal samples; and (c) averaging the signal samples.
A received signal processing including: (d) determining a peak value and a sum value for the averaged signal sample; and (e) determining a spike quality value based on the peak value and the sum value. Give way.

A feature of the present embodiment is that a carrier detection signal can be used in a multi-antenna system in which two antennas are provided.

An embodiment of the present invention will be described below with reference to the accompanying drawings.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring first to FIG. 1, there is shown a local area network (radio LAN) 10 including a plurality of stations 12, individually designated 12-1 to 12-N. Each station has two antennas 14 and 16 which are polarized in different directions, for example at mutually orthogonal angles. In the figure, these are individually 14-1
To 14-N and 16-1 to 16-N.

The communication between stations 12 is on a single radio channel and uses spread spectrum communication technology (spread).
spectrum communication technology). In the indoor radio LAN of the preferred embodiment, 902-9
A 28 MHz band is used. Another suitable frequency band is around 2.5 GHz.

Referring now to FIG. 2, a block diagram of key portions of transceiver circuit 20 included in a typical station 12 is shown. Station 12 is also conventional, with additional circuitry (not shown), such as LAN
It should be understood that it includes a control device, a memory and a central processing unit. They have no significant relevance to the present invention and are not included in the following description. In a preferred embodiment,
The information is transmitted using an 11-chip spread spectrum code. This code is quadrature modulated with two bits per symbol and a four phase differential phase shift key code scheme (4 phase).
differential phase shift keying coding).

The signals from the antennas 14 and 16 are connected to an RF (radio frequency) stage 26 via a switch 22. This stage 26 includes a 90 degree phase shifter (not shown) to provide in-phase quadrature signals on respective lines 28,30. These lines are connected to an automatic gain control circuit (IGC)
34. The in-phase quadrature output from the automatic gain control circuit 34 is applied to respective analog / digital converters 36, 38 which provide digital output to respective correlators 40, 42. Correlators 40 and 42 (described below) are adapted to correlate the respective input signals of each correlator in accordance with the spread spectrum code used for transmission, and in-phase quadrature spikes on lines 44 and 46, respectively. Give output waveform. It should be appreciated that the preferred embodiment uses an 11-chip spread spectrum code, and that each chip is sampled twice, so there are two samples per symbol. Using these parameters, the correlators 40, 4
2 gives an output spike waveform with a peak every 22 samples.

The in-phase quadrature signal I on lines 44 and 46
And Q are applied to an IQ / polar converter 48. The converter 48 is provided as a look-up table (LUT), converts the quadrature signals I and Q in phase with each other to polar coordinate signals R and φ, and outputs the signals to output lines 50 and 52. Here, R is the length or amplitude (modulus) of the vector, and φ represents the phase angle. The R signal on line 50 is applied to an integrator and register circuit 54 (described below). The register 56 is connected to the timing recovery circuit 58,
8 provides the recovered signal on line 60.
The φ signal on line 52 is applied to data detection circuit 62, which provides the recovered data signal on line 64.

The output of the integrator / register circuit 54 including a plurality of Z registers is applied to a Z-peak value determining circuit 70 and a Z-total value determining circuit 72. These circuits operate on the contents of the registers included in circuit 54 in a manner described below to provide a Z-peak value on line 74 and a Z-sum value on line 76. Lines 74 and 76 are connected to a spike quality determination circuit 78 (described below). Circuit 78 provides a spike quality value signal on line 80. Line 8
0 is connected to a carrier on / off detection circuit 82, which outputs to an antenna selection control circuit 86 via a line 84. Line 80 is also connected directly to antenna selection and control circuit 86 via line 81. The antenna selection and control circuit 86 outputs to the antenna switching control circuit 90 via the line 88. Circuit 90 also receives a signal from synchronization slot control circuit 94 via line 92. An antenna switching control circuit 90 outputs on line 96 to control the operation of switch 22.

The transceiver circuit 20 includes a timing control circuit 98 that provides the necessary and appropriate timing signals to the blocks shown. However, to avoid complications,
The individual connections from the timing control circuit 98 to each block are not shown in FIG.

Referring now to FIG. 3, there is shown a first embodiment of a correlator 100 that can be used for the correlators 40, 42 shown in FIG. The correlator 100 has coefficients C ₀ , C ₁ , C
₂ ,, ...., take the form of a finite impulse response filter (finite impulse response filter) with a C _21. These coefficients are the value stored in the register 102 +
Take 1 or -1. Length 1 used in the preferred embodiment
The spread codes used as the spread spectrum code of 1 are +1, +1, +1, -1, -1, -1, +1, -1,-
It should be understood that they are 1, +1 and -1. Since the preferred embodiment operates with an oversampling factor of 2, this correlator has 22 coefficients, which are in register 102
With the values shown in

The correlator input signal is applied via input line 104 to 2
It is applied to the two-stage shift register 106. These stages are sequentially input sample values S _k , S _k−1 , S _k−2 ,.
_{Stores k-21} . The output of this shift register stage, along with the corresponding coefficients from register 102,
08, the output of which is provided on output line 112 as a correlation output signal.

Referring to FIG. 4, the correlator 40 shown in FIG.
Or an alternative embodiment correlator 12 available as 42
0 is shown. The correlator 120 is the shift register 12
4 and the stages of the register 124 sequentially include sample values S _k , S _k−1 , S _k−2 ,.
_Sk-21 is stored. These shift register stages have an adder 1 depending on whether the corresponding coefficient value is +1 or -1.
26 or an adder 128. Adder 126,
The outputs of 128 are each connected to summer 130 as positive and negative values. Adder 130 provides a correlator output signal on output line 132.

The + used in the correlator shown in FIG. 3 and FIG.
Note that coefficients of 1 and -1 provide a simple means to achieve.

Referring to FIG. 5, the integrator / register circuit 54 and the Z-peak value determination circuit 7 shown in FIG.
0, 72 and a more detailed diagram of the spike quality determination circuit 78 is shown. In connection with FIG. 5, it should be understood that short lines across some of the interconnect lines indicate the number of bit-carrying conductors included in the line.

The 5-bit input line 50 is connected to a leaky integration circuit (leak
y integrator circuit) 140. This circuit 140 includes an adder 142, a delay circuit 144, and a multiplier 146. The adder 142 is a multiplexer circuit 14.
4 is connected to the input end of the
It is coupled to the positive input of adder 142 via 48 and to multiplier 146 via line 150. Multiplier 1
46 is applied with a constant 1/32. 146 output line 15
2 is connected to the negative input terminal of the adder 142. The input line 50 is connected to the positive input terminal of the adder 142. The multiplexer circuit 144 is also connected to a block of 22 registers 156 via a bidirectional 10-bit line 154. In the figure, these registers are individually indicated as 156-1 to 156-22. The output terminal of the register 156 is connected to a bit deletion circuit (bit de
letion circuit) 160. This circuit 160
Removes the two least significant bits and provides an 8-bit output on 8-bit line 162. The manner in which the multiplexer circuit 144 and registers 156-1 through 156-22 operate provides an effective delay of 22 sample intervals (per symbol period) between adder 142 and lines 148 and 150. The multiplexer circuit 144 operates under the control of the timing control circuit 98 (FIG. 2).

Line 162 (FIG. 5) is connected to the input of Z-peak value determining circuit 70 and the input of Z-sum value determining device 72. This will be described below. Line 162
Is connected to the input terminal of the adder 170 whose output is connected to the input terminal of the delay circuit 172. The output of circuit 172 is applied to Z-peak value determination circuit 70 via feedback line 174.
Is connected to the second input terminal. Z-peak value determination circuit 70
Operates only while there are 22 samples on line 162.
The Z-peak value determination circuit 70 calculates the overflow prevention value 20.
Perform addition under 47. That is, the Z-peak determination circuit 70 has 2047 as the maximum value. Delay circuit 1
The output of 72 is also connected to a bit deletion circuit 176. This circuit 176 eliminates the two least significant bits and provides a 9 bit output. This 9-bit output provided on line 76 represents the Z-sum value. Line 162 is also connected to Z-peak value determination circuit 70, which selects the largest of the signals on line 162 for 22 table intervals (one symbol period).

8 bit lines 74 (Z-peak value) and 9
The bit line 76 (Z-sum value) is connected to the spike quality determination circuit 7.
8 input terminals. The 8-bit line 74 is connected to the input terminal of the shifter circuit 190, and the 9-bit line 76 is connected to the input terminal of the shifter circuit 192. Shifter circuits 190 and 192 are interconnected by control line 194. Shifter circuits 190, 192 perform the addition by shifting their contents to the left, until their contents are 0, 1 until the most significant bit of the Z-peak or Z-sum value is at the leftmost position. Arrangements are made such that the operations are shifted together by one, two, three or four bits. 4
The 4-bit output of shifter circuit 190 on bit line 196 and the 5-bit output of shifter circuit 192 on 5-bit line 198 are applied as address signals for addressing spike quality readout table 200. The structure of the spike quality reading table 200 is shown in Table 1. In Table 1, numbers 0 to 15 in the horizontal direction represent Z-peak values, numbers 0 to 31 in the vertical direction represent Z-sum values, and numbers 0 to 15 in the table represent spike quality (SQ) values. . Number 1
5 represents the worst spike quality (no signal received). Table 1 Peak value 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ――――――――――――――――――――――――――――――― ―――― Sum value 31 0 0 0 0 0 0 0 0 0 0 0 0 1 2 4 7 30 0 0 0 0 0 0 0 0 0 0 0 0 1 3 6 7 29 0 0 0 0 0 0 0 0 0 0 0 1 2 4 7 8 28 0 0 0 0 0 0 0 0 0 0 0 1 3 5 7 8 27 0 0 0 0 0 0 0 0 0 0 0 2 4 6 8 9 26 0 0 0 0 0 0 0 0 0 0 1 2 5 7 9 10 25 0 0 0 0 0 0 0 0 0 0 1 3 6 7 10 10 24 0 0 0 0 0 0 0 0 0 0 2 4 7 8 10 11 23 0 0 0 0 0 0 0 0 0 1 2 5 8 9 11 11 22 0 0 0 0 0 0 0 0 0 1 3 6 9 10 12 12 21 0 0 0 0 0 0 0 0 1 2 4 7 9 10 12 13 20 0 0 0 0 0 0 0 0 1 3 5 8 10 11 13 14 19 0 0 0 0 0 0 0 0 2 4 6 9 11 12 13 14 18 0 0 0 0 0 0 0 1 2 5 7 9 11 12 14 14 17 0 0 0 0 0 0 0 1 3 6 8 10 12 13 14 14 16 0 0 0 0 0 0 0 2 4 7 9 11 13 14 14 14 15 0 0 0 0 0 0 1 2 5 8 10 12 13 14 14 15 14 0 0 0 0 0 0 1 3 6 9 11 13 13 14 15 15 13 0 0 0 0 0 0 2 3 7 10 12 13 14 15 15 15 12 0 0 0 0 0 0 2 4 9 11 13 14 14 15 15 15 11 0 0 0 0 0 1 3 5 10 12 14 14 15 15 15 15 10 0 0 0 0 0 1 3 6 12 14 14 15 15 15 15 15 9 0 0 0 0 0 2 4 7 14 14 15 15 15 15 15 15 8 0 0 0 0 1 2 5 8 14 15 15 15 15 15 15 15 15 7 0 0 0 0 1 3 6 9 15 15 15 15 15 15 15 15 6 0 0 0 0 2 3 7 10 15 15 15 15 15 15 15 15 5 0 0 0 1 2 4 8 12 15 15 15 15 15 15 15 15 15 4 0 0 1 1 3 5 9 13 15 15 15 15 15 15 15 15 3 0 0 1 2 3 6 10 15 15 15 15 15 15 15 15 15 2 0 0 2 3 4 7 11 15 15 15 15 15 15 15 15 15 15 1 0 1 2 3 5 8 13 15 15 15 15 15 15 15 15 15 0 0 1 3 4 6 9 15 15 15 15 15 15 15 15 15 15 ―――――――――――――――――――――――――― ――――――――− Peak value 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

According to Table 1, the 4-bit output of the spike quality reading table 200 is applied via a 4-bit output line 80. It should be appreciated that a spike quality value of 15 indicates very good signal reception quality, while a spike quality value of 0 indicates that no signal is received. The intermediate spike value indicates an intermediate signal quality reception state.

The circuit shown in FIG. 5 operates only when the transceiver circuit 20 is in the reception mode, and is partially processed for each sample (in this embodiment, processed at a speed of 22 MHz) and partially for each symbol. (In this embodiment, processing is performed at a speed of 1 MHz.) This reception mode processing starts 36 symbol periods after the antenna slot period starts. When no carrier signal is detected by the transceiver circuit 20, the antenna switching control circuit 90 (FIG. 2) switches the switch 22 between the state A slot interval (the antenna 14 operates) and the state B slot interval (the antenna 16 operates). Understand that it is possible to switch between them. Each antenna slot interval has a length of 40 symbol periods. When a carrier signal is detected, the antenna switching control circuit 90 operates over a further antenna slot interval.
During this period, the circuit provides a spike quality value for each of states A and B, as will be described below. This switches or maintains a state with good good spike quality whether the state is A or B while the received data frame is received. The transceiver circuit 20 always operates in the state A during the transmission period.

With the above in mind, the processing of the circuit of FIG. 5 will be described. While the antenna switching control circuit 90 alternates between states A and B, the circuit of FIG. 5 is controlled by the timing control circuit 98 (FIG. 2) for the last four symbol periods of the slot (which is 4 × 22 = 88). (Corresponding to a specimen). The slots each have a length of 40 symbol periods as described above. These four symbol periods begin after a lapse of thirty-six symbol periods from the start of each antenna slot interval. During these four symbol periods, leaky integrator circuit 140 (FIG. 5) and register 156 undergo processing. By this processing, the successive samples R are stored in the registers 156-1 to 156-1.
A variable average value of the rectified spike waveform is calculated by adding the contents to the contents of 6-22. Leakage integrator circuit 14
0 sample values R in addition to the value Z ₁ of the preceding register 156-2 was 31/32 times, stores the new Z ₁ value in register 156-1. Next, the previous register 156 multiplied by 31/32
The sample value R _{k + 1} is added to the value Z ₂ of −2, and the new value of Z ₂ is stored in the register 156-2. In this way, the remaining registers 156-3 to 156-22 are sequentially processed. After processing registers 156-22, leakage integrator circuit 140
Returns again to the processing of register 156-1 and continues in this manner as long as it is active. More specifically, in the 4-symbol interval before the end of the antenna slot, the correlator output sample is rectified (having a modulus value) and added to the contents of the 22 registers 156 as follows. The 1,23,45,67th sample is added to register 1. The 2, 24, 46, and 680,000th samples are added to register 2. The 3, 35, 47, and 690,000th samples are added to the register 3. The 22nd, 44th, 66th, and 88th samples are added to register 22.

Thus, the contents of registers 1 to 22 correspond to 22 samples of the signal. This signal is four times the average value of the rectified spike waveform.

At the end of each four-symbol period, that is, at the end of the antenna slot interval, the Z-peak value determining circuit 70 and the Z-sum total value determining device 72 undergo processing once, respectively. This provides a 4-bit spike quality value output signal on output line 80. Therefore, a spike quality value signal is derived once at the end of one antenna slot interval based on the 22 register values Z found by integration during four symbol periods.

In summary, after processing, the contents of the 22 registers 156-1 to 156-22 correspond to 22 samples of the signal. This signal is four times the average value of the rectified spike waveform. The register with the highest value gives the Z-peak value determined by the Z-peak value determination circuit 70. In the Z-sum total value determining device 72, 22 registers 15
6 are summed to give the Z value. As is evident from Table 1, the greater the Z-peak value compared to Z-Sumou,
High spike quality value. As will be described in more detail later, if the spike quality value based on these four symbols exceeds a predetermined threshold, a carrier on (ON) detection signal is sent to the antenna slot by carrier on / off detection circuit 82 (FIG. 1). Given at the end of the interval. If the correlator 40,
If the correlation performed by 42 (FIG. 2) gives a good spike waveform in successive symbol periods, the Z-peak value is relatively high and the spike quality value is above the threshold.

Referring now to FIG. 6, the carrier on /
An embodiment of the off detection circuit 82 (FIG. 1) is shown. The spike quality value signal is applied via line 80 to a switch 210 having two interconnected switch arms 212 and 214. Of course, when provided as an actual device, the switch 210 is an electronic switch. The switch arm 212 contacts either the first terminal 216 connected to the input terminal of the comparator 218 or the unconnected second terminal 220. The switch arm 214 is connected to either the unconnected first terminal 222 or the second terminal 224 connected to the input terminal of the comparator 226. An output terminal of the comparator 218 is connected to an input terminal of an OR (OR) gate 228.
The output terminal of the OR gate 228 is connected to the input terminal of the carrier ON / OFF mode control circuit 232 via a line 230 and the control input terminal 2 of the switch 210 via a line 231.
34. The output of comparator 226 is line 240
To the input of the carrier on / off mode control circuit 232 and further to another control input 244 of the switch 210 via line 242.

It should be appreciated that the carrier on / off detection circuit 82 has two different thresholds. Initially, switch arms 212 and 214 of switch 210 are in the lower, dashed position and are in contact with terminals 220 and 224, respectively. If a spike quality value of 3 or greater is detected, comparator 226 is activated to provide an output to 232 and carrier on / off mode control circuit 232 provides a carrier detect signal on line 84. Also, the switch 21 via the line 242
0 is activated to the position where the switch arm 212 contacts the terminal 216 and the switch arm 214 contacts the terminal 222. If the spike quality value is 0 during the transmission period
Then, the comparator 218 is activated via the OR gate 228 and provides an input signal to the carrier on / off mode control circuit 232 to indicate that the carrier is no longer present. Of course, this occurs in the time interval after the spike waveform disappears. This is a one-leakage integrator circuit 140 (FIG. 5)
Is the result of the integration given by A special postamble character is detected, usually at the end of the transmission, and activates OR gate 228 via line 250.

It should be appreciated that the preferred embodiment performs integration over multiple periods of four symbol periods, so that very reliable carrier-on detection can be achieved under various signal damages.

The use of spike quality values for antenna selection will be described with reference to FIGS. 7A to 7C, the first waveform (1) indicates the state of the antenna switch 22 (A or B). The second waveform (2) represents the carrier activity and the third waveform (3) represents the carrier on / off signal provided by the carrier on / off detection circuit 82 (FIG. 2).

Table 2 below shows the state of the antenna selection and control circuit 86 (FIG. 2) after carrier detection has occurred. Here, SQ is a spike quality value, and SQ (2-3) is a spike quality value generated during two or three antenna slots. Table 2 ―――――――――――――――――――――――――――――――――― SQ (2-3) | Operation ―――― ―――――――――――――――――――――――――――――――― (a) The first SQ is better than the second SQ value. | Switch to first SQ antenna. (B) The first SQ is worse than the second SQ. | Wait for third SQ slot. (B1) The second SQ is better than the third SQ. | First switch to SQ antenna. (B2) The second SQ is worse than the third SQ. | Switch to first (third) SQ antenna | ――――――――――――――――――――――――――――――――――――

The use of spike quality values over a few antenna slot intervals ensures that a proper choice can be made in all situations. LAN of FIG.
10 has a synchronizer, so that the synchronization slot circuit 94 (FIG. 2) in each station ensures synchronization of the antenna slot spacing of all stations 12, thereby providing synchronization between all stations. .
Each transmission is controlled so as to start at the start of an antenna slot. Thus, when a carrier signal is present from the beginning of an antenna slot, the automatic gain control is stabilized in the receiving stage of the transceiver by the end of that antenna slot. Then, a clean spike waveform is given so that the spike quality value exceeds a threshold value (3 in this embodiment) determined for carrier detection. Referring to situation (a) in Table 2 and FIG. 7 (a), if the detected first spike quality value is better than the second spike quality value, the selection control circuit 86 switches to the first antenna. Do. This is illustrated in FIG. 7 (a) as an example of switching to state B, in which case the antenna 16 is used for data reception.

On the other hand, if the first spike quality value is worse than the second spike quality value, the antenna selection and control circuit 86 waits for the third antenna slot, and makes further comparison using the spike quality value ( (See (b) of Table 2). In the situation (b1), it is determined that the second spike quality value is better than the third spike quality value. In this case, the antenna selection and control circuit 86 switches to the antenna giving the second spike quality value for data reception. (See FIG. 7B). Here, a state in which the state is switched to the state A corresponding to the antenna 14 for data reception is illustrated. In the situation (b2), it is determined that the second spike quality value is worse than the third spike quality value. There is no more switching (see FIG. 7 (c)). From this figure, it can be seen that state B is maintained for data reception.

[0036] The synchronization of the above-mentioned stations may be impaired, and the carrier signal may rise not at the start of the antenna slot but in the middle. In this case, the automatic gain controller on the receiving side is not stabilized at the end of the antenna slot.
Thus, the detected first spike quality value indicates that there is not a sufficiently good reception condition. However, in subsequent antenna slots, an appropriate spike quality value is determined at the end of the slot. In these cases, the situation (b) in Table 2 is obtained.

Each data transmission data frame used in the preferred embodiment includes a preamble containing a continuous multiple symbol sequence for a total of five antenna slots. In four of these slots, it is guaranteed that carrier detection and correct antenna selection are performed by the above procedure.
The fifth antenna slot spacing can be used for adjusting other reception functions.

After carrier detection and antenna selection (when the alternate switching between the states A and B is completed), the circuit of FIG. 5 and the timing control circuit 98 are processed for each symbol interval, and the registers 156-1 to 156-22 are processed.
Correspond to 22 samples of one signal waveform. This signal waveform is 32 times the variable average of the rectified spike waveform. If the spike waveform disappears, but receives a postamble character, the spike quality value (SQ) will be zero, resulting in a carrier off detection.

It should be noted from the description of the preferred embodiment that the processing of spike quality values is independent of the reception level. Thus, the spike quality value works over a wide range of reception levels. The spike quality value depends on the quality of the received spike waveform from the ratio of the Z-peak value to the Z-sum value. Z
-This ratio between the peak value and the Z-sum value depends on the relationship between the signal level and the level of noise, interference and channel distortion. This ratio has therefore an important bearing on the reliability of the data transmission. The spike quality value is based on this ratio and is therefore an applicable criterion for selecting the best antenna. Carrier on detection occurs when the carrier signal is received sufficiently satisfactorily. The spike quality method guarantees high reliability for carrier-on detection even in the presence of any kind of deterioration. This reliability can be achieved by performing carrier-on detection through a spike quality determination condition based on integration over only four symbol periods. AGC
The reliability of carrier-on detection within 4 symbols after stabilization is important for the whole communication under various adverse conditions. Also, circuit economy is achieved. This is because the integrator and register circuit 54 of FIG. 2 can be added to the timing recovery.

Another advantage of the above embodiment is that each station is provided with two antennas with a selection means for selecting one of the two antennas at the start of receiving a data frame. This is an improvement over the use of a single antenna. This is because the probability that both antennas will experience attenuation or disturbance is much smaller than with a single antenna. In the above embodiment,
Providing fast and reliable antenna selection based on appropriate quality measurements to obtain data transmission reliability dependent on basic reception conditions such as signal / noise ratio, signal / interference ratio, channel distortion, etc. .

Design changes can be made within the scope of the claims. That is, although a spread spectrum code employing 11 chips and 2 samples / chip has been described, a spread spectrum code employing a different number of chips and a different number of samples / chip may be used. In addition, the form of modulation may be other than the 4DPSK coding method. Thus, for a one-bit-per-symbol spread-spectrum code, only one correlator is required and its output can be directly connected to an integrator and register circuit without the need for a coordinate transformation block (IQ to polar). In another design change, instead of polarizing the two antennas, they can be steered in two different directions. In addition, transmission frequencies higher than radio frequencies for radio transmission links using spread spectrum codes,
That is, 3000 GHz or more can be used. For such frequencies, of course, the antenna may be of a different type than that used for radio frequencies.

[Brief description of the drawings]

FIG. 1 is a diagram showing a radio LAN.

FIG. 2 is a block diagram of a part of a transceiver unit of the LAN network station.

FIG. 3 is a first embodiment of a correlator that can be used in the circuit shown in FIG. 2;

FIG. 4 is a second embodiment of a correlator that can be used in the circuit shown in FIG. 2;

FIG. 5 is a detailed diagram of the integrator / register block shown in FIG. 2;

FIG. 6 is a detailed diagram of a carrier on / off detection block shown in FIG. 2;

FIG. 7 is a waveform chart for understanding the operation of the present invention.

[Explanation of symbols]

 Reference Signs List 10 local area network 12 network station 14, 16 antenna 20 transceiver circuit 82 carrier on / off detection circuit 100, 120 correlator

 ──────────────────────────────────────────────────続 き Continuation of the front page (73) Patent owner 596077259 600 Mountain Avenue, Murray Hill, New Jersey 07974-0636 U.S.A. S. A. (72) Inventor Hans van Driest The Netherlands, 3721 M.J.Bilsau Ven, La Brandenberger Weg 4

Claims (4)

(57) [Claims] 1. A local area network station receiving data symbols encoded on a spread spectrum code and transmitted on a wireless channel, comprising: an analog / digital converter for providing a digital representation of the received signal;
A digital conversion device; a correlator device coupled to the analog / digital conversion device for providing a plurality of signal samples; an integrator and storage device including a plurality of storage registers for storing integral values of the plurality of signal samples; A peak value determining device for determining a maximum value stored in the plurality of storage registers; a sum value determining device for determining a total value of values stored in the plurality of storage registers; A local area network station comprising: a spike quality determining device for providing a quality value signal indicating the quality of the received signal so as to be independent of the sum value; and a carrier detecting device for providing a carrier detection signal in response to the quality value signal. . 2. An apparatus for receiving a signal representing a data symbol encoded in a spread spectrum code and transmitted on a wireless communication channel, comprising: (a) converting the received signal to a digital representation; Providing a plurality of signal samples by correlating the digital representation; (c) averaging the signal samples; and (d) determining peak and sum values for the averaged signal samples. And (e) determining a spike quality value based on the peak value and the sum value. 3. An apparatus for receiving a signal transmitted on a wireless communication channel representing data symbols encoded in a spread spectrum code, comprising: (a) converting the received signal to a digital representation; Providing a plurality of signal samples by correlating the digital representation; (c) averaging the signal samples; and (d) determining peak and sum values for the averaged signal samples. (E) determining a spike quality value based on the peak value and the sum value; and (f) detecting reception of the carrier signal using the spike quality value. Method. 4. A method of operating an apparatus including a plurality of antennas for receiving a signal representing a data symbol encoded in a spread spectrum code and transmitted on a wireless communication channel, the method comprising: (a) receiving the received signal; Converting the signal to a digital representation; (b) correlating the digital representation to provide a plurality of signal samples; (c) averaging the signal samples; and (d) the averaged signal. Determining a peak value and a sum value for the sample; (e) determining a spike quality value based on the peak value and the sum value; and (f) receiving a signal using the spike quality value. Selecting one of the plurality of antennas to perform the operation.