JP3135212B2 - Individual protection transistor to reduce injection current from one PN junction island to another - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having an electric device formed on a PN junction isolation island, and in particular, a separate protection transistor adjacent to one of the islands is injected from one island into the substrate. An integrated circuit that substantially prevents parasitic currents from being collected by other islands.

[0002]

BACKGROUND OF THE INVENTION When transistors formed in PN junction isolation islands are used to drive inductive loads, instantaneous or repetitive forward biasing of the islands can occur. Also, the forward bias of the first integrated circuit island tends to create a parasitic bipolar transistor having an emitter corresponding to the first island and a collector corresponding to a nearby second PN junction isolation island. . This results in a number of unwanted effects on the second island, such as spurious currents that can cause malfunctions of devices formed on the second island, and increased power consumption and overheating of the integrated circuit. Can occur. When the devices of the first island carry substantially more current than the smaller surrounding islands,
This effect on nearby islands is particularly troublesome.

[0003]

To remedy this problem, power devices in large islands are designed to inject a small amount of current into the substrate when the PN junction separating the islands is forward biased. Designed. For an example of such a structure, Mayra, issued July 3, 1984, assigned to the same assignee as the present invention.
nd, U.S. Pat. No. 4,458,158.

Alternatively, large islands that tend to inject electrons into the substrate include structures that block such injected carriers from adjacent small islands that attempt to collect the injected carriers. Such a structure is disclosed on May 3, 1977, assigned to the same assignee as the present invention.
Genesi, U.S. Pat. No. 4,027,32, issued 1 day.
No.5.

In that patent, a high power diode operates in a full wave bridge rectifier with the anode connected to the most negative voltage, in this case ground. The island containing the power diode is made from an N-type epitaxial material serving as the cathode,
It is formed on a P-type substrate that acts as an anode. When the diode is forward biased, electrons injected into the substrate are substantially prevented from being collected by adjacent epitaxial islands due to the surrounding annular N-type ring, but separated from the diode islands. ing. Both the N-type ring and the anode, ie, the P-type substrate (and the separating wall) are electrically connected together.

[0006] Three other such "protection" structures are shown in FIGS. 1, 2 and 3 herein. In both FIGS. 1 and 2, the large island 10, that is, the island that is likely to be forward biased to inject electrons into the substrate 12, is intended to include a power diode or transistor and is provided with a separate annular ring. It is surrounded by an N-type ring or moat 14.

The protective N-type ring 14 in FIG. 1 is electrically connected to a positive bias voltage, so that the ring 14 is preemptive of electrons.
Island 19 that acts as a collector and surrounds the electrons
Let out from.

In FIG. 2, the protective N-type ring 14 is simply electrically connected to the adjacent outer P-type isolation wall 16. Again, the ring 14 serves to collect the injected electrons, in which case the electrons must flow to the ring 14 and this current again flows to the substrate 12 and through the annular P-type isolation wall to the ground point of the circuit. Flows to Operation in this configuration is based on the premise that the radial flow of current in the substrate 12 creates a field that results in the recombination of excess electrons, thereby preventing electrons from reaching the island 19 adjacent to the large island. Have been. The field seeks to limit the excess electrons to the portion of the substrate 12 below the large island 10 and the recombination current must flow to ground via the grounded isolation wall 18.

A third "protection" structure is shown in FIG. 3 herein. Large epitaxial islands 20, which are forward biased and tend to inject electrons into substrate 12,
Power diode or transistor in island part 2
0a. Big epitaxial
The power device in island 20 is island 2
0 is expected to periodically apply a forward bias to the island-to-substrate PN junction 20/12, at which time the injected electrons are injected into the adjacent epitaxial N-type.
It is about to be collected by the island 22. A heavily doped N-type buried layer 24 is formed at the bottom of the island 20 and the buried layer 24 is
It comes into contact with the system of the type wall 26, which partitions and separates the island portions 20a and 20b inside the island 20.

[0010] A bipolar transistor 28 is formed in the island portion 20b so as to act in a protective role to diverge the carriers injected into the substrate 12 so as not to reach the adjacent islands 22. P-type region 29 and N
The -type region 31 serves as the base and collector, respectively, of the protection transistor 28 in which the lightly doped N-type island portion 20b is the emitter. Conductor 3
2 connects the collector 31 of the protection transistor 28 to a P-type isolation wall 34 that separates the island 20 from the island 22. The isolation wall 36 on the opposite side of the island 20 is connected to ground, the lowest DC bias voltage circuit point.

The island portion 20b and the protection transistor 28 are disposed on the left (in the figure) away from the separation wall portion 34 and the island 22 so as to be protected. These relative positions and connections are determined by adjacent islands 22.
Of the PN junction 20/12 that is forward biased resulting in reduced collection of injected charge to the depn (deb
easing). In operation, this structure produces a current flowing through the conductor 32 and the substrate resistance through the protection transistor 28, strongest at the isolation wall 34, gradually weaker along the buried layer 24, and finally most at the isolation wall 36. It is believed that the PN junction 12/20 is weakly debiased, so that the implantation is strongest in the region far from the protected island 22.

FIG. 4 shows an equivalent circuit of the structure of FIG. 3, where the PN junction 20/12 is shown as a diode 38 and the parasitic transistor 39 is a P-type substrate 1.
2 and corresponding base and N-type implant islands 20
Is an island 22 having an emitter and the collector being protected. Resistance 35 (35a, 35b and 35
c) The bias release current is applied from the separation wall portion 34 to the substrate 12.
And the substrate resistance under the island 20 flowing through the conductor 32 to the collector of the protection transistor 28.

It is an object of the present invention to provide a new and improved means for protecting devices formed in a PN junction isolation island from the collection of current injected into the substrate by another forward biased island. To provide.

[0014]

SUMMARY OF THE INVENTION An integrated circuit chip is formed on a semiconductor substrate of one conductivity type, and a first PN junction isolation island of an opposite conductivity type is formed on and surrounded by the substrate. . As used herein, the term "substrate" refers to a semiconductor that is more heavily doped than the other, for example, one type of conductive adjacent region, including a separating wall region between islands of the opposite conductive type. It is meant to include body parts.

[0015] The present invention provides a method in which a first island is instantaneously forward biased with respect to a substrate surrounding the first island, and at least a second PN junction isolation island of opposite conductivity type is formed in the substrate to form a first island. , So that the second island seeks to collect carriers injected from the forward biased island at the first instant.

The integrated circuit chip further includes a first PN junction isolation island of the opposite conductivity type formed in and surrounded by the substrate. At least a second PN junction isolation island of the opposite conductivity type is formed in the substrate on one side of the first island, the second island being a first instantaneously forward biased island. Attempts to collect the carrier injected from.

A third island of PN junction isolation of the opposite conductivity type includes a protective vertical bipolar transistor. The protection transistor has a base of one conductivity type and has a collector and an emitter of opposite conductivity types. A ground conductor of the circuit connects a ground point in the integrated circuit to the base region of the protection transistor and the isolation wall of the substrate opposite the first island. One conductor connects the emitter of the protection transistor to the opposite conductivity type portion of the first island and another conductor connects the collector of the protection transistor to the isolation wall of the substrate on one side of the first island. Connect to

The third island is one of the first islands.
Placed adjacent to one side, but another effective location for the third island is adjacent to yet another side of the first island, for example, the side joining said one side to the opposite side Is desirable. The base of the protection transistor is formed on a surface portion of the chip of the third island, and the emitter of the third island is a region of the opposite conductivity type formed on the chip surface portion of the base.

However, a preferred protection transistor structure has a heavily doped buried layer of the opposite conductivity type formed in a third island which abuts one conductivity type substrate and acts as the collector of the protection transistor. . Thus, this one conductivity type buried layer extends from the opposite conductivity type buried layer forming the base of the protection transistor to the third island, and the heavily doped opposite conductivity type plug region becomes It extends from the chip surface through a third island to a buried layer of the opposite conductivity type. The other conductor is connected to the third island by contacting the plug region.

The present invention is directed to a first island that is implanted by favoring implantation in one direction away from the second island, and to prevent the injected charge from diffusing toward the second island. The amount of current parasitically collected is reduced by providing a delay field below.

In yet another preferred embodiment, a pair of such large alternating implanted transistors and their corresponding previously described protection transistors are integrated into a single integrated circuit chip and the two Large transistors each have sides adjacent to each other but separated by a portion of a substrate of one conductivity type. These two
The two large islands are expected to drive the inductive load and turn on alternately. In this case, the collectors of a pair of protection transistors are resistively connected through the substrate, and the protection transistor associated with the large on-transistor is about to turn on in the opposite direction, ie, what was the collector is the protection transistor Trying to be the emitter of
As a result, a current is generated between the collectors of the two protection transistors in a direction to reinforce the parasitic current from the large island on the injection side to the small island.

In contrast to the prior art protection transistors, which have a high current gain in the opposite mode of operation, the preferred protection transistor of the present invention has a lower current gain in the opposite direction, and therefore has a large transistor that is alternately injected. Provides a greater protection effect in an integrated circuit having

In the preferred embodiment, the protection structure of the present invention, which occupies the space between the PN junction-isolated small (transistor) and the injection island in which the protection transistor is protected, is a complete structure in an integrated circuit chip. It occupies approximately the same area, but at the same time produces a greater physical separation of the implanting island and the protected island, leading to a further increase in protection efficiency.

[0024]

DETAILED DESCRIPTION OF THE INVENTION The integrated circuit of FIG.
It is formed on a silicon substrate 50. Large N-type islands 52 include power devices (not shown) such as bipolar transistors, field effect transistors (FETs) or diodes. At some moment during the operation of this power device, the N-type island 52 has a P
It becomes negative with respect to the type substrate 50, this negative voltage source being represented by the generator 53. The momentary negative voltage applied to the island 52 results in imposing a forward bias on the PN junction between the island 52 and the substrate 50, resulting in the injection of minority carriers (electrons) into the substrate 50.

To the right of the large island 52 (in the figure) are several relatively small N-type islands 54, including devices with small signals (not shown). The small device islands 54 are connected to a positive voltage source to reverse bias and isolate each small island 54 with respect to the substrate 50, which is held at the largest negative bias potential, ie, ground. The protection NPN transistor 55 has an epitaxial island 56 to the right of the large island 52 (shown).
Formed.

The above structure first forms a lightly doped N-type epitaxial layer on a P-type substrate 50 and then via an epitaxial layer 51 to form isolation walls 61, 62, 63 and 64. By selectively diffusing P-type impurities. The N ⁺ buried layer 66 and the P-type buried layer 68
It is formed by a well-known process before or during the growth of the epitaxial layer 51.

The island 56 of the protection transistor 55 additionally has an annular, heavily doped N ⁺ wall 72 formed therein to seal the epitaxial pocket 70 by another selective diffusion. An annular N ⁺ plug contacts N ⁺ buried layer 66 to form an inner region 75 of epitaxial material completely surrounded by N ⁺ regions 72 and 66. Within the interior region 75 of epitaxial material, an annular P-type wall 74 reaches and contacts the P-type buried layer 68 and a smaller epitaxial pocket 76.
To form The N ⁺ emitter region 78 is formed in the chip surface portion at the center of the pocket 70. Transistor 55
Have low current gain in both forward and reverse operating directions.

The annular N ⁺ plug 72 is made of a conductor 81, 83
An outer P-type separating wall region 62 adjacent via
63 is electrically connected. The N-type implantation island 52 is connected to the protection transistor 5 through the conductor 87.
5 is electrically connected to the emitter region 78. The P-type wall 74 of the protection transistor 55 is connected to the ground of the integrated circuit, ie, the lowest bias voltage point.

In the equivalent circuit portion of FIG.
Represents the PN junction between the implant island 52 and the substrate 50. The resistance of the substrate 50 below the implantation island 52 is represented as a discrete resistance 92. When the injection island 52 is forward biased with respect to the circuit ground, charge injection occurs across the PN junction 51 of the island 52.

The location of the ground contact in the isolation wall region 61 causes a progressive de-biasing of the junction 51 from left to right (in the figure). In other words, the discrete resistor 92
The injection current through the resistance path in the substrate 50 as represented by ## EQU1 ## causes a step-up in the forward bias of the PN junction 51 from right to left. This is the separation wall area 6
1, the injection current is maximized at the PN junction 51. Thus, the implant is preferentially generated in one direction, i.e., away from the N-type island 54 where the reverse bias is imposed, and towards the isolation wall region 61.

When the island 52 becomes negative and a forward bias is imposed with respect to the substrate 50, the protection transistor 5
5 emitter region 78 becomes negative with respect to base 68;
Turning on transistor 55 to shunt current from the base / emitter junction of parasitic transistor 94, thereby rendering transistor 94 inoperative, is most easily seen by the equivalent circuit of FIG. The collector current from the protection transistor 55 flows to the resistive substrate region below the implant island 52, which is here shown as a lumped resistor 92, which allows the injected current to flow to a low impedance circuit ground 96 in the isolation wall region 61. Reach.

The protection transistor of the present invention creates a delay field for the injected charge in the substrate below the implanted island, and can also be used in other ways, such as from "epitaxial island to other," filed concurrently with the present invention and assigned to the same assignee. Epitaxial islands (A) with adjacent asymmetric structures to reduce the concentration of current injected into the islands
N EPITAXIAL ISLAND WITH A
DJACENT ASYMMETRICAL Stru
REDUCE COLLECT against CTURE
ION OF INJECTED CURRENT F
ROM THEISLAND INTO OTHER
ISLANDS) "operates with comparable efficiency to the protective structure described in this patent application. This patent application is filed concurrently with the present application and is hereby incorporated by reference for further consideration of the relationship between the protective features and the structural features of the protective device.

In the plan view of FIG. 7, the semiconductor integrated circuit chips 100 are shown in FIG.
Includes the same features shown in FIG. 5 in the upper half (in the figure).

In the lower half of FIG. 7, corresponding elements reflecting the ones in the upper half of this feature are indicated by corresponding numbers with the addition of 50; for example, the upper large island is 52 and the lower The large island is 102.

In FIG. 7, a P-type separation wall region 6 is shown.
On 1, 62 and 63 are shown metal strips 61m, 62m and 63m, respectively, which are in electrical contact. The conductor 81, shown most conveniently as a wire in the figure,
83 and 87 are more conveniently implemented in practice as well-known selectively deposited metal strips. The lower large island 102, which includes a power transistor (not shown) in the central region, is positioned on the upper side adjacent to and separated from the P-type isolation wall 103 from the side below the large island 52. Is done. N- for protection
Island 105 of the P-type is adjacent to P-type island wall 112, thereby providing a larger island 10
Separated from two. The island 102 includes the conductor 13
7 is connected to the collector 128. The injection islands 52 and 102 of this large power transistor
Are placed in parallel as a usual way to physically separate power devices from the smallest possible device island 54.

To clearly illustrate the relationship of the elements in FIGS. 5 and 7, protection transistors 55 and 105 are shown much larger than necessary for the size of large islands 52 and 102. In effect, protection transistors 55 and 105 appear to be long but narrow devices located between the large island on the injection side and the small island 54 to be protected.

Two such large islands, such as islands 52 and 102 of FIG. 7, are often incorporated into one integrated circuit chip, each containing a power transistor. Such a pair of power transistors is
In a pole driver circuit, and in particular, the two power transistors are N-type transistors in which the power transistors are formed.
It is required in a bridge driver to drive an inductive load so that the islands are driven negative with respect to the alternating surrounding substrate. An example of such a drive circuit is described in U.S. Pat. No. 5,075,568 to Bilotti et al., Assigned to the same assignee as the present invention. Two mutually adjacent islands 56 and 106 are connected by a substrate resistance, shown as lumped resistance 148 in FIGS.

In the equivalent circuit of FIG. 8, the PN junction between the large island 52 and the substrate 50 is
Is represented by Large islands 52 and 10
2 are the resistances 92 and 142, respectively.
Is represented by Large islands 52 and 10
The protective parasitic transistors associated with 2 are 5
5 and 105. One of two big islands
For example, when 52 is momentarily forward biased with respect to substrate 50, the voltage on substrate 50 near buried layer 66 of active protection transistor 55 will
Is reduced to a negative value. Since the collector 66 of the active transistor 55 is connected to the collector 116 of the protection transistor 105 via the substrate resistor 148, both the collectors 66 and 116 are pulled down to a negative voltage. This is the protection transistor 105
Of the protection transistor 1 since the junction from the collector 116 to the base 118 of this transistor is forward biased at this time.
05 is turned on in the reverse mode.

This further reduces the substrate current to the two collectors 6.
6 and 116, and vice versa.
Flowing through 05 to the positive bias voltage + Ve of the large island 102 leads to a substantial reduction in the efficiency of the protection transistor 55 which dissipates the injection current from the large island 52 to the adjacent large island 102.

In the prior art structure of FIG. 3, the protection transistor 28 has a low current gain in the forward direction (active protection) and a high current gain in the reverse direction and is associated with two alternatingly injected large islands. When used in pairs to work together, protection transistors 28 of the prior art type
The above-mentioned decline in efficiency worsens.

On the other hand, the preferred protection transistors 55 and 105 just described have relatively low gain in both directions. Thus, the inherent protection efficiency provided in the structure of FIG. 5 where protection is provided for only one power transistor is substantially the same as in the prior art structure of FIG.

However, when used in pairs as shown in FIG. 7, the protection transistors 55 and 105 are disadvantageously coupled incompletely due to the low reverse current gain of these protection transistors, which causes Leads to lower parasitic currents (via substrate resistance 148) and also lower power consumption.

No matter how the bipolar protection transistor of the present invention is constructed, the larger intervening space occupied by the protection island between the large island on the injection side and the small island 54 as shown in FIG. This intervening location of the protection transistor is desirable, as it seeks to provide additional protection effectiveness.

The integrated circuit of FIG. 9 is formed in a P-type silicon substrate 150. At some moment in the operation of the power device, the N-type island 152 becomes negative with respect to the P-type silicon substrate 150, the source of this negative voltage being represented by the generator 153. The momentary negative voltage applied to the island 152 is
A forward bias of the PN junction between 52 and substrate 150 results, resulting in the injection of minority carriers (electrons) into substrate 150.

The large island 152 (in the figure)
On the right, there are several smaller N-type islands 154 that contain smaller signal-carrying devices (not shown). The protection NPN transistor 155 is located on the right side (in the figure) of the large island 152
An island 156 is formed.

The transistor 155 is connected to the semiconductor chip 15
8 has a base 168 diffused into the N-type island 156 through the surface of the island 156 and an emitter 178 formed in the island 156. An annular N ⁺ plug extends through epitaxial island 156 and contacts N ⁺ buried layer 166 to form a central N-type epitaxial pocket 170 that works with buried layer 166 as a collector of protection transistor 155. . The numbers identifying the elements in FIG. 9 are each obtained by adding 100 to the numbers identifying the corresponding elements in FIG.

In this conventional vertical protection transistor 155, it is desirable that the current gains in the forward and reverse conduction methods are high and low, respectively. However, in the conventional protection transistor 28 of FIG. An inverse relationship is found, so this protection transistor 155 also works well in pairs with use with two large injection islands.

For example, as shown in FIG. 7, it is desirable to dispose a protection transistor between a large injection transistor and an island to be protected. However, other locations also have advantages. At any selected location of the protection transistor, the grounded isolation wall of the substrate and the isolation wall of the substrate to which the collector of the protection transistor is electrically connected must be on the opposite side of the injection transistor.

Another location for the protection transistors 180 and 182 is shown symbolically in FIG. 10 on the opposite side of the respective large parallel injection transistor islands 181 and 183 associated therewith. In FIG. 11, protection transistors 190 and 192 are shown on opposite sides of their associated parallel large injection transistor islands 191 and 193, respectively. The protection transistors 180 and 1 shown in FIG.
The advantage of the opposing side positions of 82 is that the protection transistor 1
80 and 182 are interposed between contact pads (not shown) located along these opposing surfaces of the large transistor, thus allowing a particularly space efficient layout.

In FIG. 12, the anode of protection Schottky diode 200 has a large implantation island 204
And a group of small islands 205 to be protected. The cathode of Schottky diode 200 is electrically connected to a piece of metal 207 that contacts a portion of large island 204. On the opposite side of the large island 204, a metal contact 206 contacts a separation wall of a substrate that is electrically connected to a circuit ground of the integrated circuit.

In FIG. 13, a similar integrated circuit has a Schottky diode 210 formed on the surface of a large island 214. The anode of the Schottky diode 210 is electrically connected to a piece of metal 217 that contacts the isolation wall of the substrate between the large island 214 and the protected small island 215. On the side of the large island 214 opposite the small island 215 to be protected, a metal contact 216 is in contact with the isolation wall opposite the substrate which is electrically connected to the circuit ground of the integrated circuit.

In FIG. 14, the equivalent circuit of the substrate shown in FIG. 10 shows that the Schottky diode 200 shunts the base / emitter junction of the parasitic transistor 208 formed by the large island 104 and the small island 205. Show. The Schottky diode holds the junction at a relatively low voltage other than necessary to impose a forward bias on the base / emitter junction to turn on parasitic transistor 208. Thus, as in the integrated circuit including the protection transistor described above,
A large transistor down voltage gradient is generated in the direction of pulling the injected charge towards the ground isolation wall opposite the large island 204 (left side in the figure).

The equivalent circuit in the embodiment shown in FIG. 13 is substantially the same as that shown in FIG. Thus, the retention efficiency provided is not as dynamic or as great as in the previous embodiment with a protection transistor. However, the integrated circuits of FIGS. 12 and 13 using protective Schottky diodes are more efficient with respect to the required integration area, and in some cases, for example, where small islands allow for small injection current concentrations. These simple protective Schottky structures are desirable.
Yet another advantage is that if there are two potentially implanting islands and two protected Schottky diodes, the protected Schottky diode as in protection transistors 55 and 105 Since there is no inversion condition, the cross-conduction effect described above is zero.

[Brief description of the drawings]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a PN to prevent collection of charge injected into a substrate by nearby forward-biased islands.
FIG. 2 is a partial cross-sectional view of one of three semiconductor integrated circuit chips showing a prior art structure for protecting a junction-separated island.

FIG. 2 shows PN to prevent collection of charge injected into the substrate by nearby forward-biased islands.
FIG. 2 is a partial cross-sectional view of one of three semiconductor integrated circuit chips showing a prior art structure for protecting a junction-separated island.

FIG. 3 shows a PN to prevent collection of charge injected into the substrate by nearby forward-biased islands.
FIG. 2 is a partial cross-sectional view of one of three semiconductor integrated circuit chips showing a prior art structure for protecting a junction-separated island.

FIG. 4 is a diagram showing an equivalent circuit portion showing the prior art structure of FIG. 3;

FIG. 5 is a side sectional view showing a part of one embodiment of a semiconductor integrated circuit chip of the present invention having a separate injected charge protection transistor.

6 is a diagram showing an equivalent circuit portion of the structure of FIG.

FIG. 7 is a plan view showing a portion of a semiconductor integrated circuit chip of the present invention including structural features and additional features of that shown in FIG. 5 and having the same reference numerals as the corresponding elements in FIG. 5; is there.

FIG. 8 is a diagram showing an equivalent circuit part of the structure of FIG. 7;

FIG. 9 is a side sectional view showing an alternative protection transistor in the semiconductor integrated circuit chip of the present invention.

FIG. 10 is a plan view of a portion of an integrated circuit chip of the present invention showing alternative locations for protection transistors.

FIG. 11 is a plan view of a portion of another integrated circuit chip of the present invention showing an alternative location of the protection transistor.

FIG. 12 is a plan view of a portion of an integrated circuit of the present invention using a protective Schottky diode.

FIG. 13 is a plan view of a portion of another integrated circuit of the present invention using a protective Schottky diode.

FIG. 14 is an equivalent circuit diagram for the integrated circuit of FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 Large island 12 Substrate 14 Protection N-type ring 19 Island 20 Large epitaxial island 22 Epitaxial N-type island 24 N-type buried layer 26 N-type wall 28 Protection bipolar transistor 31 Collector 34 P-type isolation Wall 36 Separation wall 50 P-type silicon substrate 51 Epitaxial layer 52 N-type large (implanted) island 53 Generator 54 N-type island 55 NPN transistor 56 Island 61 Separation wall region 62 P-type separation wall Region 63 P-type isolation wall region 66 N ⁺ buried layer 68 P-type buried layer 70 epitaxial pocket 72 N ⁺ region 74 annular P-type wall 75 epitaxial material internal region 76 epitaxial port Ket 78 N ⁺ emitter region 90 diode 92 discrete resistor 94 parasitic transistor 102 island 104 large island 105 protection transistor 116 collector 118 base 128 collector 148 substrate resistance 150 P-type silicon substrate 152 N-type island 153 generator 154 N- Type island 155 Protected NPN transistor 156 Epitaxial island 166 N ⁺ Buried layer 168 Base 170 N-type epitaxial pocket 178 Emitter 180 Protection transistor 181 Large parallel injection transistor island 182 Protection transistor 183 Injection transistor island 190 Protection Transistor 191 Parallel large injection transistor island 192 Transistor 193 parallel large injection transistor island 200 protected Schottky diode 202 substrate 204 large injection Island 205 small islands 206 metal contact strip 207 metal pieces 208 parasitic transistor 210 Schottky diode 214 larger islands 215 small islands 216 metal contact piece

──────────────────────────────────────────────────の Continuing on the front page (72) Richard Bee Cooper, Holden Street, Shrewsbury, Massachusetts, USA 01545, USA 90 (72) Robert Jay Stoddard, Massachusetts, United States 01773, Lincoln, Willard Load 8 (56) References JP-A-2-22854 (JP, A) U.S. Pat. No. 5,545,917 (US, A) EP 813247 (EP, A1) (58) Fields investigated (Int. Cl. ⁷⁾ H01L 21/822 H01L 21/8222-21/8228 H01L 21/8232 H01L 27 / 04,27 / 06 H01L 27 / 08,27 / 082

Claims (12)

(57) [Claims] 1. A semiconductor substrate of one conductivity type and a first PN of an opposite conductivity type enclosed within the substrate and momentarily subjected to a forward bias with respect to the surrounding substrate. Attempting to collect carriers injected from the junction isolation island and the island formed in the substrate and located on one side of the first island, the first momentarily forward biased island; An integrated circuit chip of the type having at least a second PN junction isolation island of the opposite conductivity type, comprising: a) a base of one conductivity type separated by a PN junction of the opposite conductivity type and a reverse conductivity. A third island having a vertical protective bipolar transistor formed therein having an emitter of a neutral type; b) connecting a ground point in the integrated circuit to the ground of the protective transistor. A circuit ground conductor that connects to the ground region and the isolation wall of the substrate opposite the first island; and c) connects the emitter of the protection transistor to an opposite conductive type portion of the first island. An integrated circuit chip comprising: one conductor; and d) another conductor connecting the collector of the protection transistor to the isolation wall of the substrate on the one side of the first island. 2. The method according to claim 1, wherein said third island is located adjacent to said one side of said first island.
An integrated circuit chip as described. 3. The integrated circuit chip according to claim 1, wherein said third island is located adjacent to another side of said first island. 4. A thickly doped buried layer of the opposite conductivity type formed in said third island in contact with said one conductivity type substrate acts as a collector of said protection transistor. A buried layer of a conductivity type extending from the buried layer of the opposite conductivity type forming the base of the protection transistor into the third island;
A heavily doped plug region of the opposite conductivity type extends from the surface of the chip through the third island to the buried layer of the opposite conductivity type, and the another conductor contacts the plug region. The integrated circuit chip according to claim 1, wherein the integrated circuit chip is connected to the third island. 5. The plug region of the opposite conductivity type is an annular wall region surrounding the interior of the third island of the opposite conductivity type, and the chip further comprises the third conductive island.
Wherein the ground conductor includes an annular wall region of one conductivity type formed therein and extending from the chip surface to the buried base region of one conductivity type. Connected to the base region of the protection transistor by contacting the one conductive type annular wall region, wherein a thickly doped opposite conductive type contact region is formed of the one conductive type annular wall. 5. The integrated circuit according to claim 4, wherein the contact region is formed on the chip surface at a central portion of the third island surrounded by the partial region, and the contact region serves as an emitter of the protection transistor to which the one conductor is connected. Chips. 6. A region of one conductivity type formed on said third island on a chip surface serves as a base of said protection transistor, and a region of opposite conductivity type formed on said base region is formed on said third island. 2. The integrated circuit chip according to claim 1, which acts as an emitter of the protection transistor. 7. A semiconductor substrate of one conductivity type and a large island having two PN junction isolation islands of opposite conductivity type wherein a forward bias is alternately imposed on said substrate. Each of the two large islands has one side, another side and a second side opposite the first side, the large islands being arranged such that the first sides face each other. And an integrated circuit of the type wherein a group of small PN junction isolation islands of opposite conductivity type is formed on said substrate and is adjacent to said one side of said first large island and said second large island A) a vertical protective bipolar transistor formed respectively adjacent to said two large islands, each formed on each of said two separate islands; Two separate PN junction isolation islands of opposite conductivity type, each having a base of one conductivity type and a collector and emitter of opposite conductivity type; b) in the integrated circuit A ground conductor for a circuit connecting a ground point to each of the base regions of the protection transistor and the two isolation walls of the substrate respectively located on opposite sides of the large island; c) connecting the emitters of the protection transistor to the respective 1 connecting to the opposite conductivity type part of the large island
An integrated circuit comprising: a pair of conductors; and d) another pair of conductors respectively connecting the collector of the protection transistor to the isolation wall of the substrate on the one side of the two large islands. 8. The method according to claim 8, wherein the separate islands including the protection transistors are two between the one large island and the group of small islands and between the other large island and the group of the small islands. The integrated circuit according to claim 7, wherein the integrated circuit is arranged in each of the regions. 9. The integrated circuit chip according to claim 7, wherein said separate island including said protection transistor is located in a region between said two large islands. 10. The integrated circuit according to claim 7, wherein said two large islands and said two corresponding separate protected islands are respectively located adjacent to said two opposing sides. 11. A semiconductor substrate of one conductivity type,
A first PN junction isolation island of opposite conductivity type formed on and surrounded by the substrate, wherein a forward bias is momentarily imposed on the surrounding substrate; and Attempting to collect carriers injected from the first momentarily forward biased island present on one side of the first island;
An integrated circuit chip of the type having at least a second PN junction isolation island of the opposite conductivity type, comprising: a) a common cathode with the first island of the opposite conductivity; A Schottky diode formed in a portion of said first PN junction isolated island having an anode electrically connected to said isolation wall of said substrate between said second island and b); A conductor connecting a ground point of the integrated circuit to a separation wall of the substrate on a side opposite to the first island. 12. A semiconductor substrate of one conductivity type,
A first PN junction isolated island of opposite conductivity type formed in and surrounded by the substrate, wherein a forward bias is momentarily applied to the surrounding substrate; Attempting to collect injection carriers from the first momentarily forward biased island formed and present on one side of the first island;
An integrated circuit chip of the type having at least a second PN junction isolated island of the opposite conductivity type, comprising: a) an isolation wall of the substrate between the first island and the second island; A cathode formed on the one side of the first island and electrically connected to the first PN junction isolation island of a conductivity type opposite to a common anode with the isolation wall of the substrate. With
An integrated circuit chip comprising: a Schottky diode; and b) an electrical conductor connecting a ground point of the integrated circuit chip to an isolation wall of the substrate opposite the first island.