JP3128987B2 - Method for manufacturing semiconductor crystal plane, reflector comprising semiconductor crystal plane, and semiconductor quantum structure - Google Patents
Method for manufacturing semiconductor crystal plane, reflector comprising semiconductor crystal plane, and semiconductor quantum structureInfo
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- JP3128987B2 JP3128987B2 JP04260034A JP26003492A JP3128987B2 JP 3128987 B2 JP3128987 B2 JP 3128987B2 JP 04260034 A JP04260034 A JP 04260034A JP 26003492 A JP26003492 A JP 26003492A JP 3128987 B2 JP3128987 B2 JP 3128987B2
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- crystal
- semiconductor
- crystal plane
- plane
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Description
【0001】[0001]
【産業上の利用分野】本発明は半導体結晶面の作製方法
と、これを用いて作製した半導体結晶面より成る反射鏡
及び半導体量子構造に係わる。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for fabricating a semiconductor crystal plane, and to a reflector and a semiconductor quantum structure comprising a semiconductor crystal plane fabricated using the method.
【0002】[0002]
【従来の技術】半導体結晶面を基板上に気相成長により
形成して各種構造の半導体装置、例えば埋込み型構成の
半導体レーザや量子構造を形成する方法及び構造が各種
提案されている。2. Description of the Related Art Various methods and structures have been proposed for forming semiconductor devices having various structures, for example, semiconductor lasers and quantum structures having a buried structure by forming a semiconductor crystal plane on a substrate by vapor phase growth.
【0003】例えばAlGaAs系化合物半導体におい
て、{111}B結晶面と{110}結晶面との成長条
件が全く異なることを利用して、(111)B結晶面を
主面とする基板上に〔11−2〕結晶軸方向に延長する
マスクを形成してMOCVD(有機金属気相成長法)に
より気相成長を行うことによって基板に垂直な{11
0}結晶面を形成するとか、また3つの{110}結晶
面と{111}B基板面とによって四面体構造を形成す
る方法が提案されている(例えば福井らによる「真空」
34 (1991)499、T.Fukui et al.Appl.Phys.Lett. 57 (19
90)1209 、T.Fukui et al. Appl.Phys.Lett. 58 (1991)
2018)。しかしながらこれらの方法では、汎用性が低く
取扱いにくいとされる{111}B結晶面基板を用いて
いることから、上述の文献にも記載されているように、
例えば通常用いられる{100}結晶面基板に比し成長
条件が非常に難しいため、結晶成長面の形成前後の選択
成長、集積化が極めて困難となる。[0003] For example, in an AlGaAs-based compound semiconductor, the fact that the growth conditions of the {111} B crystal plane and the {110} crystal plane are completely different makes use of the fact that a [111] B crystal plane is used as a principal plane on a substrate. 11-2] By forming a mask extending in the crystal axis direction and performing vapor phase growth by MOCVD (metal organic chemical vapor deposition), {11
There has been proposed a method of forming a {0} crystal plane or a method of forming a tetrahedral structure by three {110} crystal planes and a {111} B substrate plane (for example, “vacuum” by Fukui et al.).
34 (1991) 499; T. Fukui et al. Appl. Phys. Lett. 57 (19
90) 1209, T. Fukui et al. Appl. Phys. Lett. 58 (1991)
2018). However, these methods use a {111} B crystal plane substrate, which is considered to be low in versatility and difficult to handle, so as described in the above-mentioned literature,
For example, since the growth conditions are much more difficult than that of a normally used {100} crystal plane substrate, selective growth and integration before and after formation of a crystal growth plane are extremely difficult.
【0004】また、〈011〉及び〈01−1〉結晶軸
方向を各辺とした窓を有するマスクをInP基板の{1
00}結晶面上に設け、InGaAs、InPを成長す
ることで、InGaAs基板においては{111}及び
{110}結晶面、InP基板においては{111}結
晶面を形成する方法が提案されている(例えば Y.D.Gal
euchet et al. Appl.Phys.Lett.58(1991)2423)。この
場合、主に{111}結晶を支配的に成長させて(11
1)A結晶面及び(111)B結晶面で囲まれた量子箱
構造を形成する方法が提案されている。しかしながらこ
の方法は、量子箱構造を得る以外に例えばレーザ光等の
反射鏡を形成する場合に利用しようとすると、{11
1}結晶面が{100}結晶面に対し54.7°という
変則的な角度を成すことから光学系が複雑となってしま
うという問題がある。Further, a mask having a window having each side of the <011> and <01-1> crystal axis directions is a
A method has been proposed in which a {111} and {110} crystal plane is formed on an InGaAs substrate and a {111} crystal plane is formed on an InP substrate by growing InGaAs and InP on a {100} crystal plane. For example, YDGal
euchet et al. Appl. Phys. Lett. 58 (1991) 2423). In this case, the {111} crystal is mainly grown (11
1) A method of forming a quantum box structure surrounded by an A crystal plane and a (111) B crystal plane has been proposed. However, if this method is used to form a reflecting mirror such as a laser beam in addition to obtaining a quantum box structure, the method will be described as {11}.
Since the 1 問題 crystal plane forms an irregular angle of 54.7 ° with the {100} crystal plane, there is a problem that the optical system becomes complicated.
【0005】また或いは、{100}結晶面上に〔01
1〕(いわゆる逆メサ方向)、〔01−1〕(いわゆる
順メサ方向)、〔001〕結晶軸の各方向に延長する細
線構造のAlGaAs系半導体層を、ジエチルアルミニ
ウムクロライド (C2H5)2AlClやジエチルガリウムクロラ
イド (C2H5)2GaCl等のハイドライド系材料を用いて成長
させ、{110}結晶面及び{111}結晶面を得る方
法が提案されている(例えば J.Lebens et al. Appl.Ph
ys. Lett. 56 (1990)2642 、または T.F.Kuechet al. A
ppl.Phys. Lett. 56 (1990)2642) 。Alternatively, [01] on the {100} crystal plane
1) (a so-called reverse mesa direction), [01-1] (a so-called forward mesa direction), and [001] an AlGaAs-based semiconductor layer having a thin wire structure extending in each direction of a crystal axis is made of diethyl aluminum chloride (C 2 H 5 ). A method of obtaining a {110} crystal plane and a {111} crystal plane by growing using a hydride-based material such as 2 AlCl or diethyl gallium chloride (C 2 H 5 ) 2 GaCl has been proposed (for example, J. Lebens et al. al. Appl.Ph
ys. Lett. 56 (1990) 2642, or TFKuechet al. A
ppl.Phys. Lett. 56 (1990) 2642).
【0006】更にまた、GaAs基板上に〔011〕及
び〔0−11〕の各結晶軸方向に沿う辺を有するマスク
を形成し、トリメチルガリウム(TMG)やトリメチル
アルミニウム(TMA)等の材料を用いて半導体層を形
成し、成長後に(111)A及び(111)B結晶面に
より囲まれた量子箱構造を得る方法が述べられている
(例えば Y.Nagamune et al. Extended Abstracts of t
he 1991 InternationalConferrence on Solid State De
vices and Materials,Yokohama,pp689-691)。Further, a mask having sides along the respective crystal axis directions of [011] and [0-11] is formed on a GaAs substrate, and a material such as trimethylgallium (TMG) or trimethylaluminum (TMA) is used. A method of forming a semiconductor layer by growth and obtaining a quantum box structure surrounded by (111) A and (111) B crystal planes after growth is described (for example, Y. Nagamune et al. Extended Abstracts of t).
he 1991 InternationalConferrence on Solid State De
vices and Materials, Yokohama, pp689-691).
【0007】一方、武部らによる「電気学会研究会、電
子材料研究会技報 EFM-91-17、pp69-71 」においては、
(111)A結晶面を主面とする基板上に段差構造を作
製して、この上に半導体層を成長するものであるが、本
文中69頁で「(100)基板上では4つの等価な{11
0}斜面で囲めそうに思われるが、隣接する2つの等価
な(110)斜面の交叉点は1つおきに等価でしかな
く、実際には囲めない」との記載があり、(100)基
板上に{110}結晶面で囲まれた半導体層を形成する
ことはできないとしている。[0007] On the other hand, in Takebe et al., "Technical Report of the Institute of Electrical Engineers of Japan, Technical Committee of Electronic Materials, EFM-91-17, pp69-71",
A step structure is formed on a substrate having a (111) A crystal plane as a main surface, and a semiconductor layer is grown thereon. $ 11
0 ° slope seems to be enclosed, but the intersection of two adjacent equivalent (110) slopes is only equivalent every other one and cannot actually be enclosed. " It is stated that a semiconductor layer surrounded by a {110} crystal plane cannot be formed thereon.
【0008】また、"E.Boeckenhoff et al. JOURNAL of
CRYSTAL GROWTH 114(1991)pp610-632" においては、基
板上にフォトリソグラフィの適用により0.5〜1.5
μm径の円柱状のリッジを形成した後、MBE(分子線
エピタキシー法)によりこの上に半導体層を形成するこ
とによって{110}結晶面で囲まれた結晶構造を得て
いる。しかしながらこの場合、その本文中 626頁のFig.
8 にあるように、{110}結晶面の裾部が広がる形状
となり、例えば反射鏡面として利用しにくいという問題
がある。Further, "E. Boeckenhoff et al. JOURNAL of
In CRYSTAL GROWTH 114 (1991) pp610-632 ", 0.5 to 1.5
After forming a columnar ridge having a diameter of μm, a semiconductor layer is formed thereon by MBE (Molecular Beam Epitaxy) to obtain a crystal structure surrounded by {110} crystal planes. However, in this case, Fig.
As shown in FIG. 8, there is a problem that the skirt of the {110} crystal plane is widened and, for example, it is difficult to use as a reflecting mirror surface.
【0009】[0009]
【発明が解決しようとする課題】本発明は、上述したよ
うな半導体結晶面の作製にあたって、基板に対し45°
を成す反射鏡面として利用し易い形状を簡単に即ち比較
的緩やかな成長条件をもって得られるようにし、更に量
子構造をも得ることのできる汎用性の高い半導体結晶面
の作製方法を提供し、これにより精度良くまた簡単に反
射鏡面や量子構造を得られるようにする。SUMMARY OF THE INVENTION The present invention relates to a method for fabricating a semiconductor crystal plane as described above, in which a substrate is formed at an angle of 45.degree.
A method for producing a highly versatile semiconductor crystal surface capable of easily obtaining a shape that can be easily used as a reflecting mirror surface forming the same, that is, under relatively moderate growth conditions, and further obtaining a quantum structure is provided. A mirror surface and a quantum structure can be obtained accurately and easily.
【0010】[0010]
【課題を解決するための手段】本発明半導体結晶面の作
製方法は、図1A及びBにその一例の工程図を示すよう
に、主面が{100}結晶面である半導体基板上に、側
面2A〜2Dが{010}結晶面で且つこれら側面2A
〜2Dに囲まれた上面2Sが主面に平行な面から成る段
差2を形成し、この段差を有する半導体基板上に半導体
3を気相成長することで段差2のエッジ12Eに対応す
る部分から延びる{110}結晶面を生じさせ、これら
{110}結晶面を構成面として主面に対し45°の角
度を有する半導体結晶面を作製する。As shown in FIGS. 1A and 1B, a method for manufacturing a semiconductor crystal plane according to the present invention is shown in FIGS. 1A and 1B. 2A to 2D are {010} crystal faces and these side faces 2A
2D form a step 2 consisting of a plane parallel to the main surface, and a semiconductor 3 is vapor-phase-grown on a semiconductor substrate having this step so that a portion corresponding to the edge 12E of the step 2 Extending {110} crystal planes are produced, and a semiconductor crystal plane having these {110} crystal planes as constituent planes and having an angle of 45 ° with respect to the main surface is produced.
【0011】また本発明は、主面が{100}結晶面で
ある半導体基板上に、〈001〉結晶軸方向に延びるエ
ッジを有する成長阻止層を形成し、この成長阻止層を形
成した半導体基板上に半導体を気相成長し、半導体基板
の成長阻止層の形成されていない部分上でエッジに対応
する部分から延びる{110}結晶面を生じさせ、この
{110}結晶面を構成面として主面に対し45°の角
度を有する半導体結晶面を作製する。[0011] The present invention also provides a semiconductor substrate having a {001} crystal plane having an edge extending in the <001> crystal axis direction on a semiconductor substrate having a {100} crystal plane. A semiconductor is vapor-phase grown thereon to generate a {110} crystal plane extending from a portion corresponding to an edge on a portion of the semiconductor substrate where the growth inhibition layer is not formed, and the {110} crystal plane is mainly used as a constituent surface. A semiconductor crystal plane having an angle of 45 ° with respect to the plane is manufactured.
【0012】また他の本発明は、上述の各作製方法によ
って、主面に対し平行に進行する光を主面に対しほぼ垂
直な方向に反射するか、またはこの主面に対し垂直に入
射する光を主面に対しほぼ平行な方向に反射する半導体
結晶面より反射鏡を構成する。According to another aspect of the present invention, light that travels parallel to the main surface is reflected in a direction substantially perpendicular to the main surface, or is incident perpendicularly to the main surface, by the above-described respective manufacturing methods. A reflecting mirror is constituted by a semiconductor crystal surface that reflects light in a direction substantially parallel to the main surface.
【0013】また更に他の本発明は、図2A及びBにそ
の工程図を示すように、主面が(100)結晶面である
半導体基板上に、側面2A〜2Dが(010)、(00
1)、(0−10)、(00−1)の各結晶面から成り
且つ上面2Sが主面に平行な面から成るメサ部12を有
し、このメサ部12を有する半導体基板上に、半導体3
を気相成長してメサ部12の各エッジ2Eに対応する部
分から延びる(110)、(101)、(1−10)、
(10−1)各結晶面を形成して反射鏡4A〜4Dを構
成して、これら各反射鏡4A〜4Dがそれぞれ主面に対
し平行に進行する光を主面に対しほぼ垂直な方向に反射
するか、或いは主面に対し垂直に入射する光を主面に対
しほぼ平行な方向に反射するようにして半導体結晶面よ
り反射鏡を構成する。In still another embodiment of the present invention, as shown in FIGS. 2A and 2B, the side surfaces 2A to 2D are (010) and (00) on a semiconductor substrate whose main surface is a (100) crystal plane.
1) has a mesa portion 12 composed of crystal planes of (0-10) and (00-1), and the upper surface 2S is composed of a surface parallel to the main surface. On a semiconductor substrate having the mesa portion 12, Semiconductor 3
(110), (101), (1-10), extending from a portion corresponding to each edge 2E of the mesa portion 12 by vapor phase growth.
(10-1) Each of the crystal planes is formed to form the reflecting mirrors 4A to 4D, and each of the reflecting mirrors 4A to 4D directs light traveling parallel to the main surface in a direction substantially perpendicular to the main surface. A reflecting mirror is constituted by a semiconductor crystal surface so as to reflect light or to make light incident perpendicular to the main surface in a direction substantially parallel to the main surface.
【0014】また本発明は、主面が(100)結晶面で
ある半導体基板上に、側面が(010)、(001)、
(0−10)、(00−1)各結晶面から成り且つこれ
らに囲まれた面が主面に平行な面から成るメサ部を有
し、このメサ部を有する半導体基板上に、半導体が気相
成長されてメサ部のエッジに対応する部分から延びる
(110)、(101)、(1−10)、(10−1)
各結晶面が形成され、これら(110)、(101)、
(1−10)、(10−1)各結晶面の内少なくとも2
つの結晶面で囲まれた領域に導電領域6を有し、導電領
域6に電子を閉じ込めた量子構造を構成する。Further, according to the present invention, a semiconductor substrate having a (100) crystal plane as a main surface has side surfaces of (010), (001),
(0-10), (00-1) A mesa portion composed of crystal planes and a plane surrounded by these crystal planes is formed of a plane parallel to the main surface. A semiconductor is provided on the semiconductor substrate having the mesa section. (110), (101), (1-10), (10-1) extending from a portion corresponding to the edge of the mesa portion by being vapor-phase grown
Each crystal plane is formed, and these (110), (101),
(1-10), (10-1) At least 2 of each crystal plane
It has a conductive region 6 in a region surrounded by two crystal planes, and forms a quantum structure in which electrons are confined in the conductive region 6.
【0015】[0015]
【作用】上述したように本発明においては、側面が{0
10}結晶面より成る段差即ちメサ部又は溝、また或い
はエッジが〈010〉結晶軸方向に延長する成長阻止層
を{100}結晶面を主面とする半導体基板上に形成
し、この上に気相成長による半導体を形成して自然発生
的に主面に対し45°を成す{110}半導体結晶面を
得ることができることを利用して、これを用いて反射
鏡、又はこれら半導体結晶面に囲まれた導電領域として
半導体量子構造を構成するものである。As described above, in the present invention, the side face is $ 0.
A step formed by a 10 crystal plane, that is, a mesa portion or a groove, or a growth inhibition layer whose edge extends in the <010> crystal axis direction is formed on a semiconductor substrate having a {100} crystal plane as a main surface. Utilizing the fact that a semiconductor is formed by vapor phase growth and a {110} semiconductor crystal plane which naturally forms an angle of 45 ° with respect to the principal plane can be obtained. It constitutes a semiconductor quantum structure as an enclosed conductive region.
【0016】そしてこの本発明によれば、基板に対し4
5°を成す{110}結晶面を{111}B基板のよう
な特殊な基板を用いることなく通常の{100}結晶面
を主面とする基板を用いて形成することができ、従って
成長条件を緩やかにして成長することができる。According to the present invention, 4
The {110} crystal plane forming 5 ° can be formed on a normal substrate having a main surface of {100} crystal without using a special substrate such as a {111} B substrate. Can grow slowly.
【0017】また基板に対し45°を成す{110}結
晶面によって囲まれた例えば四角錐状の半導体結晶面に
より反射鏡を構成することによって、基板と平行な方向
の光ビームをこの反射鏡により基板に対し垂直な方向へ
の変換が可能となり、しかも四面が同時に得られるた
め、単数又は複数の光ビームに対応して設計に自由度を
もたせて構成することができる。またこの四角錐の大き
さを適切に選定することにより、各光ビームの間隔を狭
小化することができる。Further, by forming a reflecting mirror with, for example, a quadrangular pyramid-shaped semiconductor crystal plane surrounded by a {110} crystal plane forming 45 ° with respect to the substrate, a light beam in a direction parallel to the substrate is formed by the reflecting mirror. The conversion in the direction perpendicular to the substrate becomes possible, and furthermore, since four surfaces can be obtained at the same time, the configuration can be designed with a degree of freedom corresponding to one or a plurality of light beams. By appropriately selecting the size of the quadrangular pyramid, the interval between the light beams can be narrowed.
【0018】更にまた本発明によれば、{100}基板
を使って容易に半導体量子構造が得られ、制御性良くま
た再現性良く半導体量子構造を作製することができる。Further, according to the present invention, a semiconductor quantum structure can be easily obtained using a {100} substrate, and a semiconductor quantum structure can be manufactured with good controllability and good reproducibility.
【0019】[0019]
【実施例】以下本発明の各実施例を図面を参照して詳細
に説明する。各例共にGaAs又はAlGaAs系化合
物半導体結晶をMOCVDにより作製したもので、結晶
面の各例を説明した後、反射鏡を構成する場合及び半導
体量子構造を構成する場合を説明する。Embodiments of the present invention will be described below in detail with reference to the drawings. In each example, a GaAs or AlGaAs-based compound semiconductor crystal is manufactured by MOCVD. After describing each example of the crystal plane, a case where a reflecting mirror is formed and a case where a semiconductor quantum structure is formed will be described.
【0020】実施例1 先ず図1Aに上面からみた図を示すように、{100}
結晶面を主面とする半導体基板上に〈001〉結晶軸方
向に沿うエッジ12Eを有する段差2、この場合各辺の
長さがそれぞれ例えば10μm、高さが例えば7μmの
メサ部を示す。この他例えば基板に直接的にRIE(反
応性イオンエッチング)等の異方性エッチングにより溝
を形成しても良く、また或いはフォトレジスト等より成
る成長阻止層によって溝を形成しても良い。図1Aにお
いて矢印a〜dは段差2の各側面2A〜2Dのそれぞれ
の面と直交する結晶軸方向を示す。Embodiment 1 First, as shown in FIG. 1A as viewed from above, {100}
A step 2 having an edge 12E along the <001> crystal axis direction on a semiconductor substrate having a crystal plane as a main surface. In this case, a mesa portion having a length of, for example, 10 μm and a height of, for example, 7 μm is shown. In addition, for example, the groove may be formed directly on the substrate by anisotropic etching such as RIE (reactive ion etching), or the groove may be formed by a growth inhibiting layer made of a photoresist or the like. In FIG. 1A, arrows a to d indicate crystal axis directions orthogonal to the respective surfaces of the side surfaces 2A to 2D of the step 2.
【0021】そしてこの上に、図1Bに示すようにGa
As又はAlGaAs等の半導体3の気相成長を行う。
このとき、{111}A結晶面及び{111}B結晶面
の成長を極力抑え、{110}結晶面が支配的になるよ
うに、即ち{111}結晶面が成長するが{110}結
晶面の成長が極めて遅くなるように適切な成長条件を選
定する。Then, as shown in FIG. 1B, Ga
A vapor phase growth of a semiconductor 3 such as As or AlGaAs is performed.
At this time, the growth of the {111} A crystal plane and the {111} B crystal plane is suppressed as much as possible, so that the {110} crystal plane becomes dominant, that is, the {111} crystal plane grows, but the {110} crystal plane grows. An appropriate growth condition is selected so that the growth of the crystal becomes extremely slow.
【0022】この成長条件としては、例えばAlx Ga
1-x AsをTMG、TMA等のメチル系材料を用いてx
=0〜0.3として結晶成長を行うとき、常圧又は減圧
のMOCVDにおいて共に下記の通りとする。 成長温度 : 800℃以上 V/III 比 : 200以上 成長速度 : 0.4nm/s以下The growth conditions include, for example, Al x Ga
1-x As is converted to x using a methyl-based material such as TMG and TMA.
When crystal growth is performed with = 0 to 0.3, both are as follows in MOCVD under normal pressure or reduced pressure. Growth temperature: 800 ° C or more V / III ratio: 200 or more Growth rate: 0.4 nm / s or less
【0023】また、特にエチル系材料のトリエチルガリ
ウム(TEG)、トリエチルアルミニウム(TEA)等
の材料により同様にAlx Ga1-x Asをx=0〜0.
3として成長するときは、常圧又は減圧のMOCVDに
おいて下記の通りとする。 成長温度 : 750℃以上 V/III 比 : 100以上 成長速度 : 0.4nm/s以下In addition, in particular, Al x Ga 1 -x As is similarly set to x = 0 to 0. 0 using a material such as triethylgallium (TEG) or triethylaluminum (TEA) as an ethyl-based material.
When growing as No. 3, MOCVD under normal pressure or reduced pressure is performed as follows. Growth temperature: 750 ° C. or more V / III ratio: 100 or more Growth rate: 0.4 nm / s or less
【0024】但し上記条件のうち、成長温度は基板温度
を示し、成長速度は平坦基板使用時のものとし、またV
/III 比は原子数比を示す。However, of the above conditions, the growth temperature indicates the substrate temperature, the growth rate is that when a flat substrate is used, and V
The / III ratio indicates the ratio of the number of atoms.
【0025】このように成長条件を選定する場合は、図
1Bに示すように、基板の主面即ち{100}結晶面に
対し45°を成す{110}結晶面、この場合(11
0)、(101)、(1−10)、(10−1)の各結
晶面で囲んだ形状として半導体3が自然発生的に成長す
る。この形状は、上述のメサ部12の大きさによること
なく同様に得ることができた。When the growth conditions are selected in this way, as shown in FIG. 1B, the {110} crystal plane which forms 45 ° with respect to the main surface of the substrate, ie, the {100} crystal plane,
The semiconductor 3 grows spontaneously as a shape surrounded by the crystal planes of (0), (101), (1-10), and (10-1). This shape could be obtained similarly without depending on the size of the mesa portion 12 described above.
【0026】またこのときの工程図を図2A及びBに示
すように、段差この場合メサ部12上に上述の条件によ
り結晶成長を行うと、半導体3は{110}結晶面が支
配的に成長すると共に、その基部側において各角部毎に
3つの垂直面、図2Bにおいては(010)、(01
1)及び(001)の各結晶面が成長する。他の角部に
おいても同様に隣り合う2つの{110}結晶面に対
し、{011}結晶面を挟んで{010}結晶面が配さ
れた3つの垂直面が形成され、上面からみて八角形状と
なるように構成される。As shown in FIGS. 2A and 2B, when the crystal is grown on the mesa portion 12 under the above-described conditions, the {110} crystal plane grows predominantly in the semiconductor 3. At the same time, three vertical surfaces are provided for each corner on the base side, (010) and (01) in FIG. 2B.
Each crystal plane of 1) and (001) grows. Similarly, at the other corners, three perpendicular planes having {010} crystal planes sandwiched between {011} crystal planes are formed with respect to two adjacent {110} crystal planes, and have an octagonal shape as viewed from above. It is configured to be.
【0027】この場合{011}結晶面は{110}結
晶面と同様にその面上において成長速度が極めて遅く、
この面に垂直な方向へは半導体3は成長せず、主面と平
行な(100)結晶面と、これに対し垂直な(01
0)、(001)、更に図3に示すように(0−10)
及び(00−1)の各結晶面が成長する。即ち基板主面
に垂直な方向及び〈001〉結晶軸方向と等価な4つの
方向に延長するように結晶成長することがわかる。In this case, the {011} crystal plane has a very low growth rate on the same plane as the {110} crystal plane.
The semiconductor 3 does not grow in a direction perpendicular to this plane, and the (100) crystal plane parallel to the main surface and the (01) crystal plane
0), (001), and (0-10) as shown in FIG.
Each crystal plane of (00-1) grows. That is, it can be seen that the crystal grows so as to extend in four directions equivalent to the direction perpendicular to the main surface of the substrate and the <001> crystal axis direction.
【0028】図3において、図2Aに示す結晶成長前の
メサ部12の形状を破線eに示すように、各{110}
結晶面はメサ部12のエッジから延長するように成長さ
れる。この図3においては、図2Bに示す各結晶面とは
反対側の結晶面の構成を示す。In FIG. 3, the shape of the mesa portion 12 before crystal growth shown in FIG. 2A is {110} as shown by a broken line e.
The crystal plane is grown so as to extend from the edge of the mesa portion 12. FIG. 3 shows a configuration of a crystal plane on the opposite side to each crystal plane shown in FIG. 2B.
【0029】そしてこの結晶成長を更に続けると、半導
体3は図4A及びBにそれぞれ平面図及び斜視図を示す
ように、半導体3はその上部が(110)、(1−1
0)、(101)、(10−1)の各{110}結晶面
によって閉じられて四角錐状となる。図4において、図
1及び図2に対応する部分には同一符号を付して重複説
明を省略する。When the crystal growth is further continued, the semiconductor 3 has an upper portion of (110) and (1-1) as shown in plan and perspective views in FIGS. 4A and 4B, respectively.
0), (101), and (10-1) are closed by the {110} crystal planes to form a quadrangular pyramid. 4, parts corresponding to those in FIGS. 1 and 2 are denoted by the same reference numerals, and redundant description will be omitted.
【0030】また、図5に示す例では、メサ部12の高
さを比較的低く形成して、結晶成長を上述の条件により
行った場合の結晶面の構造を示す。基部側の{010}
結晶面は成長せず、基板主面に対し45°を成す各{1
10}結晶面とこれと同等でかつ基板主面に大して垂直
な{011}結晶面のみによって半導体が構成される。In the example shown in FIG. 5, the structure of the crystal plane in the case where the height of the mesa portion 12 is formed relatively low and the crystal growth is performed under the above conditions is shown. {010} on the base side
The crystal planes do not grow, and each # 1 that forms 45 ° with respect to the main surface of the substrate
A semiconductor is constituted only by a 10-crystal plane and a {011} crystal plane equivalent to the 10-crystal plane and substantially perpendicular to the main surface of the substrate.
【0031】即ち、メサ部12の高さを上述したように
7μm程度と比較的高くした場合、或いはメサ部12を
設けない領域上での成長がメサ部12上の成長に比し遅
く、成長が追いつかない場合は上述の図2〜図4に示す
如く基部側が八角形状となり、メサ部12が比較的例え
ば2〜3μm程度と低く形成される場合は、図5に示す
ように、基板主面に対し45°を成す{110}結晶面
が基部側に延長する構造となる。That is, when the height of the mesa portion 12 is relatively high, about 7 μm as described above, or the growth on the region where the mesa portion 12 is not provided is slower than the growth on the mesa portion 12, 2 cannot be caught, the base side has an octagonal shape as shown in FIGS. 2 to 4 described above, and when the mesa portion 12 is formed relatively low, for example, about 2 to 3 μm, as shown in FIG. The {110} crystal plane, which forms 45 ° with respect to the base, extends to the base side.
【0032】また、上述の成長条件において、メチル系
材料を用いて成長する場合に例えば成長温度を800℃
以上からはずれた750℃程度とするとか、また或いは
成長速度を0.4nm/s以下からはずれた1nm/s
程度とするときには、図6及び図7に各例の斜視図及び
平面図を示すように、{111}B結晶面や{111}
A結晶面が現れる。図6及び図7において、図1及び図
2に対応する部分には同一符号を付して重複説明を省略
する。図6においては(101)結晶面と(1−10)
結晶面との間に(1−11)B結晶面、更にこれとは逆
側即ち図示しないが(10−1)結晶面と(110)結
晶面との間に(11−1)B結晶面が発生する場合を示
す。また、図7に示すように、(10−1)結晶面と
(1−10)結晶面との間に(1−1−1)A結晶面、
(110)結晶面と(101)結晶面との間に(11
1)A結晶面が発生する場合を示す。In the above-described growth conditions, when growing using a methyl-based material, for example, a growth temperature of 800 ° C.
It may be set to about 750 ° C. which deviates from the above, or the growth rate may be deviated from 0.4 nm / s or less to 1 nm / s.
6 and 7 show a perspective view and a plan view of each example, the {111} B crystal plane and the {111}
A crystal plane appears. In FIGS. 6 and 7, portions corresponding to FIGS. 1 and 2 are denoted by the same reference numerals, and redundant description is omitted. In FIG. 6, the (101) crystal plane and (1-10)
(1-11) B crystal plane between the crystal plane and the other side, ie, not shown, but (11-1) B crystal plane between the (10-1) crystal plane and the (110) crystal plane. Shows a case in which Further, as shown in FIG. 7, a (1-1-1) A crystal plane exists between the (10-1) crystal plane and the (1-10) crystal plane,
(11) between the (110) crystal plane and the (101) crystal plane
1) The case where the A crystal plane occurs is shown.
【0033】また、図4A及びBにおいて説明した場合
と同様に、4つの{110}結晶面により四角錐形状が
形成される場合を図8に、またメサ部12が比較的低く
形成される場合を図9にそれぞれ示す。図8及び図9に
おいて、図4及び図5に対応する部分には同一符号を付
して重複説明を省略する。FIG. 8 shows a case where a quadrangular pyramid is formed by four {110} crystal planes, and a case where the mesa portion 12 is formed relatively low, similarly to the case described with reference to FIGS. 4A and 4B. Are shown in FIG. 8 and 9, parts corresponding to those in FIGS. 4 and 5 are denoted by the same reference numerals, and redundant description is omitted.
【0034】尚、本発明においては段差の延長方向を
〈001〉結晶軸方向に沿うように選定するものである
が、これに対し45°を成す〈011〉結晶軸方向に延
長する段差を設ける場合は、図10A及びBにその製造
工程図を示すように、成長条件を上述の各例における条
件と同一条件としても、{110}結晶面が支配的に成
長することがなく、{111}A結晶面及び{111}
B結晶面と{110}結晶面が混在した形状となる。更
にこの場合メサ部12の側面は{110}結晶面により
構成されるため、基板主面において横方向の成長は極め
て少なくなり、上述の各例において説明した本発明半導
体結晶面の構造とは異なり、基部側には結晶面が延長し
ない構造となる。In the present invention, the extending direction of the step is selected so as to be along the <001> crystal axis direction. On the other hand, a step extending in the <011> crystal axis direction at 45 ° is provided. In this case, as shown in the manufacturing process diagram in FIGS. 10A and 10B, even if the growth conditions are the same as those in each of the above examples, the {110} crystal plane does not grow dominantly and the {111} crystal plane does not grow. A crystal plane and {111}
The shape becomes a mixture of B crystal plane and {110} crystal plane. Further, in this case, since the side surface of the mesa portion 12 is constituted by the {110} crystal plane, the lateral growth on the main surface of the substrate is extremely small, and is different from the structure of the semiconductor crystal plane of the present invention described in each of the above examples. Thus, the crystal face does not extend to the base side.
【0035】実施例2 次に本発明半導体結晶面の作製方法を用いて半導体反射
鏡を構成する場合を説明する。例えば図2A及びBに示
す例において、半導体基板に対し45°を成す各{11
0}結晶面を反射鏡4A〜4Dとして構成する。これに
より、図示しないが例えばこの半導体基板上に形成した
共振器から基板の主面に対し平行に出射させる光ビーム
を主面に対し垂直な方向に出射させることができる。ま
た、同様に例えば基板に対し垂直な方向から入射させる
光ビームを基板主面に対し平行に反射するようになす構
成とすることもできる。Embodiment 2 Next, a case where a semiconductor reflecting mirror is formed by using the method for producing a semiconductor crystal plane of the present invention will be described. For example, in the example shown in FIGS. 2A and 2B, each of the {11
The 0 ° crystal plane is configured as reflecting mirrors 4A to 4D. Thus, although not shown, for example, a light beam emitted from a resonator formed on the semiconductor substrate in parallel with the main surface of the substrate can be emitted in a direction perpendicular to the main surface. Similarly, for example, it is also possible to adopt a configuration in which a light beam incident on the substrate from a direction perpendicular thereto is reflected parallel to the main surface of the substrate.
【0036】この場合(0−11)及び(01−1)の
各結晶面も図3に示すように反射鏡4C、4Dとして構
成することにより、例えば4つの反射鏡4A〜4Dに対
向してそれぞれ半導体基板上に共振器を構成し、反射鏡
4A〜4Dにより光ビームを基板主面に対し垂直な方向
に出射させて各光ビーム間を四角形状のパターンとして
出射させることもできる。これらの光ビームは別々に或
いは同時に垂直方向に取り出すことができることとな
り、四角錐の大きさを適切に選定することによって、各
ビーム間の間隔を互いに相互作用を生じない程度に狭小
な間隔とすることができる。In this case, each of the crystal planes (0-11) and (01-1) is also configured as reflecting mirrors 4C and 4D as shown in FIG. 3 so as to face, for example, four reflecting mirrors 4A to 4D. Resonators may be formed on the respective semiconductor substrates, and the light beams may be emitted in a direction perpendicular to the main surface of the substrate by the reflecting mirrors 4A to 4D so that the light beams are emitted in a rectangular pattern. These light beams can be taken out separately or simultaneously in the vertical direction, and by appropriately selecting the size of the pyramid, the intervals between the beams can be made small enough that they do not interact with each other. be able to.
【0037】また上述の図4及び図5において説明した
ように、4つの{110}結晶面により頂部が閉じられ
るまで成長させた構造や、又は図6〜図9において説明
したように、{111}A及び{111}B結晶面が形
成される構造においても{110}結晶面を反射鏡とし
て用いることができる。Also, as described in FIGS. 4 and 5 above, a structure grown until the top is closed by four {110} crystal planes, or as described in FIGS. Even in the structure where the {A} and {111} B crystal planes are formed, the {110} crystal plane can be used as a reflecting mirror.
【0038】実施例3 次に本発明半導体結晶の作製方法を用いて半導体量子構
造を構成する場合を説明する。この場合、先ず図4A及
びBに示すように、頂部が{110}結晶面で閉じられ
た構造とする場合に、その四角錐の頂部付近に量子井戸
構造を形成することができる。Embodiment 3 Next, a case where a semiconductor quantum structure is formed by using the method of manufacturing a semiconductor crystal of the present invention will be described. In this case, as shown in FIGS. 4A and 4B, when the top is closed by a {110} crystal plane, a quantum well structure can be formed near the top of the pyramid.
【0039】即ち図1及び図2に示すように、メサ部1
2上に前述の成長条件即ち成長温度800℃以上、V/I
II比200以上、成長速度0.4nm/s以下としてメ
チル系MOCVDによって例えばAlGaAsより成る
半導体3を、その{100}結晶面より成る上面4Sの
一辺の長さが100nm程度となるまで結晶成長させ、
その後図4A及びBに示す如く{110}結晶面によっ
て頂部が閉じられるまでGaAs或いは前述のAlGa
Asに比しAl含有量の少ないAlGaAsを成長さ
せ、導電領域6を形成する。そして図示しないが、その
後全面的に通常のエピタキシャル成長条件によって導電
領域6に比しAl含有量の大なるAlGaAsを成長す
ることによって、四角錐の頂部に量子ドット(量子箱)
構造を形成することができる。That is, as shown in FIG. 1 and FIG.
2 on the above-mentioned growth conditions, that is, a growth temperature of 800 ° C. or more, V / I
The semiconductor 3 made of, for example, AlGaAs is crystal-grown by methyl MOCVD at an II ratio of 200 or more and a growth rate of 0.4 nm / s or less until the length of one side of the upper surface 4S of {100} crystal plane becomes about 100 nm. ,
Thereafter, as shown in FIGS. 4A and 4B, GaAs or the aforementioned AlGa
A conductive region 6 is formed by growing AlGaAs having a smaller Al content than As. Then, although not shown, a quantum dot (quantum box) is formed on the top of the quadrangular pyramid by growing AlGaAs having a higher Al content than the conductive region 6 over the entire surface under normal epitaxial growth conditions.
A structure can be formed.
【0040】尚、この場合前述の福井らによる文献
(「真空」第34巻第5号(1991)P.501〜)において
{111}B結晶面と{110}結晶面の成長速度の違
いを利用して{111}B基板上に{110}結晶面に
囲まれた三角錐(四面体)状構造を形成しているが、上
述したように本発明では{100}基板を用いている点
においてこの例とは相違する。In this case, in the aforementioned document by Fukui et al. (“Vacuum”, Vol. 34, No. 5, (1991), p. A triangular pyramid (tetrahedron) -like structure surrounded by {110} crystal planes is formed on a {111} B substrate by using the {100} substrate in the present invention as described above. Is different from this example.
【0041】また、本発明においては、図11A及びB
に工程図を示すように、頂部に量子構造6を形成すると
共に、上述の図8において説明した例と同様に、{11
1}B結晶面を発生させてこの部分においてもGaAs
等の導電領域6を成長形成し、その後この{111}B
結晶面が消滅する成長条件に戻して半導体結晶構造を構
成することもできる。In the present invention, FIGS.
As shown in the process diagram, the quantum structure 6 is formed on the top, and as in the example described in FIG.
A 1} B crystal plane is generated and GaAs
And the like, and a conductive region 6 such as {111} B
The semiconductor crystal structure can be formed by returning to the growth condition where the crystal plane disappears.
【0042】即ち前述したように、例えば成長温度か或
いは成長速度の例えばどちらか一方を所定の条件からず
らして半導体例えばAlGaAsの成長を行うと、(1
−11)B結晶面、(11−1)B結晶面を出現させる
ことができる。この{111}B結晶面の一辺は上述の
図4の例と同様に100nm程度とする。次に所定の成
長条件、即ち上述したようにメチル系材料の場合成長温
度800℃以上、V/III比を200以上、成長速度0.
4nm以下としてGaAs等の成長を行い、{111}
B結晶面上に{110}結晶面より成る三角錐状の導電
領域6を形成する。このとき、4つの{110}結晶面
に囲まれた四角錐構造の頂部においても同様に導電領域
6を形成することもできる。That is, as described above, when a semiconductor such as AlGaAs is grown while, for example, either the growth temperature or the growth rate is shifted from predetermined conditions, (1)
-11) B crystal plane and (11-1) B crystal plane can appear. One side of the {111} B crystal plane is about 100 nm as in the example of FIG. Next, under predetermined growth conditions, that is, in the case of a methyl-based material as described above, the growth temperature is 800 ° C. or more, the V / III ratio is 200 or more, and the growth rate is 0.
GaAs or the like is grown to 4 nm or less, and {111}
A triangular pyramid-shaped conductive region 6 composed of a {110} crystal plane is formed on the B crystal plane. At this time, conductive region 6 can also be formed at the top of a quadrangular pyramid structure surrounded by four {110} crystal planes.
【0043】そしてこの後全面的にAlGaAs等の半
導体層を成長させることによって、量子ドットがメサ部
12上のこの場合三箇所に形成された半導体量子構造を
得ることができる。Thereafter, by growing a semiconductor layer of AlGaAs or the like over the entire surface, a semiconductor quantum structure in which quantum dots are formed at three locations on the mesa portion 12 in this case can be obtained.
【0044】このように本発明においては、{111}
B基板を用いることなく、通常の{100}基板により
簡単に半導体量子構造を形成することができる。As described above, in the present invention, {111}
A semiconductor quantum structure can be easily formed using a normal {100} substrate without using a B substrate.
【0045】尚、上述の各実施例においては、AlGa
As系の半導体結晶構造を形成したが、その他例えばA
lGaAsP等の各種化合物半導体の結晶面を作製する
場合に本発明を適用することができ、これを利用して反
射鏡、半導体量子構造を作製し得ることはいうまでもな
い。In each of the above embodiments, AlGa
An As-based semiconductor crystal structure was formed.
The present invention can be applied to the case where crystal planes of various compound semiconductors such as lGaAsP are manufactured, and it is needless to say that a reflector and a semiconductor quantum structure can be manufactured using the crystal planes.
【0046】また更に、上述の各例においては段差とし
て平面正方形状のメサ部を形成したが、例えば平面長方
形状とするとか、或いは〈001〉方向に延長するリッ
ジ(ストライプ)状とする場合にも同様にそのエッジか
ら延長する{110}結晶面を構成することができ、こ
れを利用して例えば半導体量子細線構造をつくる等、本
発明は上述の各例の他各種変形変更をなし得るものであ
る。Further, in each of the above-described examples, a planar square mesa portion is formed as a step. However, for example, a planar rectangular shape or a ridge (stripe) shape extending in the <001> direction may be used. Similarly, a {110} crystal plane extending from the edge can be formed, and the present invention can make various modifications and changes other than the above-described examples, for example, by making a semiconductor quantum wire structure using the crystal plane. It is.
【0047】[0047]
【発明の効果】上述したように本発明によれば、基板に
対し45°を成す{110}結晶面を{111}B基板
のような特殊な基板を用いることなく通常の{100}
結晶面を主面とする基板を用いて形成することができ、
従って成長条件を比較的緩やかにして成長することがで
きる。As described above, according to the present invention, the {110} crystal plane which forms an angle of 45 ° with the substrate can be formed without using a special substrate such as a {111} B substrate.
It can be formed using a substrate having a crystal plane as a main surface,
Therefore, the growth can be performed under relatively mild growth conditions.
【0048】そして基板に対し45°を成す{110}
結晶面によって囲まれた四角錐状の半導体結晶面により
反射鏡を構成することによって、基板と平行な方向の光
ビームをこの反射鏡により基板に対し垂直な方向への変
換が可能となり、しかも四面が同時に得られるため、単
数又は複数の光ビームに対応して設計に自由度をもたせ
て構成することができる。Then, {110} which forms 45 ° with respect to the substrate.
By forming a reflecting mirror with a semiconductor crystal surface of a quadrangular pyramid surrounded by a crystal surface, a light beam in a direction parallel to the substrate can be converted to a direction perpendicular to the substrate by the reflecting mirror. Can be obtained at the same time, so that the design can be made flexible with respect to one or a plurality of light beams.
【0049】またこの四角錐の大きさを適切に選定する
ことにより、各光ビームの間隔を狭小化することができ
て、例えば光ディスク装置や光磁気ディスク装置等にお
いてその読み出し光に複数の光ビームを用いる場合に、
各ビームの間隔を一つの光学系によって集束し得る程度
に近づけることができるなど、装置構成の改善をはかる
ことができる。By appropriately selecting the size of the quadrangular pyramid, the interval between the light beams can be narrowed. For example, in the case of an optical disk device or a magneto-optical disk device, a plurality of light beams When using
The configuration of the apparatus can be improved, for example, the distance between the beams can be made close enough to be focused by one optical system.
【0050】また本発明によれば、{100}基板を使
って容易に量子箱、量子細線等の半導体量子構造が得ら
れ、制御性良くまた再現性良く半導体量子構造を作製す
ることができる。Further, according to the present invention, a semiconductor quantum structure such as a quantum box or a quantum wire can be easily obtained using a {100} substrate, and a semiconductor quantum structure with good controllability and good reproducibility can be manufactured.
【図1】半導体結晶面の作製方法の一例の工程図であ
る。FIG. 1 is a process chart of an example of a method for manufacturing a semiconductor crystal plane.
【図2】反射鏡の一例の製造工程図である。FIG. 2 is a manufacturing process diagram of an example of a reflecting mirror.
【図3】反射鏡の一例の略線的斜視図である。FIG. 3 is a schematic perspective view of an example of a reflecting mirror.
【図4】半導体結晶面の略線的平面図及び略線的斜視図
である。FIG. 4 is a schematic plan view and a schematic perspective view of a semiconductor crystal plane.
【図5】半導体結晶面の略線的斜視図である。FIG. 5 is a schematic perspective view of a semiconductor crystal plane.
【図6】半導体結晶面の略線的斜視図である。FIG. 6 is a schematic perspective view of a semiconductor crystal plane.
【図7】半導体結晶面の略線的平面図である。FIG. 7 is a schematic plan view of a semiconductor crystal plane.
【図8】半導体結晶面の略線的斜視図である。FIG. 8 is a schematic perspective view of a semiconductor crystal plane.
【図9】半導体結晶面の略線的斜視図である。FIG. 9 is a schematic perspective view of a semiconductor crystal plane.
【図10】半導体結晶面の製造工程図である。FIG. 10 is a manufacturing process diagram of a semiconductor crystal plane.
【図11】半導体量子構造の一例の製造工程図である。FIG. 11 is a manufacturing process diagram of an example of a semiconductor quantum structure.
2 段差 3 半導体 4 反射鏡 6 導電領域 12 メサ部 2 step 3 semiconductor 4 reflector 6 conductive area 12 mesa
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平2−137316(JP,A) 特開 平2−163928(JP,A) 特開 平2−165679(JP,A) 特開 平3−219623(JP,A) 特開 平4−118916(JP,A) 特開 平5−3375(JP,A) 特開 平5−299636(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 21/205 H01L 29/04 H01S 5/34 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-2-137316 (JP, A) JP-A-2-1633928 (JP, A) JP-A-2-165679 (JP, A) JP-A-3- 219623 (JP, A) JP-A-4-118916 (JP, A) JP-A-5-3375 (JP, A) JP-A-5-299636 (JP, A) (58) Fields investigated (Int. 7 , DB name) H01L 21/205 H01L 29/04 H01S 5/34
Claims (5)
板上に、側面が{010}結晶面で且つ上記側面に囲ま
れた面が上記主面に平行な面から成る段差を形成し、該
段差を有する半導体基板上に半導体を気相成長すること
で上記段差のエッジに対応する部分から延びる{11
0}結晶面を生じさせ、該{110}結晶面を構成面と
して上記主面に対し45°の角度を有する半導体結晶面
を作製することを特徴とする半導体結晶面の作製方法。1. A step is formed on a semiconductor substrate having a {100} crystal plane as a principal plane, the step being a {010} crystal plane and a plane surrounded by the side plane being a plane parallel to the principal plane. Extending from a portion corresponding to the edge of the step by growing a semiconductor on the semiconductor substrate having the step by vapor phase growth.
A method for producing a semiconductor crystal plane, comprising: producing a 0 crystal plane, and producing a semiconductor crystal plane having an angle of 45 ° with respect to the main surface with the {110} crystal plane as a constituent plane.
板上に、〈001〉結晶軸方向に延びるエッジを有する
成長阻止層を形成し、上記成長阻止層を形成した半導体
基板上に半導体を気相成長し、上記半導体基板の成長阻
止層の形成されていない部分上で上記エッジに対応する
部分から延びる{110}結晶面を生じさせ、該{11
0}結晶面を構成面として上記主面に対し45°の角度
を有する半導体結晶面を作製することを特徴とする半導
体結晶面の作製方法。2. A growth inhibition layer having an edge extending in a <001> crystal axis direction is formed on a semiconductor substrate having a {100} crystal plane as a main surface, and a semiconductor is formed on the semiconductor substrate on which the growth inhibition layer is formed. Is vapor-phase grown to generate a {110} crystal plane extending from a portion corresponding to the edge on a portion of the semiconductor substrate where the growth inhibition layer is not formed,
A method for producing a semiconductor crystal plane, characterized by producing a semiconductor crystal plane having a 0 ° crystal plane as a constituent plane and having an angle of 45 ° with respect to the main surface.
主面に対しほぼ垂直な方向に反射するか、または上記主
面に対し垂直に入射する光を上記主面に対しほぼ平行な
方向に反射する上記請求項1または上記請求項2に記載
の半導体結晶面の作製方法により作製したことを特徴と
する半導体結晶面より成る反射鏡。3. Reflecting light traveling parallel to the main surface in a direction substantially perpendicular to the main surface, or reflecting light incident perpendicular to the main surface in a direction substantially parallel to the main surface. 3. A reflecting mirror comprising a semiconductor crystal surface, which is produced by the method for producing a semiconductor crystal surface according to claim 1 or 2, which reflects light in a direction.
板上に、側面が(010)、(001)、(0−1
0)、(00−1)各結晶面から成り且つ上面が上記主
面に平行な面から成るメサ部を有し、該メサ部を有する
半導体基板上に、半導体が気相成長されて上記メサ部の
エッジに対応する部分から延びる(110)、(10
1)、(1−10)、(10−1)各結晶面が形成され
て反射鏡が構成され、上記各反射鏡はそれぞれ上記主面
に対し平行に進行する光を上記主面に対しほぼ垂直な方
向に反射するか、或いは上記主面に対し垂直に入射する
光を上記主面に対しほぼ平行な方向に反射するようにな
されたことを特徴とする半導体結晶面より成る反射鏡。4. On a semiconductor substrate having a (100) crystal plane as a main surface, side surfaces are (010), (001), and (0-1).
0) and (00-1) a mesa portion having a crystal plane and an upper surface formed of a plane parallel to the main surface, and a semiconductor is vapor-phase grown on a semiconductor substrate having the mesa portion to form the mesa. (110), (10) extending from a portion corresponding to the edge of the portion
1), (1-10), and (10-1) each of which has a crystal plane formed thereon to form a reflecting mirror. Each of the reflecting mirrors transmits light traveling parallel to the main surface substantially to the main surface. A reflecting mirror comprising a semiconductor crystal surface, wherein the reflecting mirror reflects light in a direction perpendicular to the principal surface or in a direction substantially parallel to the principal surface.
板上に、側面が(010)、(001)、(0−1
0)、(00−1)各結晶面から成り且つこれらに囲ま
れた面が上記主面に平行な面から成るメサ部を有し、該
メサ部を有する半導体基板上に、半導体が気相成長され
て上記メサ部のエッジに対応する部分から延びる(11
0)、(101)、(1−10)、(10−1)各結晶
面が形成され、これら(110)、(101)、(1−
10)、(10−1)各結晶面の内少なくとも2つの結
晶面で囲まれた領域に導電領域を有し、該導電領域に電
子が閉じ込められて量子構造が構成されて成ることを特
徴とする半導体量子構造。5. On a semiconductor substrate having a (100) crystal plane as a main surface, side surfaces (010), (001), and (0-1) are formed.
0), (00-1) A mesa portion composed of crystal planes and surrounded by these crystal planes is formed of a plane parallel to the main surface, and a semiconductor is vapor-phased on a semiconductor substrate having the mesa portion. Grown from the portion corresponding to the edge of the mesa portion (11
0), (101), (1-10) and (10-1) crystal planes are formed, and these (110), (101) and (1-
10), (10-1) wherein a quantum region is formed by confining electrons in the conductive region in a region surrounded by at least two crystal planes of each of the crystal planes. Semiconductor quantum structure.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP04260034A JP3128987B2 (en) | 1992-09-29 | 1992-09-29 | Method for manufacturing semiconductor crystal plane, reflector comprising semiconductor crystal plane, and semiconductor quantum structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP04260034A JP3128987B2 (en) | 1992-09-29 | 1992-09-29 | Method for manufacturing semiconductor crystal plane, reflector comprising semiconductor crystal plane, and semiconductor quantum structure |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH06112134A JPH06112134A (en) | 1994-04-22 |
JP3128987B2 true JP3128987B2 (en) | 2001-01-29 |
Family
ID=17342388
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Application Number | Title | Priority Date | Filing Date |
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JP04260034A Expired - Fee Related JP3128987B2 (en) | 1992-09-29 | 1992-09-29 | Method for manufacturing semiconductor crystal plane, reflector comprising semiconductor crystal plane, and semiconductor quantum structure |
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Country | Link |
---|---|
JP (1) | JP3128987B2 (en) |
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1992
- 1992-09-29 JP JP04260034A patent/JP3128987B2/en not_active Expired - Fee Related
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JPH06112134A (en) | 1994-04-22 |
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