JP3127950B2 - ATM bus system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter suitable for simultaneous processing of control processing and communication processing in a computer device such as a personal computer or a workstation.
It relates to a TM bus system.

[0002]

2. Description of the Related Art In recent years, in a computer device such as a personal computer and a workstation, a huge amount of information transfer accompanying image processing, simultaneous processing in a plurality of media, real-time performance in image communication, and the like have been performed in order to support multimedia. Various processing functions such as securing
That is, a function of performing the control processing and the communication processing in parallel is required. On the other hand, conventionally, measures have been taken to realize these requirements by a method of increasing the information transfer speed of a single bus provided inside a computer.

FIG. 16 is a block diagram showing a basic configuration of a conventional information transfer system. The central control unit 1 uses the control signals 6a, 6b, 6c transferred via the control bus 8 to store the information as the bus user, the information storage unit 2, the information processing unit 3,
It controls the network line connection unit 4. Information storage unit 2
Accumulates strong real-time media information. Here, information such as images and sounds that are required to be processed in real time is referred to as media information having strong real-time properties. The information processing section 3 processes the media information having a strong real-time property into a predetermined format.

A network line connection unit 4 has an interface with an ATM network 5, and is connected to the present system and A
The connection with the TM network 5 is performed. The signal 7a is media information having a strong real-time property transferred from the information storage unit 2 to the information processing unit 3. Similarly, the signal 7b is transmitted from the information processing unit 3 via the network line connection unit 4 to the ATM.
This is media information having strong real-time properties transferred to the network 5.

Here, ATM (Asynchronous Transfer)
Mode: Asynchronous transfer mode) Network is several tens of bp
All communication information from s to several hundred Mbps is stored in a fixed-length cell (packet) of 53 bytes (1 byte = 8 bits).
This is a communication network that performs high-speed processing by high-speed packet exchange by dividing the data into transmission lines and transferring the data through a transmission path. A cell in the ATM network includes a 5-byte header (control information section) and a 48-byte information field. The advantage of the ATM network is its high flexibility and high efficiency in that communication traffic of various speeds including high speed can be mixed and transmitted.

[0006] Next, a moving image signal is taken as an example of media information having a strong real-time property, and the above-described configuration in a case where the moving image signal is transferred from the information storage unit 2 to another computer device via the ATM network 5 is described. The operation of the information transfer system will now be described. The central control unit 1
The control signal 6b transmitted via the control bus 8 is used to instruct the information processing section 3 to receive a moving image signal. As a result, the information processing section 3
A signal indicating whether or not a moving image signal can be received is returned.

After confirming that the information processing unit 3 is capable of receiving a moving image signal, the central control unit 1 uses the control signal 6a transmitted through the control bus 8 to send the information to the information storage unit 2. Then, transmission of the moving image signal to the information processing unit 3 is instructed. Then, the information storage unit 2 transmits the moving image signal 7 a previously stored in the information storage unit 2 to the information processing unit 3 via the control bus 8. The information processing unit 3 receives the moving image signal 7a transmitted via the control bus 8, and processes the moving image signal 7a into a predetermined format.

Next, the central control unit 1 uses the control signal 6c transmitted via the control bus 8 to send an ATM signal of the moving image signal 7b obtained by processing the moving image signal 7a to the network line connecting unit 4. The transfer to the network 5 is instructed.
As a result, the network line connection unit 4 returns to the central control unit 1 a signal indicating whether or not transfer of the moving image signal is possible. After confirming that the network line connection unit 4 can transfer the moving image signal, the central control unit 1 sends a network signal to the information processing unit 3 using the control signal 6b transmitted through the control bus 8. Line connection unit 4
To transmit the moving image signal 7b to the.

Then, the information processing section 3 outputs the moving image signal 7b
To the network line connection unit 4 via the control bus 8. Finally, network line connection unit 4
Transfers the video signal 7b to the ATM network 5.

[0010]

By the way, in the above-mentioned conventional information transfer system, the control information and the real-time media information at the time of continuous data transfer compete on the same bus as the amount of data to be processed increases. In addition, there is a drawback that queuing occurs between the pieces of information, making it difficult to secure real-time properties.

As an example, in the conventional information transfer system shown in FIG.
In order to transfer the moving image signal 7b through the TM network 5, the moving image signal 7b is transmitted from the information processing unit 3 to the network line connecting unit 4
During the transfer to the central control unit 1, the control signal 6a
When the control signal 6b is used to instruct the information storage unit 2 to transmit, or the control signal 6b is used to instruct the information processing unit 3 to receive another moving image signal, the control signals 6a and 6b and the moving image signal 7b are used. Conflict with each other on the control bus 8, so that the moving image signal 7
In some cases, the transfer of b must be interrupted.

[0012] The interruption of the transfer causes a decrease in image quality and a disturbance in the image of the computer of the communication partner receiving the moving image signal 7 b via the ATM network 5. As a result, in multimedia communication for processing moving image signals and the like, processing of media information having strong real-time properties has often been interrupted. In order to address this problem, a technology developed by Tran Switch (USA) to transfer ATM information to a bus.
A Cell Bus (transfer method) using CUBIT (VLSI) is known.

An STM (Synch) different from the control bus
As a technology for transmitting information by providing a ronous Transfer Mode (synchronous transfer mode) bus, MVIP (Multivender In
Integration Protocol) is known. This standard is 1
990, Natural Microsystems (NMS),
Announced by Mitel and five other companies, and later in 1994, as an industry-neutral organization, GO-MV
IP (The Gloval Organization for MVIP) was launched. However, a technique for transferring information using an ATM bus together with a control bus has not been disclosed.

In multimedia communication, etc.,
It is necessary to perform so-called broadcast communication in which media information with strong real-time properties is simultaneously transferred to multiple bus users in the computer. However, the conventional broadcast communication method requires a plurality of bus users as information transfer destinations. And sent and received once in turn. That is, in the conventional method,
In order to transfer the same data to a plurality of bus users, the data is held and a transfer destination address is specified for each transfer. However, such a method has a problem that it takes an enormous amount of time in proportion to the number of receiving bus users to complete transmission of information to all receiving bus users.

In order to solve such a problem, the address information of all the receiving bus users or the address information specified so that all the receiving bus users can be specified at the same time is transferred to the header portion of the information cell. And transmitting and receiving. However, in these cases, the generation of address information in the transmission circuit of the transmission-side bus user and the determination processing in the reception circuit of the reception-side bus user (the address information in the header replaces the specified address information described above) There is a drawback that the process of determining whether or not the transmission is specified) is complicated, and the transmission processing time becomes long.

Further, conventionally, a single bus is shared by a plurality of bus users, and a bus arbitration circuit is provided on the bus so that each bus user does not compete with data transmitted from each bus user on the bus. There is an information transfer system that arbitrates data transfer. In this type of information transfer system, when a bus user has data to be transferred preferentially, when the bus user notifies a bus use request to the bus arbitration circuit, a priority step indicating the priority of data transfer is performed. The bus arbitration circuit, which has received the bus use request, performs arbitration from a higher priority stage based on the priority stage assigned to the bus use request, and sends the arbitration circuit to one bus user according to the adjustment result. There is a type in which a bus use permission is given and only the bus user who has received the use permission transfers data.

In such an information transfer system, conventionally, for example, when a plurality of bus users transmit a bus use request to which the same priority level is assigned, the arbitration circuit sets the Only one was authorized to use the bus. For this reason, the bus user to whom the use permission has not been given has at least the bus user to whom the permission has been given, despite having transmitted a bus use request at the same priority level as the bus user to whom use permission has been given. Until the data transfer was completed, the bus could not be used.

Further, in the conventional information transfer system, for example, in an ATM bus system for transferring information in an ATM transfer mode based on a fixed length cell unit, a case where an ATM bus is extended to increase the information transfer capacity. , Use request phase (stage in which the bus user transmits a bus use request to the bus arbitration circuit), bus use permission phase (arbitrates the bus use request received by the bus arbitration circuit, and permits the bus user to use the bus according to the result. ) And a data transmission / reception phase (a stage in which a bus user who has received a bus use permission transmits data to a target bus user) has the same bus cycle before and after bus expansion, and the bit width of the ATM bus is maintained. A method of expanding only the data transfer amount and expanding the data transfer amount per transfer can be considered.

However, in such a method, a bus user corresponding to the bit width of the expanded ATM bus can be connected to the expanded ATM bus, but a bus user corresponding to the bit width of the ATM bus before expansion is connected to the expanded ATM bus. Cannot connect to the bus. Further, the bus arbitration circuit has a problem that the bus arbitration circuit must be changed to one corresponding to the bit width of the expanded ATM bus.

The present invention has been made in view of the above-described circumstances, and increases the amount of information and the type of information associated with the use of multimedia, secures real-time properties, and changes in the scale and generation pattern of data to be processed. A that can flexibly respond to
It is an object to provide a TM bus system.

[0021]

According to a first aspect of the present invention, there is provided an AT for performing information transfer in an ATM transfer mode based on fixed-length cell units on a bus which is an information transfer path.
An M bus system for transmitting the information;
In the ATM bus system which performs only one cell unit of information transfer at the same time when a plurality of bus use requests of the TM bus are generated, a plurality of buses connected to the ATM bus and performing the information transfer by sharing the bus are provided. A bus user, and a bus arbitration means for selecting a single bus use request from a plurality of bus use requests transmitted simultaneously by the bus user and determining a bus user who has made the bus use request. An ATM bus system, wherein the cell unit is AT
An extension header in addition to the ATM bus data including an M header, the extension header comprising: bus use request information for the bus user to make the bus use request to the bus arbitration means; Consists of bus use permission information indicating the only bus user determined by the user, and user address information for designating a transmission or reception bus user,
The bus arbitration means arbitrates a plurality of bus use requests notified by the bus use request information, and uses the bus use permission information to give a bus use permission given to only one bus user to all the bus users. And the bus user determines the bus use permission information so that only the bus user who has received the bus use permission performs the cell-unit information transfer within the same cell time as the extension header transfer. The bus user who has determined the user address information and determined that the address is the corresponding address is
An ATM bus system for receiving M bus data.

According to a second aspect of the present invention, in the ATM bus system according to the first aspect, a central control means for controlling processing and information transfer performed by each of the bus users; A control bus for transferring control information for controlling each bus user to a user.

According to a third aspect of the present invention, in the ATM bus system according to the second aspect, an address unique to the bus user that is the source of the information is provided to all the bus users that receive the information. The bus user, which is set in advance via the control bus and transmits information, assigns an address unique to the own bus user to the extension header of the cell unit, and then transmits the cell unit within the bus user. AT from circuit
All bus users transmitting on the M bus and receiving information are individually and in parallel with the user address of the transmission source preset via the control bus and the AT.
A comparison with an address given to a cell unit on the M bus is performed, and when an address matches based on the comparison result, the broadcast is performed by receiving the cell unit.

According to a fourth aspect of the present invention, in the ATM bus system according to any one of the first to third aspects, a plurality of priority stages indicating the priority of the information transfer are provided, and Selects one priority stage from among the plurality of priority stages and adds it to the bus use request information, and the bus arbitration means permits the bus use at a certain priority stage to be higher than the certain priority stage. When there is no bus use request, the bus use request of the priority stage lower than the certain priority stage is ignored, and the bus is sequentially and equally used for the certain priority stage and the bus use request of the same priority stage as the certain priority stage. Multi-stage priority bus arbitration for granting bus use permission is performed.

According to a fifth aspect of the present invention, in the ATM bus system according to any one of the first to fourth aspects, the ATM bus is a main bus in which two identical buses are installed in parallel. And a sub-bus, wherein the bus arbitration means comprises two master controllers for separately arbitrating the bus use request from the bus user in one data transfer on the main bus and the sub-bus, An ATM bus system comprising a synchronization control unit for synchronizing a bus cycle of the sub-bus, wherein the bus user is connected to the main bus and provided so as to share the main bus and the sub-bus; , Are connected to the main bus and the sub-bus, respectively. A bus controller that issues the bus use request to a master controller and performs data transfer when a bus use permission is obtained from the master controller; a bus use state detector that detects a use state of an ATM bus; Used bus selecting means for switching between one data unit transfer on the main bus and the sub bus in accordance with the bus congestion information by the use state detecting means; For the unit transfer, first, the main bus is used, and the sub bus is used only when the bus use state detecting means detects that the main bus is congested.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an ATM bus system according to the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1 is a block diagram showing the configuration of an ATM bus system according to a first embodiment of the present invention. In this figure, parts corresponding to the respective parts in FIG. 16 are denoted by the same reference numerals, and description thereof will be omitted.

In FIG. 1, reference numerals 10a to 10d denote bus users of the ATM bus system. Each bus user 10a-
Different addresses are assigned to 10d, and it is possible to uniquely determine which bus user is by specifying the address. An ATM bus 11 is a common data transfer path of the ATM bus system. Each of the bus users 10a to 10d can directly transfer data to an arbitrary partner on the bus via the ATM bus 11. The data transferred here is media information having strong real-time properties. Also, 1
2 is a bus arbitration circuit.

Here, generally, only one information transfer is performed on the bus at the same time. For this purpose, the bus arbitration circuit 12 determines which bus user can transmit information at a certain time, and arbitrates a conflict that occurs when the bus users 10a to 10d share the data transfer path. The control bus 8 includes a central control unit 1 for each bus user 10.
This is a transfer path used when transferring control signals to a to 10d, and is not used for transferring media information having strong real-time properties.

On the other hand, in this ATM bus system,
The data transfer is performed in a so-called ATM transfer mode including a plurality of cells of a fixed length cell unit. FIG. 2 shows an ATM bus 11
This shows an example of the data configuration in the unit of one cell above. As shown in the figure, the data of one cell unit is composed of an extension header provided at the head and ATM bus data. Further, the extension header is composed of three types of information fields of bus use request information, bus use permission information, and bus user address information.

Here, the bus use request information in the extension header is transmitted from each bus user to the bus arbitration circuit 12 by the AT.
This field stores request information for requesting permission to use the M bus 11. The bus use permission information is an information field for designating the only bus user selected by the bus arbitration circuit 12 from the bus users who have requested the use of the bus in a procedure described later. Further, the user address information is an information field including an address for designating another bus user when a certain bus user sends data to another bus user.

On the other hand, the ATM bus data is composed of 53 bytes, and includes an ATM header defined by the international standard ITU-TS (International Telecommunication Union-Telecommunication Standardization Division) or the ATM Forum, and an ATM field which is an information field. Consists of a payload.

Next, with reference to FIG.
The operation of the TM bus system will be described. Here, a case is shown in which data transfer from the bus user 10a to the bus user 10d and data transfer from the bus user 10b to the bus user 10c are performed. The central control unit 1 instructs the bus users 10a and 10b to transmit data via the control bus 8. As a result, the bus user 10a transmits the transmission data SDa to the ATM bus 11 in cell units, and the data is received by the bus user 10d as reception data RDd in cell units.

Similarly, the bus user 10b transmits the transmission data S
Db is transmitted to the ATM bus 11 in units of cells, and this data is received by the bus user 10c as received data RDc in units of cells. Reference numeral 13 denotes a cell array on the ATM bus 11, and in the order determined by the bus arbitration circuit 12,
The figure shows a state in which cells are sequentially arranged on the ATM bus 11. Data transfer is performed by sequentially repeating three phases of a bus use request phase, a bus use permission phase, and a data transmission / reception phase shown in FIG. 2 during one cell time. Hereinafter, description will be made with reference to FIGS.

(1) Bus use request phase When a request for information transfer using the bus occurs, each of the bus users 10a to 10d uses the bus use request information in common and transmits the request via the ATM bus 11. Arbitration circuit 1
Notify 2.

(2) Bus Use Permission Phase The bus arbitration circuit 12 monitors the bus use request information of the cell notified from each of the bus users 10a to 10d at the cell time, and makes the bus user making the bus use request. Find out. As a result of the monitoring, from among bus requests from a plurality of bus users, the ATM bus 1 is sent according to a predetermined procedure.
1 is used to determine the only bus user who is authorized to send one cell of data. After selecting one of the bus users as described above, information on the determined bus user is notified to all the bus users 10a to 10d via the ATM bus 11 as bus use permission information.

(3) Data transmission / reception phase Each of the bus users 10a to 10d that has made the bus use request is
The contents of the bus use permission information included in the data notified from the bus arbitration circuit 12 are checked to determine whether or not the user is a bus user who has been granted data transmission permission. As a result of this determination, if it is found that transmission permission has been given,
The bus user sends one cell of data to the ATM bus 11. At the same time, each of the bus users 10a to 10d determines the user address information and, when the address specified by the information corresponds to the address to be received, receives the ATM bus data following the user address information.

In this manner, data transmission / reception is performed between the bus users 10a to 10d in units of fixed-length cells. As described above, in the present embodiment, the control signal is transferred via the control bus 8, and the media information having a strong real-time property is transferred via the ATM bus 11. Therefore, for example, a continuous moving image signal is represented by A
During the transfer of the moving image signal from the bus user 10a to the bus user 10d for transfer via the TM network, the central control unit 1 issues an instruction to transmit to the bus user 10b via the control bus 8. Is performed, the moving image signal from the bus user 10a is transferred via the ATM bus 11, so that the transfer is not interrupted.

As described above, since the control signal and the media information having a strong real-time property are transferred through different buses, they are completely separated from each other, and mutual influence is avoided. Therefore, no competition occurs between the two, and real-time properties such as continuity of moving image signals are ensured.
Further, since the ATM bus 11 uses the ATM system as its information transfer system in addition to sharing the function with the control bus 8 as the information transfer bus as described above, it has the following features. The ATM system is a system in which all information is divided into fixed-length packets called cells (53 bytes in this system + extension header) and transferred at a high speed. Transfer rate can be selected.

In addition, by using the ATM system, a plurality of successive data do not affect each other at the same time, and the transfer state can be maintained. Furthermore, since the media information having a strong real-time property is directly transferred by the ATM system via the ATM bus 11, it is possible to connect the transfer information to the ATM network without the network line connection unit having a conversion device. In addition, it is possible to prevent deterioration of information quality at the time of network connection.

[Second Embodiment] In a second embodiment of the present invention, a broadcast communication between a single transmitting-side bus user and a plurality of receiving-side bus users on an ATM bus is flexibly supported. A description will be given of an ATM bus system that can be used. The configuration of the ATM bus system according to this embodiment is the same as that of the ATM bus system according to the first embodiment shown in FIG. Further, the information cell according to the present embodiment includes:
This is the same as the information cell in the first embodiment shown in FIG. 2, but the user address information in the extension header is not the user address of the receiver but the user address of the sender. Further, arbitration by the bus arbitration circuit 12 is performed in exactly the same manner.

Next, the operation of broadcast communication by the ATM bus system having the above configuration will be described with reference to FIG. Here, as an example, a case where broadcast communication is performed from the bus user 10a to the bus users 10b and 10c is shown. First, when a request to transmit information from the bus user 10a to the bus users 10b and 10c occurs, the bus user 10b and the bus user 10c are set with the address of the bus user 10a via the control bus 8. Then, the bus user 10b and the bus user 10c store the address in a built-in memory in a receiving circuit (not shown).

Next, the bus user 10a on the transmitting side,
The data to be transmitted is stored in the ATM payload portion of the information cell, and the address of itself (bus user 10a) is stored in the user address information portion of the extension header. Then, the bus user 10a sends out the information cell created by the above method onto the ATM bus 11 by using a transmission circuit (not shown). Next, the bus user 1 on the receiving side
0b constantly monitors the ATM bus 11, and the ATM bus 1
When an information cell is transmitted onto the information cell 1, the information cell is fetched by using a receiving circuit, and the transmission-side user address information stored in the extension header portion is read.

Then, the bus user 10b compares the transmission-side user address information with the address (address set via the control bus 8) stored in the internal memory. As a result, if the addresses match, the data of the ATM payload portion is subsequently read. At this time, a similar process is performed also in the bus user 10c in parallel with the above-described process by the bus user 10b (incorporation of information cells, comparison of addresses, reading of data in the payload portion). That is, the bus user 10
b and the bus user 10c individually and in parallel take in information cells, compare addresses, and read data in the payload portion.

By the above procedure, the broadcast communication from the bus user 10a to the bus user 10b and the bus user 10c is performed. The bus user 10a divides the data into a plurality of information cells and stores the data, and sends the information cells individually to the ATM bus 11 as shown in FIG. And
The bus user 10b and the bus user 10c individually receive the plurality of information cells transmitted on the ATM bus 11 by the same processing as the above-described receiving method, and the ATM of the information cells is received.
Read data from the payload.

As described above, according to the broadcast method in the ATM bus system according to the present embodiment, a plurality of receiving-side bus users can receive information in parallel at the same time. The time required for is reduced. Further, the transmitting bus user need only always store his / her own address information as a process of storing the address information in the information cell. The receiving bus user receives the transmitting user address given via the control bus 8. Since it is only necessary to detect information, it is possible to simplify the processing in both bus users on the transmission side and the reception side.

[Third Embodiment] In a third embodiment of the present invention, when a bus user notifies a bus arbitration circuit of a bus use request, the bus arbitration circuit adds a priority stage indicating the priority of data transfer and transmits the data. When the arbitration circuit receives a bus use request, in an ATM bus system that performs arbitration from a higher priority stage based on the priority stage given to the bus use request, the bus arbitration circuit sends a bus use request with the same priority stage to a plurality of bus users. An ATM bus system provided with a bus arbitration circuit that performs arbitration so that the bus user can use the bus equally when transmitted from the ATM bus system will be described.

The operation of the above ATM bus system will be described below with reference to FIGS. FIG. 9 shows the configuration of information cells transmitted and received at that time. FIG. 5 is a block diagram showing the configuration of the ATM bus system according to the embodiment. In this figure, parts corresponding to the respective parts in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

In the bus users 10a to 10d, 14
Reference numerals a to 14d denote a data transfer control circuit, which selects one of a plurality of priority stages and performs a request for use of the ATM bus 11 and data transfer. Also, 15a to 15d
Is a bus controller, which has an input / output function on the ATM bus 11. In the bus arbitration circuit 12, 1
Reference numeral 7 denotes a master controller, and bus users 10a to 1
The input / output of each of the bus controllers 15a to 15d at 0d is controlled. .., 18n are priority stage arbitration circuits, each of which has priority order 1, priority stage 2, priority stage 3,.
Arbitration of bus use permission in Further, reference numeral 19 denotes a bus use permission transmission circuit, which is a priority stage arbitration circuit 18a to 18a.
18n, and collects the arbitration results by the master controller 1
Then, all the bus users 10a to 10d are notified of the bus use permission via the server 7. Here, it is assumed that priority level 1 has the highest priority, followed by priority level 2, priority level 3,..., Priority level n. Also, the priority stage arbitration circuits 18a to 18n are mounted by the number of priority stages supported by the present system.

First, in the bus use request phase, when the bus users 10a to 10d have data to be transferred, the data transfer control circuits 14a to 14d select one from a plurality of priority stages and provide the priority stage information. 16a-1
The bus use request information 20 to which 6d is added is transmitted to the master controller 17 via the bus controllers 15a to 15d. Then, the master controller 17 sets the received bus use request information to 20a and sets the priority stage 1 arbitration circuit 1 to 20a.
Hand over to 8a. In this figure, the bus user 10
a and bus user 10b perform priority stage 1
0c and the bus user 10d specify the priority stage 2 respectively.

Next, in the bus use permission phase,
The priority stage 1 arbitration circuit 18a transmits the bus use request information 20a
If there is a priority stage 1 request in
Mediate between each other. Then, the arbitration result 21 a is passed to the bus use permission transmission circuit 19. On the other hand, when there is no request of the priority stage 1, the bus use request information is passed to the priority stage 2 arbitration circuit 18b as 20b. At this time, the priority stage 2 arbitration circuit 18b passes the arbitration result 21b to the bus use permission transmitting circuit 19 when there is a request of the priority stage 2, and sets the bus use request information to 20c when there is no request, and sets the bus use request information to 20c. Transfer to arbitration circuit 18c. Here, arbitration between the same priority stages in each arbitration circuit is performed so that the corresponding bus users are sequentially and equally selected.

Similarly, if there is a request that can be arbitrated by each arbitration circuit, arbitration is performed by the arbitration circuit, and the arbitration result is transferred to the bus use permission transmission circuit 19. And
The bus use permission transmission circuit 19 outputs the arbitration results 21a to 21n.
, The bus use permission information 22 including the information on the bus user determined by the arbitration result is transferred to the master controller 17. Further, the master controller 17 notifies the same information 22 to all the bus users 10a to 10d via the ATM bus 11.

In the case of this figure, the bus users 10a,
10b, 10c, 10d are respectively priority stages 1, 1, 2,
Since 2 is specified, the arbitration result 21a for giving permission to the bus user 10a or the bus user 10b is transmitted to the bus use permission transmission circuit 19 by the priority stage 1 arbitration circuit 18a. Then, bus use permission information 22 for permitting use of the ATM bus 11 is transmitted to the bus users 10a to 10d.

Next, in the data transmission / reception phase, each of the bus users 10a to 10d that has made the bus use request checks the contents of the bus use permission information included in the data notified from the bus arbitration circuit 12, and transmits the data. It is determined whether the user is an authorized bus user. As a result of this determination, if it is determined that the transmission permission has been given, the bus user transmits one cell of data to the ATM bus 11. In this case, the bus user 10a and the bus user 10b
And alternately transfer data. This is shown in FIG.

FIG. 6 shows the flow of data on the ATM bus in the priority stage of each bus user shown in FIG. Here, the bus user 10a has priority level 1, the bus user 10b has priority level 1, and the bus user 10c.
Is the priority stage 2 and the bus user 10d is the priority stage 2, so that the ATM bus 11 is used alternately by the data of the bus user 10a and the bus user 10b.

Similarly, FIG. 7 shows the bus user 10a in FIG.
In this case, the bus user 10a has no use request, the bus user 10b has the priority stage 1, the bus user 10c has the priority stage 2, and the bus user 10c has no use request.
Since d is in the priority stage 2, the ATM bus 11 is used by data of only the bus user 10b.

Similarly, FIG. 8 shows the case where the use request of the bus user 10b is further eliminated in FIG.
The bus user 10a has no use request, the bus user 10b has no use request, the bus user 10c has priority stage 2, and the bus user 10d has priority stage 2, so the bus user 10c
And the ATM bus 1 alternately according to the data of the bus user 10d.
1 is used.

As described above, in this embodiment, 1
In a system in which one ATM bus is shared by a plurality of bus users, the bus user adds priority stage information to the bus use request information and notifies the bus arbitration circuit of the information.
The bus arbitration circuit selects the bus with the highest priority level from the bus usage requests from the bus users and gives the bus usage right. Therefore, a bus user who wants to transfer high-priority data can preferentially transfer data using the ATM bus. Further, even when a plurality of bus users transmit a bus use request in the same priority stage, those bus users can use the bus equally.

[Fourth Embodiment] In a fourth embodiment of the present invention, an AT that allows a bus user corresponding to the bit width of an ATM bus before expansion to be connected to the ATM bus after expansion.
The M bus system will be described. Hereinafter, a fourth embodiment will be described with reference to the drawings. FIG. 10 is a block diagram showing the configuration of the ATM bus system according to the embodiment. In this figure, parts corresponding to the respective parts in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. However, illustration of the central control unit 1 and the control bus 8 is omitted.

The ATM bus system shown in this figure has two ATM buses which are the same as the ATM bus before expansion in parallel, and are called a main bus 11A and a sub bus 11B, respectively. Here, the main bus 11A is an ATM bus used first by each bus user during data transfer, and the sub-bus 11B is an ATM bus used when data transfer on the main bus 11A is congested. The main bus 11A and the sub-bus 11B each have the same bit width as the above-described ATM bus before expansion. Then, bus users 10c and 10d corresponding to the ATM bus before expansion.
The bus controllers 15c and 15d of the main bus 11
Connected to A only.

A bus user 10e is provided in place of the bus user 10a, and includes two bus controllers 15eA and 15eB having the same functions as the bus controllers 15c and 15d in the bus users 10c and 10d. One bus controller 15eA is connected to the main bus 11A, and the other bus controller 15eB is connected to the sub-bus 11B. Reference numeral 24e denotes a bus use state detection circuit, which is a bus controller 15e.
A according to the use state information 25e from the main bus 11A
Monitor the usage status of.

Further, reference numeral 26e denotes a used bus selection circuit, which uses the bus congestion information 27e, which is transferred when the bus use state detection circuit 24e detects congestion of the main bus 11A based on the use state information 25e, to minimize the bus used. Switch for each data transfer unit. This switching is performed by a bus controller control signal 28 for selecting a bus to be used.
e from the used bus selection circuit 26e to the bus controller 1
This is performed by outputting to 5eA and 15eB.

A bus user 10f is provided in place of the bus user 10b, and has the same configuration as the bus user 10e. The bus controller 15fA of the bus user 10f is connected to the main bus 11A, and the bus controller 15fB is connected to the sub-bus 11B.

Reference numeral 12a denotes a bus arbitration circuit which arbitrates the use permission of both the main bus 11A and the sub bus 11B and synchronizes both bus cycles. In this bus arbitration circuit 12a, 17A and 17B are master controllers, each having the same function as the master controller provided in the bus arbitration circuit 12 before expansion.
It controls each bus controller connected to the main bus 11A and the sub-bus 11B. Reference numeral 29 denotes a synchronization control unit which synchronizes the bus cycles of the main bus 11A and the sub-bus 11B with a synchronization signal 30.

Here, bus users 10c and 10d
Is connected only to the main bus 11A, and performs exactly the same operation as before the bus expansion using the main bus 11A. The bus users 10e and 10f are connected to both the main bus 11A and the sub-bus 11B, but do not use both buses at the same time for one data unit transfer. Use Then, the sub bus 11B is used only when the bus use state detection circuits 24e and 24f determine that the main bus 11A is congested. Information transfer between these bus users is performed based on a bus use request phase, a bus use permission phase, and a data transmission / reception phase, as in the first embodiment.

Hereinafter, the operation of the ATM bus system having the above configuration will be described. First, regarding data transfer between the bus users 10e and 10f corresponding to the expansion of the ATM bus,
This will be described with reference to FIG. Here, a case where data is transferred from the bus user 10e to the bus user 10f is shown. First, the bus user 10e performs data transfer 31A to the bus user 10f using the main bus 11A, and thereafter, when another bus user uses the main bus 11A, the bus use state detection circuit 2 of the bus user 10e.
4e is a main bus 11A based on the use state information 25e.
Is congested, and notifies the used bus selection circuit 26e of the bus congestion information 27e.

Next, the used bus selecting circuit 26e receives the bus congestion information 27e and receives the bus controller control signal 2e.
8e instructs the bus controller 15eA connected to the main bus 11A to stop data transfer, and instructs the bus controller 15eB connected to the sub-bus 11B to transfer data. As a result, the data transfer 31A by the main bus 11A is
The mode is switched to the data transfer 31B by B. At this time, the bus user 10f has received the data from the main bus 11A, but now receives the data from the sub-bus 11B by the transfer bus switching of the bus user 10e. In this case, the bus user 10f is on the main bus 11A and the sub-bus 1
Although the data on 1B can be received at the same time, the data to be received is identified and processed according to the address described in the user address information.

Thereafter, another bus user enters the main bus 11
When the use of A is stopped and the bus 11A becomes unused,
The bus use state detection circuit 24e determines that the congestion of the main bus 11A has been resolved. Thus, the used bus selection circuit 26e instructs the bus controller 15eB to stop the data transfer and instructs the bus controller 15eA to transfer the data by the bus controller control signal 28e. Therefore, the data transfer 31 on the sub-bus 11B is performed.
B switches to data transfer 31A on main bus 11A, and bus user 10f receives data from main bus 11A.

FIG. 12 is a diagram showing an example of a change in the bus use state of the main bus 11A and the sub-bus 11B in time series. In this example, if the bus 11A is congested while the bus user 10e is transferring data to the bus user 10f using the main bus 11A, the sub-bus 11B is used, and then the congestion of the main bus 11A is resolved. The state where the bus 11A is used again is shown. In this figure, one frame indicates one bus cycle,
The box 32a marked "Use 10e" is the bus user 10e.
Indicates a bus cycle used for data transfer. A frame 32b shows a bus cycle used by another bus user for data transfer, and a frame 32c shows an unused bus cycle.

Next, the bus user 1 corresponding to before the bus expansion
Data transfer between the bus user 0e and the bus user 10e corresponding to the bus expansion will be described with reference to FIG. Here, a case where data is transferred from the bus user 10e to the bus user 10c is shown. First, it is assumed that the bus user 10e performs data transfer 33A to the bus user 10c using the main bus 11A, and thereafter, the main bus 11A is used by another bus user. However, at this time, the bus user 10e determines that the bus 11A is crowded,
The switching operation from the upper data transfer 33A to the data transfer on the sub-bus 11B is not performed.

That is, if the bus user 10c
Since data cannot be received from 1B, the bus user 10e does not transfer data when the main bus 11A is congested. In this case, for example, the addresses of the bus users 10c and 10d corresponding to the addresses before the expansion are recorded in advance via the control bus 8 (not shown) so that the bus user 10e can use the sub bus 1 when the main bus 11A is congested.
The switching operation to 1B can be prevented from being performed.

Thereafter, when the main bus 11A enters the unused state, the bus use state detecting circuit 24e determines that the congestion of the bus 11A has been resolved, and restarts the data transfer 33A to the bus user 10c using the bus 11A. I do. FIG.
Are the main bus 11A and the sub-bus 11B in this case.
FIG. 7 is a diagram showing an example of a change in the bus use state in time series. Note that the frames 32a, 32b, 32c in FIG.
Are the same as each bus cycle in FIG. In the figure, when the bus user 10e transfers data to the bus user 10c using the main bus 11A, the data transfer is stopped when the bus 11A is congested, and the data transfer is restarted when the congestion is resolved. Is represented.

Finally, data transfer between the bus users 10c and 10d before the bus expansion will be described with reference to FIG. This figure shows a case where data transfer 34A is performed from the bus user 10c to the bus user 10d. In this case, since the bus users 10c and 10d are both connected to only the main bus 11A, the data transfer is performed only through the bus 11A.
That is, the transfer is performed in exactly the same manner as the data transfer before the bus expansion.

As described above, in the fourth embodiment, as shown in FIG. 10, the ATM bus having the same bit width as
They are installed in parallel. Then, the corresponding bus user can be connected to the main bus before the expansion, and the bus user uses only the main bus. Also,
A bus user connected to both buses and supporting the bus expansion uses the main bus when transferring data to the corresponding bus user before the bus expansion, and transfers the data to the bus user corresponding to the bus expansion. In this case, first, the main bus is used, and the sub bus is used only when the main bus is congested.

The congestion of the main bus can be determined, for example, by monitoring bus use request information (see FIG. 2) on the bus. Furthermore, the transmitting bus user who supports the bus expansion does not use two buses simultaneously in the same bus cycle in order to maintain the order of data arrival in the receiving bus user. In addition, the receiving bus user can simultaneously receive data from different bus users in the same bus cycle. The bus arbitration circuit according to the present invention uses the synchronization control unit in the bus arbitration circuit so that each time the bus user switches the bus to be used, it is not necessary to adjust the timing in the bus user to the bus cycle of the switched bus. To completely synchronize the bus cycles.

According to the configuration described above, the AT before the extension
By expanding the bus by installing two M buses in parallel, the information transfer capacity of the ATM bus is doubled. At the same time, since each of the main bus and the sub-bus after the bus expansion has the same bit width as the ATM bus before the expansion, a bus user corresponding to the bus expansion and a bus user corresponding to the bus expansion can be used together. . Further, by connecting the corresponding bus user to the main bus before the bus expansion, it is possible to obtain the effect that the bus user can transfer information as before the bus expansion.

Although the first to fourth embodiments of the present invention have been described in detail with reference to the drawings, the specific configuration is not limited to these embodiments and does not depart from the gist of the present invention. Even if the design of the range is changed, it is included in the present invention.

[0077]

As described above, according to the first aspect of the present invention, an extended head is provided for each cell, and bus arbitration is performed when each bus user sharing the bus sends a bus use request at the same time. Means arbitrating bus use requests of a plurality of bus users using the information in the extension header, determining a unique bus user, and performing the bus user in the same cell time as the information transfer; Since only the designated bus users receive the ATM bus data, each bus user can send data from any bus user on an equal basis and any bus user can receive data. The effect is that data can be freely transferred between the bus users. Also, if the information transfer on the bus is A
The adoption of the ATM bus, which is performed based on the TM transfer mode, makes it extremely compatible with the ATM communication network.
In addition, the minimum data unit can be a fixed-length cell unit. As a result, it is possible to simultaneously perform information transfer of a plurality of cells while securing different bands without permitting continuous transfer of a specific large amount of data, and it is possible to obtain an effect that it is easy to secure real-time properties. .

According to the second aspect of the present invention, control information for each bus user is transferred from the central control means to the control bus, and real-time media information, for example, is transferred to the ATM bus. The control information and the real-time media information can be separated, and the mutual influence between the two information can be avoided. As a result, it is possible to flexibly cope with an increase in the amount of information and information types due to the use of multimedia in computer devices, secure real-time properties, and flexibly respond to changes in the size and pattern of data to be processed. realizable.

According to the third aspect of the present invention, an address unique to the bus user that is the source of the information is preset for all the bus users that are the source of the information via the control bus. However, the bus user that is the source of the information is
After assigning the bus user-specific address to the extension header in cell units, the transmission unit in the bus user sends out the cell units onto the ATM bus. Then, all the bus users that are the information receiving sources are individually and in parallel with each other via the control bus, the source user address set in advance and the address assigned to each cell on the ATM bus. A comparison is performed, and when the addresses match based on the comparison result, the broadcast is performed by receiving the cell unit. Therefore, one source bus user among a plurality of bus users connected by the ATM bus is used. Can perform broadcast communication to a plurality of receiving source bus users in a short time. Further, it is possible to simplify the processing in both the transmission source and the reception source bus users.

According to the invention described in claim 4, the bus arbitration means permits the bus user who has transmitted the bus use request information to which the higher priority stage is added, to use the bus. At this time, if a bus use request to which the same priority step is added has been transmitted from another bus user,
Since the bus user and the other bus users are given permission to use the bus in order, the bus user who wishes to transfer high-priority data among the bus users preferentially uses the bus to transfer data. In addition to being able to transfer, even when a plurality of bus users transmit a higher priority bus use request of the same priority level, the bus user is
Buses can be used equally.

Further, according to the fifth aspect of the present invention,
Since the bus is expanded by installing two ATM buses before expansion and the same bus as the ATM bus in parallel, the information transfer capacity of the ATM bus is doubled, and the main bus and sub-bus after expansion of the bus are expanded. Have the same bit width as the ATM bus before the expansion, it is possible to use both the bus user corresponding to the bus expansion and the bus user corresponding to the bus expansion. Further, by connecting the corresponding bus user to the main bus before the bus expansion, it is possible to obtain the effect that the bus user can transfer information as before the bus expansion.

[Brief description of the drawings]

FIG. 1 shows an AT according to first and second embodiments of the present invention.
FIG. 2 is a block diagram illustrating a configuration of an M bus system.

FIG. 2 is an explanatory diagram for explaining an example of a data configuration in a unit of one cell on an ATM bus in an ATM bus system according to first, second, and fourth embodiments of the present invention.

FIG. 3 is an explanatory diagram for explaining an operation concept of the ATM bus system according to the first embodiment of the present invention.

FIG. 4 is an explanatory diagram illustrating an operation concept of broadcast communication in an ATM bus system according to a second embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of an ATM bus system according to a third embodiment of the present invention.

FIG. 6 shows a bus user 1 in the ATM bus system.
FIG. 9 is an explanatory diagram for describing an example of a change in an ATM bus use state due to 0a and 10b.

FIG. 7 shows a bus user 1 in the ATM bus system.
FIG. 11 is a diagram showing an example of a change in the ATM bus use state due to only 0b in chronological order.

FIG. 8 shows a bus user 1 in the ATM bus system.
FIG. 9 is an explanatory diagram for describing an example of a change in an ATM bus use state due to 0c and 10d.

FIG. 9 is an explanatory diagram for explaining an example of a data structure of one cell unit on an ATM bus in the same ATM bus system according to a third embodiment of the present invention.

FIG. 10 is a block diagram showing a configuration of an ATM bus system according to a fourth embodiment of the present invention.

FIG. 11 is an explanatory diagram for explaining an operation of data transfer between bus users corresponding to an extended ATM bus system.

FIG. 12 is an explanatory diagram illustrating an example of a change in a bus use state of a main bus and a sub bus in the same data transfer.

FIG. 13 is an explanatory diagram for explaining an operation in a case where data is transferred from a bus user corresponding to an extended bus user to a bus user corresponding to a pre-extended bus user in the ATM bus system;

FIG. 14 is an explanatory diagram for describing an example of a change in a bus use state of a main bus and a sub bus in the same data transfer.

FIG. 15 is an explanatory diagram for explaining an operation of data transfer between bus users corresponding to before expansion in the same ATM bus system.

FIG. 16 is a block diagram showing a basic configuration of a conventional information transfer system.

[Explanation of symbols]

10a, 10b, 10c, 10d, 10e, 10f ...
Bus user, 11 ATM bus, 11A main bus, 11B sub bus, 12 bus arbitration circuit, 14
a, 14b, 14c, 14d ... data transfer control circuit,
15a, 15b, 15c, 15d, 15eA, 15e
B, 15fA, 15fB ... bus controller, 17 ...
... master controller, 18a, 18b, 18c, ...
18n: arbitration circuit, 19: bus use permission transmission circuit,
24e, 24f... Bus use state monitoring circuit, 26e, 2
6f... Used bus selection circuit, 29... Synchronization control unit.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Mitsugu Anai 3-19-2 Nishishinjuku, Shinjuku-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Ryoichi Himeno 3-19 Nishishinjuku, Shinjuku-ku, Tokyo No. 2 within Nippon Telegraph and Telephone Corporation (72) Inventor Keito Igarashi 3-2-1, Nishi-Shinjuku, Shinjuku-ku, Tokyo Nippon Telegraph and Telephone Corporation (56) References JP-A-54-126435 (JP, A) JP-A-59-188720 (JP, A) JP-A-4-44152 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 12/28

Claims (5)

(57) [Claims] 1. An ATM bus system for transferring information in an ATM transfer mode based on fixed-length cell units on a bus serving as an information transfer path, wherein the ATM bus system performs the information transfer. When a plurality of use requests occur, the AT performs only one cell-unit information transfer at a time.
In the M bus system, a plurality of bus users connected to the ATM bus and performing the information transfer by sharing the bus, and a single bus use request among a plurality of bus use requests simultaneously transmitted by the bus user are transmitted. An ATM bus system comprising: a bus arbitration means for selecting a bus user who has made a bus use request, wherein the cell unit includes an extension header in addition to ATM bus data including an ATM header. The extension header comprises: bus use request information for the bus user to make the bus use request to the bus arbitration means; and bus use permission information indicating the only bus user determined by the bus arbitration means. And user address information for designating a transmission or reception bus user, wherein the bus arbitration unit is notified by the bus use request information. Arbitrating the plurality of bus use requests, and using the bus use permission information to notify the bus use permission given to only one bus user to all the bus users. By determining the information, only the bus user who has received the bus use permission performs the information transfer in the cell unit within the same cell time as the transfer of the extension header, and further determines the user address information and An ATM bus system characterized in that a bus user who has determined that the address is an ATM bus data receives the ATM bus data. 2. A central control means for controlling processing and information transfer performed by each bus user, and control for transferring control information for controlling each bus user from the central control means to each bus user. The ATM bus system according to claim 1, further comprising a bus. 3. An address specific to a bus user, which is a source of the information, is set in advance for all the bus users, which are sources of the information, via the control bus. The user assigns an address unique to his / her bus user to the extension header of the cell unit, and then transmits the cell unit to the ATM from a transmission circuit in the bus user.
All bus users transmitting on the bus and receiving information are individually and in parallel with a user address of a transmission source set in advance via the control bus and a cell unit on the ATM bus. 3. The ATM bus system according to claim 2, wherein a comparison is made with the address assigned to the ATM bus, and when the addresses match based on the comparison result, the broadcast is performed by receiving the cell unit. 4. A plurality of priority stages indicating priority of the information transfer are provided, wherein the bus user selects one priority stage from the plurality of priority stages and adds the selected priority stage to the bus use request information; The bus arbitration means in the bus arbitration means, when there is no bus use request in a higher priority stage than the certain priority stage, ignores the bus use request in a lower priority stage than the certain priority stage and ignores the bus use request in the lower priority stage. 4. A multi-stage priority bus arbitration for granting a bus use permission so that a bus can be used sequentially and equally in response to a bus use request at the same priority stage as the certain priority stage. The ATM bus system according to claim 1 or 2. 5. The ATM bus includes a main bus and a sub-bus in which two identical buses are installed in parallel, and the bus arbitration unit performs the bus transfer in one data transfer on the main bus and the sub-bus. An ATM bus system comprising two master controllers for separately arbitrating the bus use requests from a user and a synchronization control unit for synchronizing bus cycles of the main bus and the sub bus, wherein the bus user comprises: A bus user is connected to the main bus and provided so as to share the main bus and the sub-bus. The bus user is connected to the main bus and the sub-bus, respectively, and when there is data to be transferred, the bus user Each bus use request is issued, and the bus A bus controller for performing data transfer when permission is obtained, a bus use state detecting means for detecting a use state of the ATM bus, and a single data unit transfer in accordance with the bus congestion information by the bus use state detection means. Use bus selection means for switching between bus use and sub bus use, wherein the bus user uses the main bus first for one data unit transfer, The ATM bus system according to any one of claims 1 to 4, wherein the sub-bus is used only when it is detected by the state detecting means that the main bus is congested.