JP3123941B2 - Baseband signal processing circuit for quadrature signal demodulation - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a quadrature signal demodulation baseband signal processing circuit, and more particularly to a quadrature signal demodulation function having a demodulation frequency correction function for stabilizing a reception state of a quadrature modulation signal used for mobile radio or the like. The present invention relates to a baseband signal processing circuit.

[0002]

2. Description of the Related Art A receiving circuit for receiving and demodulating a quadrature modulated signal of this type by a method such as synchronous detection or the like requires a demodulation frequency on the receiving side in order to stabilize the reception state of the quadrature modulated signal and perform high-precision demodulation. It requires frequency correction to match the modulation frequency on the transmitting side with high accuracy.

Conventionally, this frequency correction is performed, for example, in Japanese Unexamined Patent Application Publication No.
As in the conventional quadrature signal demodulation circuit described in 216957 (Document 1), this has been performed by changing the oscillation frequency of the local oscillation circuit. For this reason, the control circuit of the voltage controlled oscillator (VCO) for the local oscillation circuit requires a VCO peripheral circuit such as a digital / analog converter (DAC) dedicated to frequency correction.

In recent years, in portable radio terminals such as mobile radios, which have become highly functional and compact and lightweight, power consumption is reduced in order to extend the charging interval of a small battery as a power source as much as possible from the viewpoint of operability improvement. This is a necessary condition. In particular, companies are competing for techniques to extend the reception time during standby reception.
Therefore, it is necessary to reduce power consumption during standby reception as much as possible. An effective means for reducing power consumption is elimination of circuits, particularly elimination of analog circuits.

[0005] A general mobile terminal employs a heterodyne detection system as a reception system, and uses an RF frequency of IF
Two PLL circuits are provided, a first PLL circuit for down-conversion to a frequency and a second PLL circuit for down-conversion of the IF frequency to a baseband frequency.

[0006] Each of these two PLL circuits is an independent VCO, that is, the first PLL circuit is an RF VC.
O The second PLL circuit includes an IF VCO. further,
When the above-described frequency correction is required, the first PL
A circuit for fine adjustment of a reference oscillation circuit that generates a reference frequency of the PLL is required independently of the L circuit and the second PLL circuit. The reference oscillation circuit generally uses a temperature-compensated voltage controlled crystal oscillation circuit (VCTCXO), and a large-scale analog circuit such as a DAC is used as a circuit for fine adjustment. Therefore, there is a problem that the number of analog circuits increases and power consumption increases.

If frequency correction is performed by digital processing in order to eliminate power consumption, a large-scale analog circuit such as the above-mentioned DAC becomes unnecessary.

The basic principle is as follows. In order to perform the digital signal processing, the baseband signal down-converted to the baseband frequency is subjected to quadrature detection using the characteristics of the quadrature modulation signal, and the following calculation is performed.

I = I′cos θ−Q′sin θ (1a) Q = I′sin θ + Q′cos θ (1b) where I ′ and Q ′ are detection signals of the received quadrature modulation signal, c
osθ and sinθ represent a corrected frequency signal, and I and Q represent quadrature modulated signals after frequency correction.

[0010] Generally, quadrature detection is simultaneously performed at the time of down-conversion from IF to baseband by using an LSI equipped with an IF signal processing circuit (LSI for IF).

The detection signals I ′ and Q ′ are sin2π
f and cos2πf. Now the correction frequency is fc
Then, the equations (1a) and (1b) can be rewritten as the following equations.

I = sin2πfcos2πfc−cos2πfsin2πfc · (2a) Q = sin2πfsin2πfc + cos2πfcos2πfc · (2b) From the trigonometric function addition and embedding, the equations (2a) and (2b) are converted as the following equations, and the detected frequency of fc is changed by the following equation. Occurs.

I = sin2π (f−fc) (3a) Q = cos2π (f−fc) (3b) By utilizing this fact and performing frequency correction in a digitized baseband signal processing circuit, the peripheral circuit of the second VCO, which has been conventionally required, can be eliminated.

Referring to FIG. 6, which shows a block diagram of a conventional orthogonal signal demodulation baseband signal processing circuit, the conventional orthogonal signal demodulation baseband signal processing circuit shown in FIG.
Each of the I and Q analog input signals I and Q is converted to a digital I,
1-bit ΔΣ type analog-to-digital converters (ADCs) 1 and 2 for converting into Q signals ID and QD;
First thinning filters 3 and 4 for thinning Q signals ID and QD and outputting first thinning signals IM and QM, a second thinning filter 5 for thinning first thinning signals IM and QM and outputting digital output signals IS and QS, Is provided.

Referring to FIG. 7 which shows the configuration of the second thinning filter 5 by blocks, this second thinning filter 5
36-word data RAMs 51 and 52 and coefficient ROM 5
3, an addition circuit 54, a multiplication circuit 55, and an addition circuit 56
And latch circuits L52 and L5 for temporarily holding output signals of data RAM 51 and coefficient ROM 53, respectively.
3, L55, a latch circuit L54 that temporarily holds the output signal of the adding circuit 54, a latch circuit L56 that temporarily holds the output signal of the multiplying circuit 55, and a latch circuit L57 that temporarily holds the output signal of the adding circuit 56. Prepare.

This conventional quadrature signal demodulation baseband signal processing circuit is constructed using a well-known oversampling ADC as shown in the figure. As an example, the first decimation filter uses a 16-tap, three-stage comb filter, and reduces the digital I, Q signal ID, QD to 1/16.
To generate first decimated signals IM and QM. The second decimation filter uses a linear phase 48-tap FIR filter, decimates the first decimation signals IM and QM by に, and generates decimation digital output signals IS and QS. Therefore, in this example, the ADC is a 48-times oversampling type ADC. With this configuration, (3a), (3b)
What is necessary is just to realize the operation of the expression.

There are two issues to consider here. The first problem is that a frequency correction requires a multiplication circuit as is apparent from the equations (1a) and (1b). Therefore, the circuit scale of the digital circuit increases.

A second problem is that an ADC usually has an offset, and the oversampling type also has an offset. As is clear from the equations (1a), (1b) to (3a), and (3b), when an offset occurs, the offset signal is also frequency-corrected and appears as noise.

[0019]

In the above-described conventional baseband signal processing circuit for quadrature signal demodulation, the baseband signal processing circuit is configured using an oversampling type ADC. Has a disadvantage that a multiplication circuit having a large circuit scale is required and the overall circuit scale is increased.

Further, when an offset inherently existing in the ADC occurs, the offset signal is also frequency-corrected and appears as noise.

An object of the present invention is to provide a quadrature signal demodulation baseband signal processing circuit capable of reducing a circuit scale by eliminating a large-scale analog circuit and realizing a mobile radio terminal with low power consumption. It is in.

[0022]

A baseband signal processing circuit for demodulating a quadrature signal according to the present invention receives a quadrature modulated signal comprising an in-phase signal and a quadrature signal orthogonal to the in-phase signal, and down-converts an intermediate frequency signal. An analog-to-digital conversion circuit that receives supply of a baseband signal generated by conversion, samples the in-phase signal and the quadrature signal of the baseband signal at a predetermined frequency, and then performs analog-to-digital conversion; varying of the quadrature modulated signal it receives the signal to quadrature detection signals of the quadrature detection Sico
Before by performing frequency correction for matching the frequency of the No. recovery Choshin obtained by demodulating the quadrature modulated signal and tone frequency
A quadrature signal demodulation baseband signal processing circuit that demodulates the quadrature modulation signal by a synchronous detection method, comprising a quadrature detection calculation circuit that performs quadrature detection of the baseband signal and performs the following equation to perform the frequency correction. A quadrature detection operation circuit for converting the in-phase signal and the quadrature signal into a digital in-phase signal and a digital quadrature signal at a first sampling period, respectively And decimating each of the digital in-phase signal and the digital quadrature signal at a second sampling period longer than the first sampling period.
1st and 2nd, which output a thinned in-phase signal and a first thinned quadrature signal
A second first decimation filter, a sine / cosine generation circuit receiving a supply of the correction value for frequency correction and generating a frequency correction signal, and the first decimation in-phase signal in response to the supply of the frequency correction signal , A predetermined frequency correction operation is performed on each of the first decimated quadrature signals to generate a corrected first decimated in-phase signal and a corrected first decimated quadrature signal. A second decimating filter for outputting each of a decimated digital in-phase output signal and a digital quadrature output signal at a third sampling period longer than the second sampling period is provided. I = I′cos θ−Q′sin θ Q = I′sin θ + Q′cos θ where I ′ and Q ′ are detection signals of the received quadrature modulation signal, c
os θ and sin θ are correction frequency signals, I and Q are quadrature modulated signals after frequency correction, and θ = 2πfc and fc are correction frequencies.

I = I′cos θ−Q′sin θ Q = I′sin θ + Q′cos θ where I ′ and Q ′ are detection signals of the received quadrature modulation signal, c
os θ and sin θ are correction frequency signals, I and Q are quadrature modulated signals after frequency correction, and θ = 2πfc and fc are correction frequencies.

[0024]

FIG. 1 is a block diagram showing a first embodiment of the present invention, in which constituent elements common to FIG. 6 are denoted by blocks using common characters / numerals. The quadrature signal demodulation baseband signal processing circuit of the present embodiment includes:
In addition to the 1-bit ΔΣ type analog-to-digital converters (ADCs) 1 and 2 and the first thinning-out filters 3 and 4 which are common to the conventional ones, the offset values IO and QO of the digital I and Q signals ID and QD are set. Rounding signal IR, QR respectively
ΔΣ-type rounding circuits 6 and 7 for generating the frequency correction value F
C supplied, frequency correction operation, ie, sin / cos
A sine / cosine generating circuit 8 for generating a signal FS and a predetermined offset correction in response to supply of rounding signals IR and QR in place of the second thinning filter 5 and sin
A second thinning filter 5A that performs a predetermined frequency correction in response to the supply of the / cos signal FS.

The circuit of the present embodiment is configured using an oversampling type ADC as in the prior art, and the first thinning filters 3 and 4 use a 16-tap, three-stage comb filter, and provide digital I and Q signal IDs. , QD are thinned to 1/16 to generate first thinned signals IM, QM. The second decimation filter 5A uses a 36-tap linear phase FIR filter to decimate the first decimation signals IM and QM to １ ／ to generate decimation digital output signals IS and QS. Therefore, a 48-fold oversampling ADC
Becomes

In the present embodiment, the correction operation of the equations (1a) and (1b) is performed on the input side of the second decimation filter 5A with respect to the first decimation signals IM and QM output from the first decimation filters 3 and 4. Do.

Referring to FIG. 2 in which the configuration of the second thinning filter 5A is shown by blocks using common characters / numerals for components common to those in FIG.
36-word data RAMs 51 and 52 which are common with the prior art;
A coefficient ROM 53, an addition circuit 54, a multiplication circuit 55,
In addition to the adder circuit 56 and the latch circuits L52 to L57, the first decimating signals IM and Q having a total of 6 words of 3 words each of I and Q.
A latch circuit L51 for temporarily holding M.
1 and an output of the latch L51, and a selection circuit S51 for selecting one of the output of the data RAM 52 and the round signal IR / QR.
52, the output of the coefficient ROM 53 and the sin / cos signal F
And a selection circuit S53 for selecting one of the two.

Next, the operation of the present embodiment will be described with reference to FIGS. 1 and 2. This embodiment has two problems of the necessity of the multiplication circuit in the above-described frequency correction operation and the offset of the ADC. To realize frequency correction by digital signal processing.

First, considering the first problem, (1)
Since the expressions a) and (1b) require multiplication, a multiplication circuit is naturally required. In a conventional baseband signal processing circuit comprising a first thinning filter and a second thinning filter, providing a new multiplier circuit has a very large impact on the circuit and is disadvantageous in power consumption. For this reason, it is desired to realize this without providing a new multiplication circuit. Therefore, it is considered to perform the required operation by sharing the multiplication circuit 55 of the conventional second thinning filter 5.

When the multiplication circuit 55 is used for multiplication for frequency correction, there are two ways of realization in consideration of the data flow, that is, a method of performing frequency correction on the output of the first decimation filter, and a method of performing the second decimation. It can be considered that the method is performed for the output of the filter.

When frequency correction is performed on the output of the first thinning filter, a large number of frequency correction calculations are required because the sampling rate is faster than the sampling rate of the second thinning filter. Therefore, considering the amount of calculation, it is more advantageous to use the output of the second thinning filter. However, when frequency correction is performed using the output of the second thinning filter, there is a problem that the correction result is affected by the filter characteristics of the second thinning filter. That is, in the oversampling type ADC, the first thinning filter uses a comb-shaped filter whose characteristics gradually change from a pass band to a stop band, and the second thinning filter is a low-pass filter having a steep transition region characteristic. Used. For this reason the second
When the above-described correction is performed on the output of the thinning filter, the frequency of the stop band is corrected in the transition region, and the signal is passed as a pass band signal. Conversely, the signal in the pass band is corrected to be a signal in the stop band. For this reason, the characteristics of the second thinning filter greatly change due to the frequency correction. This is a big problem.

Although the amount of calculation is large, if the output of the first thinning filter is subjected to frequency correction, the problem caused by the output of the second thinning filter can be reduced. Further, although the amount of calculation is further increased, it can be easily imagined that the above problem does not occur at all if the first thinning filter is input.

Up to now, it has been considered to use the multiplication circuit 55 of the second decimation filter. However, when the oversampling type ADC is used, the input of the first decimation filters 3 and 4 is 1 bit, so that it is particularly required. No multiplication circuit is required. Therefore, the frequency correction is inserted before or after the first thinning filter.

Considering the second problem, the problem of the ADC offset can be easily solved by using a known DC offset canceling method. For example, there is no problem if a calibration period is provided in advance to calculate a DC offset value, and the DC offset is canceled using this value. Here, it goes without saying that the DC canceling operation is performed before the frequency correction operation.

The problem with DC canceling is the accuracy of the operation. Input signal IDs of the first decimation filters 3 and 4,
QD has 1-bit resolution, and output signals IM and QM are 12 bits.
Bit resolution. Therefore, in this state, the accuracy of DC cancellation is limited by the bit resolution of each signal. Of course, there is no problem if the calculation is performed with the number of bits necessary for DC cancellation. However, all the circuits after the first thinning filters 3 and 4, that is, the data RAMs 51 and 52 for the linear phase FIR filter calculation of the thinning circuit 5A, the multiplication circuit It is necessary to extend the number of operation bits of the 55, the adder circuits 54, 56, etc., which leads to an increase in circuit scale, which is a very problematic problem.

In order to solve the problem of DC cancellation occurring at the time of frequency correction by digital technology, a DC calibration value of high bit resolution is rounded by a rounding circuit 6 using a ΔΣ modulation circuit to obtain round data IR, Q
A rounding DC canceling operation is performed on R. Similarly, by performing rounding using the sine / cosine generation circuit 8 for the frequency correction operation, the frequency correction operation at the first decimation filters 3 and 4 can be performed without significantly increasing the circuit scale.

Referring again to FIG. 2, the second line shown in FIG.
The thinning-out filter 5A is a second thinning-out filter having a DC canceling and a frequency correction function added, which is configured by a signal processing circuit that performs 48 product-sum operations in 48 steps during one sampling period.

In operation, first, frequency correction of signals IM and QM is performed in the first 12 steps of 48 steps, and thinning calculation of IM and QM is performed in the subsequent 36 steps. As described above, since the linear phase FIR filter is used as the thinning filter, the calculation using the return of the filter coefficient is performed, so that I, Q can be performed in 36 steps.
Can be calculated. Since the calculation is performed in a time-sharing manner, a buffer latch L51 for temporarily storing input data requires a total of six words for each of the three words IM and QM.

The input data signals IM and QM are first temporarily held in the buffer L51. This buffer L5
The data is read from 1 and operated as needed. First, the adder circuit 54 reads data from the buffer L51,
The rounding signal IR / supplied via the selection circuit S52
The DC offset is canceled by adding QR. At this time, the input rounding signals IR / QR are complemented by DC offset values IO and QO by ΔΣ-type rounding circuits 6 and 7 described later.
Is rounded. Next, the multiplication circuit 55 and the addition circuit 56 carry out the rounding number correction calculation processing of the equation (1), and then sequentially output the data from the second decimation filter, that is, the decimation digital output signals IS and QS.
Store in 51. At this time, the oldest data in the data RAM 51 is transferred to the data RAM 52, and the oldest data in the data RAM 52 is discarded.

Thereafter, the second thinning filter operation is started. In the second thinning filter operation, the data RAM 51 sequentially stores the latest data as data DN and data RA
M52 reads out the data DN, DP as a data DP sequentially from the oldest data, and reads them out, respectively.
4, the read data DN and DP are added to each other, the multiplication circuit multiplies the filter coefficient from the coefficient ROM 53, and the addition circuit 56 performs cumulative addition 18 times. As a result, a second thinning filter operation, which is a 36-tap FIR filter, is performed, and an output is obtained.

Referring to FIG. 3 which shows a block diagram of the configuration of rounding circuit 6, this rounding circuit 6 includes adder circuits A61 to A6.
4, a second-order ΔΣ modulation circuit including delay circuits D61 to D63, and a round-off circuit 61, and for improving the DC canceling accuracy by rounding the DC offset values IO and QO as described above. Things.

The rounding circuit 6 truncates the 4 LSBs of the 16-bit DC offset value IO by the truncation circuit 61 to generate a 12-bit round signal IR. The DC offset value IO, which is input data, is a value measured and held in advance.

The sine / cosine generation circuit 8 generates a digital sine wave and a digital cosine wave having a frequency corresponding to the frequency correction set value.

Next, referring to FIG. 4 in which the second embodiment of the present invention is shown by blocks using common characters / numerals for constituent elements common to FIG. 1, this embodiment shown in FIG. Is different from the first embodiment in that the outputs I and I of the ADCs 1 and 2 are different.
Adder circuits 11 and 12 for subtracting the rounding signals IR and QR for each of D and QD to perform offset cancellation and outputting cancellation signals IC and QC, and cancel signals IC and QC.
A frequency correction operation is performed for each of the QCs to obtain a correction signal I.
F, a frequency correction computing circuit 10 for outputting a QF to the first decimation filter, and a rounding circuit 9 outputs a correction signal FR rounding rounds the output signal FS of the sine / cosine generation circuit 8, the first decimation filter 3 , 4 before the frequency correction calculation.

Referring to FIG. 4, the operation of the present embodiment will be described focusing on the differences from the first embodiment.
Each of the adders 11 and 12 outputs the output of the ADC 1 or 2, that is, 1-bit digital data (2 in complement representation).
(Bit) ID and QD are subtracted from the rounding signals IR and QR from the rounding circuits 6 and 7 to perform offset cancellation and output cancellation signals IC and QC. The frequency correction operation circuit 10 performs a frequency correction operation for each of the cancel signals IC and QC by using the rounding correction signal FR, that is, the operation of Expression (1), outputs correction signals IF and QF, and performs first thinning. Supply to filter. At this time (1)
The multiplication of the expression can be realized by a complement operation because the multiplier is rounded to one bit.

FIG. 5 is a block diagram showing the configuration of the frequency correction operation circuit 10. Referring to FIG.
Are the cancellation signal IC and the rounding correction signal cos / si
a complementary circuit 102 receiving each supply of nFR,
103, a cancel signal QC and a rounding correction signal sin
/ ComsFR which receives the supply of each of the complement circuits 1
01, 104, an addition circuit A101 that subtracts the outputs of the complement circuits 101 and 102 and outputs a correction signal IF, and an addition circuit A102 that subtracts the outputs of the complement circuits 103 and 104 and outputs a correction signal QF. .

First, when the rounding correction signal (sin / cos) FR, which is a multiplier, is -1, complement processing is performed on the cancel signals IC, QC, which are multiplicands, and nothing is performed when +1. Output as is.

The correction signals IF and QF that have been subjected to the DC offset cancellation and frequency correction are passed through the first thinning filters 3 and 4 and the second thinning filter 5 as in the prior art, and output as output signals IS and QS.

In this embodiment, the rounding of the frequency correction signal FR is 1 bit.

As described above, the frequency correction operation circuit 1
In the case of a configuration using no multiplier circuit at 0, the frequency correction signal FR can be up to ± 2. Since ± 2 can be realized by a shift operation, even when the frequency correction signal FR is rounded to 2 bits, the frequency correction operation can be realized without using a multiplication circuit.

[0051]

As described above, the quadrature signal demodulation baseband signal processing circuit of the present invention performs quadrature detection of the baseband signal and performs the following operation to correct the frequency, that is, the second quadrature detection operation circuit, Since the thinning filter is provided, there is an effect that digital frequency correction can be realized with a relatively small circuit scale without using a multiplication circuit.

I = I'cos θ-Q'sin θ Q = I'sin θ + Q'cos θ Further, large-scale analog circuits such as a DAC for frequency correction can be reduced, and power consumption can be greatly reduced. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a baseband signal processing circuit for quadrature signal demodulation according to the present invention.

FIG. 2 is a block diagram illustrating a configuration of a second thinning filter of FIG. 1;

FIG. 3 is a block diagram illustrating a configuration of a rounding circuit in FIG. 1;

FIG. 4 is a block diagram showing a second embodiment of a quadrature signal demodulation baseband signal processing circuit according to the present invention.

FIG. 5 is a block diagram illustrating a configuration of a frequency correction operation circuit in FIG. 4;

FIG. 6 is a block diagram showing an example of a conventional orthogonal signal demodulation baseband signal processing circuit.

FIG. 7 is a block diagram showing a configuration of a second thinning circuit of FIG. 6;

[Explanation of symbols]

1, 2 ADC 3, 4 First decimation filter 5, 5A Second decimation filter 6, 7, 9 Rounding circuit 8 Sine / cosine generation circuit 10 Frequency correction operation circuit 11, 12, 54, 56, A61 to A64, A101,
A102 Addition circuit 51, 52 Data RAM 53 Coefficient ROM 55 Multiplication circuit 61 Round-down circuit 101-104 Complement circuit D61-D63 Delay circuit L51-L57 Latch S51-S53 Selection circuit

Continuation of the front page (56) References JP-A-6-334698 (JP, A) JP-A-9-83596 (JP, A) JP-A-7-327057 (JP, A) JP-A-9-83588 (JP) JP-A-8-335959 (JP, A) JP-A-4-360345 (JP, A) JP-A-9-18531 (JP, A) (58) Fields studied (Int. Cl. ⁷ , DB Name) H04L 27/00-27/38

Claims (5)

(57) [Claims] 1. A baseband signal generated by receiving a quadrature modulation signal composed of an in-phase signal and a quadrature signal orthogonal to the in-phase signal, down-converting an intermediate frequency signal, and receiving the baseband signal. An analog-to-digital conversion circuit that samples the in-phase signal and the quadrature signal at a predetermined frequency and then performs analog-to-digital conversion, quadrature-detects the baseband signal and performs quadrature detection.
Wherein the modulation frequency of the quadrature modulated signal it receives into a wave signal
The quadrature modulated signal by performing frequency correction for quadrature modulation signal is matched with the frequency of the No. recovery Choshin demodulated
A quadrature signal demodulation baseband signal processing circuit for demodulating the baseband signal by a synchronous detection method, comprising: a quadrature detection calculation circuit that performs quadrature detection of the baseband signal and performs the following equation to perform the frequency correction: Converts the in-phase signal and the quadrature signal into a digital in-phase signal and a digital quadrature signal, respectively, in a first sampling period.
A 1-bit ΔΣ-type analog-to-digital converter, and decimating each of the digital in-phase signal and the digital quadrature signal in a second sampling period longer than the first sampling period. First and second first thinning filters that output orthogonal signals, a sine / cosine generating circuit that receives a supply of the correction value for frequency correction and generates a frequency correction signal, and responds to the supply of the frequency correction signal. A predetermined frequency correction operation is performed on each of the first decimated in-phase signal and the first decimated quadrature signal to generate a corrected first decimated in-phase signal and a corrected first decimated quadrature signal. , Each of the corrected first decimated quadrature signals is decimated by a third sampling period longer than the second sampling period. A quadrature signal demodulation baseband signal processing circuit, comprising: a second decimation filter that outputs each signal. I = I′cos θ−Q′sin θ Q = I′sin θ + Q′cos θ where I ′ and Q ′ are detection signals of the received quadrature modulation signal, c
os θ and sin θ are correction frequency signals, I and Q are quadrature modulated signals after frequency correction, and θ = 2πfc and fc are correction frequencies. 2. A frequency correction signal rounding circuit of a ΔΣ type for generating a rounded frequency correction signal by truncating a predetermined number of lower-order bits of the frequency correction signal, and performing the frequency correction operation using the rounded frequency correction signal. The orthogonal signal demodulation baseband signal processing circuit according to claim 1, wherein 3. An offset canceling operation for canceling each of a DC offset value and a DC offset value of each of the digital in-phase signal and the digital quadrature signal before the frequency correction operation. The baseband signal processing circuit for orthogonal signal demodulation according to claim 1 . 4. The method according to claim 1, wherein the rounded frequency correction signal is a 1-bit or 2-bit digital signal, and the frequency correction operation is performed by performing a complement operation on each of the first decimated in-phase signal and the first decimated quadrature signal, which are multiplicands. 3. The quadrature signal demodulation baseband signal processing circuit according to claim 2, wherein the function of the multiplication circuit is performed by performing at least one operation of an operation and a reset. 5. A ΔΣ-type first and second rounding circuit for generating a rounded in-phase offset value and a rounded quadrature offset value by truncating a predetermined number of lower-order bits of each of the in-phase offset value and the quadrature offset value. 4. The quadrature signal demodulation baseband signal processing circuit according to claim 3, wherein the offset value canceling operation is performed using the in-phase offset value and the rounded quadrature offset value.