JP3120382B2 - Three-way transfer operation by computer - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to the efficient transfer of digital information in digital computers. In particular, the present invention relates to the transfer of digital information from a central processing unit to a bus (bus), from storage to a bus (bus), and from the bus (bus) to a subsystem including a graphics subsystem.

[Conventional technology]

Digital computers have traditionally utilized methods and systems for transferring digital information from storage to various subsystems of the computer, including graphics subsystems. The graphics subsystem partially controls the display of a computer workstation or terminal.

In one of the conventional structures, the graphical information was first downloaded to the main memory (ie, host memory) portion of the computer. Conventional computers have a dedicated display list processor in addition to the host processor. The display list processor then transferred the graphical information from the host memory to the display list memory. Then display
The list processor transmitted graphic information from the display list memory to the graphic subsystem by continuously scanning the display list.

One of the drawbacks of this conventional structure is not a single transfer, but a double transfer: the first transfer from the host memory to the display list memory, and the display list memory to the graphics sub. A second transfer to the system was necessary.

Another drawback of this conventional architecture was the inclusion of special hardware in addition to the host processor and host memory: the display list processor and the display list memory.

In another conventional structure, there is no dedicated display list processor and dedicated display list memory, but instead the graphical information is stored in the main (or host) memory and is used by the host processor. Transferred from storage to the graphics subsystem.

One of the drawbacks of this other conventional structure was that much of the processing time of the processor was spent transferring the graphics information from memory to the graphics subsystem. This delayed the execution of other operations by the processor.
Another drawback was that the processor could not keep up with the speed at which the graphics subsystem could receive data. In other words, the transfer was not as fast as it should have been.

[Problems to be Solved by the Invention and Means for Solving the Problems]

In view of the aforementioned limitations of known methods and systems for transferring digital information from a computer storage device to a computer subsystem, including a graphics subsystem, one of the objects of the present invention is to increase the efficiency of the computer. , Providing an efficient means of transferring data to a subsystem of a computer, including a graphics subsystem.

Another object of the present invention is to transfer the digital information to a subsystem of a computer under the control of a central processing unit (“CPU”) while minimizing the time the CPU spends transferring. Is to provide other computer operations other than the transfer for a longer period of time. Therefore, the problem of the present invention is that the transfer is performed by the CPU.
Is to avoid occupying the processing time of.

Another object of the present invention is to provide a method for transferring digital information to a subsystem of a computer that minimizes the amount of computer hardware required for the transfer.

Another object of the present invention is to provide digital information to a computer such that the rate at which the computer transmits the digital information to the subsystem is high enough to approximately match the maximum rate at which the subsystem can receive the digital information. It is to provide a method for transferring to the subsystem.

Another object of the invention is to provide a method for transferring digital information to a subsystem of a computer in which two or more data words are transferred simultaneously.

Another object of the invention is to provide a method for transferring digital information to a subsystem of a cache-compliant multiprocessor computer, the data transmission of which is also possible for data extending over more than one line of the cache. Is.

Yet another object of the present invention is to provide a method of transferring digital information to a subsystem of a computer when the interrupt occurs during the transfer so that the computer can restore the pre-interrupt state after the interrupt. Is.

These objects of the invention are accomplished by a method and apparatus for performing a three-way transfer of digital information within a digital computer. Digital computer is CPU
And a decoding circuit coupled to the CPU, a bus coupled to the decoding circuit, a memory coupled to the bus, and a subsystem coupled to the bus. The digital information includes a data block, and the data block includes (1) a start address that is the address of the first word of the data block, and (2) the number of words in the data block. It contains the word count and the word to represent. The trigger address for the write operation is transmitted from the CPU to the decode circuit. The trigger address is decoded and the subsequent write operation is prevented from modifying the memory. The start address of the write operation is the CPU
To the bus. The starting address is then transmitted from the bus to memory and to the subsystem. Data including word counts are transmitted from the CPU to the bus. Two,
Or a series of more data words is transmitted from the memory to the bus. The number of words in the series of data words is greater than or equal to the word count. One data word of the series of data words is at the starting address of the memory. A series of data words is transmitted from the bus to the subsystem. In this way, blocks of data are transferred from memory directly to the subsystem via the bus.

The foregoing objects of the invention are further achieved by a method and apparatus for performing a three-way transfer of digital information in a digital computer as follows. The digital computer includes a CPU, a decode circuit coupled to the CPU, a bus coupled to the decode circuit, a memory coupled to the bus, and a subsystem coupled to the bus. The digital information includes (1) a start address that is the address of the first word of the data block, and (2) an end address that is the address of the last word in the data block.
(3) A word count indicating the number of words in the data block is included. The trigger address for the write operation is transmitted from the CPU to the decode circuit. The trigger address is decoded and the subsequent write operation is prevented from modifying the memory. The first start address for the write operation is transmitted from the CPU to the decode circuit. The bits of the first start address are stored as tag bits. The tag bit has an order of arrangement that represents the position of the tag bit within the start address. The first start address is transmitted from the decode circuit to the bus. The first start address is transmitted from the bus to the memory and subsystem. Data including word counts are transmitted from the bus to the subsystem. The first sequence of N data words is transmitted from the memory to the bus. N is an integer greater than 1 and greater than or equal to the word count. One data word of the first sequence of N data words is first in memory
At the start address of the. The first sequence of N data words is transferred from the bus to the subsystem.
The word count is divided by N, 1 is subtracted, and if the result is fractional, the result is rounded to the next largest integer,
The integer X is generated. If X is a positive integer greater than or equal to 0, the above steps are repeated X times. Before repeating the above steps, (1) the first start address is incremented by N to generate a second start address, (2) the first start address becomes the second start address, and (3)
The tag bit is cleared, and (4) the first sequence of N data words is the next (N data number) of the sequence of consecutive (N data word) sequences. Sequence) and the operation for a series of consecutive sequences will end when the above steps are repeated X times. After completion of these steps, the end address of the write operation is transmitted from the CPU to the decode circuit. The tag bit is compared to the bit of the ending address that has the same ordering as it. If the two bits are not the same, (1) the end address is transmitted from the decoding circuit to the bus, (2) the end address is transmitted from the bus to the memory and subsystem, and (3)
Data including word count is transmitted from the CPU to the bus,
(4) Data containing the word count is transmitted from the bus to the subsystem, (5) The end sequence of N data words is transmitted from the memory to the bus (where one of the data words of the end sequence of data words is Is at the end address of memory), and (6) the end sequence of N data words is transferred from the bus to the subsystem. Data blocks are thus transferred directly from memory to the subsystem via the bus.

Other objects, features and advantages of the present invention will be made clear by the following detailed description of the present invention with reference to the accompanying drawings.

[Brief description of drawings]

The accompanying drawings illustrate the present invention and the present invention is not limited to the accompanying drawings. In the drawings, the same reference numerals indicate the same elements.

FIG. 1 is a block diagram of a system of a digital computer including two CPUs, a decoding circuit, a bus, a memory, and a graphics subsystem.

FIG. 2 is a diagram of a data block with various word counts.

FIG. 3 is a timing diagram of three-way transfer of digital information.

[Detailed Description of the Invention]

Referring to the drawings, FIG. 1 is a block diagram of a circuit 10 which constitutes the architecture of a cache-compliant multiprocessor digital computer with enhanced graphics capabilities. Viewed from the left side of FIG. 1, CPU 20 is a microprocessor of a 32-bit R3000 RISC (Instruction Set Simplification) computer commercially available from MIP Computer, Inc. of Sunny Bell, Calif. Each data word consists of 32 bits. Instruction cache 22
Is coupled to CPU 20 and data cache 24 is also CPU
Combined with 20. The instruction cache 22 and the data cache 24 function as a small high speed memory arranged between the processor 20 and the main memory 80. The instruction cache 22 and the data cache 24 are each directly mapped. The fact that the cache 22 and the cache 24 are of the direct mapping type means that the CPU 20 can recognize where in the main storage device 80 the data enters the caches 22 and 24. With such a dual cache method, it is guaranteed that the instruction and the data do not compete in the same cache area even if the direct mapping method is used. The separate instruction and data caches increase instruction bandwidth. The circuit 10 further comprises a second direct mapped data cache 40 coupled between the write buffer 30 and the bus 70. Graphical subroutines are in instruction cache 22 and data cache 24 of CPU 20 and in instruction cache 102 and data cache 104 of CPU 100.

In the preferred embodiment of the present invention, three-way transfer of digital information within circuit 10 is performed. In the three-way transfer operation,
The start address is from the CPU 20 via the bus 70 to the storage device 80
Be transmitted to. The start address is also transmitted from the CPU 20 via the bus 70 to the graphics subsystem 90. Then, a data block (a data block having a starting address which is the address of the first word and a word count representing the number of words in the data block) is transferred from storage device 80 or data cache 40 via bus 70 to a graphic To subsystem 90,
It is transmitted directly. The graphics subsystem 90 utilizes the data blocks so transmitted.

The data cache 24 is a write-through cache. In the case of a write-through cache such as the data cache 24, the CPU 20 always writes to both the data cache (ie the data cache 24) and the main memory 80. Since data cache 24 is write-through, main memory 90 always has an up-to-date copy of all the data in data cache 24. In a write-through cache architecture, the CPU always seems to miss the cache and writes to both the cache (ie cache 24) and storage 80. The tag (sign) to the cache 40 is also updated.

However, the second level data cache 40 is a writeback cache. In a write-back cache scheme, cache 40 may have a newer version of the data word than the data word at the same address location in storage 80. In the write-back cache method, the CPU 20 writes only to the cache 40 and does not write to both the cache 40 and the storage device 80 at the same time. In other words, in the write-back cache scheme, cache 40 may have a proprietary copy of the most recent modified data word. CPU20 is
When writing to the same storage area twice, it is sufficient to write to the storage device 80 only once. Therefore, the write-back cache method minimizes the bus traffic.

The write buffer 30 is a write buffer having a depth of 4 steps. That is, the write buffer 30 can hold four words of digital information in each memory location. The write buffer 30 is also first-in first-out (“FIFO”)
It is a write buffer. The write buffer 30 is coupled to the second level data cache 40 via line 82. Write buffer 30 is further coupled to address decoder 50 via line 34.

Write buffer 30 is coupled to CPU 20 and data cache 24 via line 26. The write buffer 30 eliminates the need for the write-through cache 24 to wait for the slow main memory 80 to complete a write cycle. CPU20 (data of the second level
The digital information desired to be written (in the cache 40 or the storage device 80) is dumped in the write buffer 30. Then
The write buffer 30 writes to the second level data cache 40 and main memory 80 at a relatively slow rate, during which the CPU 20 can perform other computer operations. In a preferred embodiment of the invention,
The CPU 20 is a 25 MHz microprocessor that transfers digital information relatively quickly. Thus, write buffer 30 holds digital information from CPU 20 so that CPU 20 can move to another computer operation.

CPU 20 performs a read or write operation. In a read operation (ie a load operation), the CPU 20 can get instructions, addresses and data from the caches 22, 24 and 40 or the storage device 80. If a cache miss occurs during a read operation of the CPU 20, the CPU 20 will go to the storage device 80 instead of the cache 22, 24 or 40 to get the instruction, address, and data. CPU 20 must wait for data during a read operation. on the other hand,
During a write operation (ie, a store operation), CPU 20 caches addresses and data 24 and 40, or storage devices.
Transmit to 80. Cache 24 during CPU20 write operation
Or, “miss” 40, cache 22 forwards the address and data to both caches 24 and 40.

CPU 20 transmits and receives addresses and data on line 26. Write buffer 30 transmits and receives addresses and data on line 32. The second level data cache 40 transmits and receives addresses and data on line 44.

Referring to the right side of FIG. 1, CPU 100 is a 32-bit R3000 microprocessor also commercially available from MIP Computer, Inc. of Sunnybell, Calif.
The circuit on the right side of FIG. 1 is similar to the circuit on the left side of FIG. The instruction quiche 102 is coupled to the CPU 100. data·
The cache 104 is also coupled to the CPU 100. Both the instruction cache 102 and the data cache 104 are directly mapped. The data cache 104 is a write-through data cache. The CPU 100 transmits the address and data to the write buffer 110 via the line 106. Similarly, the write buffer 110 is a FIFO write buffer having a depth of four stages. The write buffer 110 transfers the address and data to the second level data cache 120 via line 112. The write buffer 110 is further connected via line 114 to the address decoder.
Combined with 130. The second level data cache 120 is a direct mapping writeback data cache. The second level data cache 120 transfers addresses and data to bus 70 via line 124. The second level data cache 120 is further coupled to address decoder 130 via line 122.

Referring to the lower part of FIG. 1, addresses and data are
Communication is performed between the storage device 80 and the bus 70 via 82. Addresses and data are communicated between graphics subsystem 90 and bus 70 via line 92.

Alternative embodiments of the invention may include additional processors sharing the bus 70, storage 80, and graphics subsystem 90. For example, four microprocessors could share bus 70 instead of two.

Furthermore, in another alternative embodiment of the invention, a single processor could be coupled to bus 70 rather than multiple processors. In another such embodiment, the CPU 20
And the lower left circuit of FIG. 1 is part of the circuit of such an embodiment, but CPU 100 is no longer part of the circuit.

In yet another embodiment of the present invention, the circuit of the present invention comprises a write buffer or second level data cache 40,1.
Not equipped with 20. In other words, write buffer 30
And 110 and data caches 40 and 120 are not provided. However, a digital computer has a CPU
A decoding circuit coupled to the CPU, a bus coupled to the CPU, a memory coupled to the bus, and a subsystem coupled to the bus.

Returning to the preferred embodiment of FIG. 1 where circuit 10 includes multiple data caches, cache coherency,
Or there must be a way to maintain cache coherency. If cache coherency or cache coherency is maintained, CPU20
Even when writing to the cache 40, it is guaranteed that the CPU 100 can access the same data written in the cache 40.

Two state bits are used as part of the cache coherency retention scheme in the preferred embodiment of the invention. Two status bits can indicate the next four possible statuses.

(1) Valid state (valid) (2) Unjustified state (invalid) (3) Shared state (shared) (4) Contamination state (dirty).

In the preferred embodiment of the invention, the status bits are associated with a data line (in the cache). In the preferred embodiment, the data line (or line of data) (corresponding to the unit of mapping of the cache) is:
It consists of four data words. Modifying any of the data words that make up the data line means that the data line has been modified.

A valid state indicates that a particular data line from memory is only in one data cache and that data line has not been modified. In other words, the unchanged data line is the same in both the memory and the data cache. For example, unmodified data lines appear in both data cache 40 and storage 80.

The invalid state (invalid) means that there is no data in the cache. There, the cache is initialized to an illegal state. An illegal state also means the same state as a "miss".

A shared state indicates that a particular data line is probably in one or more caches and has not been modified. For example, data lines are in both data cache 40 and data cache 120.

A dirty state is that there is only one copy of a particular data line, it is the most recent copy, and only that cache has that particular data,
In addition, it indicates that the storage device 80 does not include the specific data. In other words, if the status bit corresponding to cache 40 is set to indicate a dirty condition (dirty), cache 40 will cache that particular data
Means that you have your own copy of the line. That is, that particular data line cannot be found in another data cache or memory device 80 in circuit 10. Thus, when the status bit indicates a dirty state of the data cache 40, both the data cache 120 and the storage device 80 will
It means that there is no copy of the line.

All operations involving the bus 70 require the involvement of the data cache 40 and data cache 120 and the storage device 80. Thus, cache 40 and cache 120 are both "snooping" caches in the sense of looking up an address on bus 70.

The cache coherency protocol will be explained using the cache state as an example. The data cache 40 and the data cache 120 are first set to an illegal state.
The data cache 40 is then in a valid state. After the data cache 40 is in the valid state, the CPU 100 requests reading from the main memory 80. So cache 40
Both the cache and the cache 120 are shared.

Now suppose, for example, that CPU 20 requests a write to data cache 40 at the same address. In other words, assume that CPU 20 has requested a write to a shared data line. The CPU 20 accordingly performs a bus operation via the bus 70 to notify that the data cache 120 is changed from the shared state to the invalid state for the data line. In this way, the cache 120 becomes invalid. The data cache 40 is then tainted.

Thus, the dirty (dirty) copy of that particular data line is in data cache 40, but not in data cache 120 or main memory 80. If the CPU 100 requests that a particular dirty data line be read, the data will come from the data cache 40 rather than from main memory 80. The reason is data
This is because cache 40 has its own copy of the modified data line. When the data is read by the CPU 100, the data is transferred from the cache 40 to the bus.
Head towards Cash 120 via 70. Then, the data cache 40 and the data cache 120 are returned to the shared state.

Depending on the status bit of the cache coherency protocol during a three-way transfer operation, for example, data cache 40 may have its own copy of the data line to be transferred (ie cache 40 may have a dirty copy). Data lines are transferred from cache 40, rather than from storage 80, via bus 70 to graphics subsystem 90. Similarly, if the data cache 120 has a modified, proprietary copy of the data to be transferred during a three-way transfer operation (ie, the cache 120 has a dirty copy), then the data is It is transferred from the cache 120 to the graphics subsystem 90 rather than from storage 80. Due to the consideration of the cache coherency protocol during the three-way transfer operation, only the most recently modified copy of the data word, and not the old, previous copy of the data word, is transferred. Guaranteed to be transferred as part of

Bus 70 is a 64-bit bus. The bus 70 includes address lines and data lines separately. CPU20 and CPU100 are
Bus 70 can be accessed at another time, and thus bus 70 is a multiplexed bus. The three-way transfer operation is a special bus operation.

In the preferred embodiment of the invention, each cache transfer is four.
It is the transmission of words. Thus, in the transfer using the bus 70,
Four data words (128 bits as 32 bits per word) are transferred for each address. Therefore, instead of transferring a single data word in a single bus cycle, four data words are transferred in a single bus cycle. Each time a single memory read or write operation is performed, four words are transferred simultaneously. Whether the CPU 20 needs 4 words, or less than 4 words, 4 words are transferred at the same time. For example, CPU2
Even if 0 requires 3 words instead of 4, CPU 20 will receive 4 words because less than 4 data is never transferred.

Storage device 80 and cache 22, 24, 40, 102, 104 and 120
Is organized around the cache's word boundary. Cache word boundary
301, 302, 304, 306 and 307 are shown in FIG. Data is shown below the column labeled "Data", and addresses are listed below the column labeled "Address".
Cache word boundaries 301, 302, 304, 306 and 3
07 organizes the data into groups of 4 data words. For example,
There are four words between Boundary 302 and Boundary 304. Thus, each of the boundaries 301, 302, 304, 306 and 307 is a 4-word boundary.

As shown in FIG. 1, graphics subsystem 90 has line 92
It is connected to the bus 70 via. In the preferred embodiment of the present invention, graphics subsystem 90 handles the transformation, rendering, and display of graphics information for a digital computer. These operations are performed locally using a pipelined "VLSI" processor, a parallel finite state processor, a high speed memory and a 32-bit microprocessor (all not shown). Graphic subsystem
90 includes a geometry subsystem (not shown), a rendering subsystem (not shown), and a display subsystem (not shown). The graphics management board (not shown) is part of the rendering subsystem, which is part of the graphics subsystem 90. The graphic management board includes a microprocessor (not shown) and a local storage device (not shown). Graphic management board microprocessor circuit
Communicate with 10 microprocessors 20 and 100. The graphics management board of the graphics subsystem 90 is also the graphics subsystem 90.
Monitor the activity of the geometric pipeline within.

Address decoder 50 is coupled to write buffer 30 via line 34. The address decoder 50 includes a decoder circuit that decodes the address in the write buffer 30. The information obtained from the address decoder 50 is used to determine whether to make a request on the bus 70 and also to determine whether to perform a read, write, or three-way transfer operation. ·cache
Used to decide what to do for 40.

The address decoder 50 transmits a signal to the data cache 40 via line 42. Address decoder 50
Decode or status bits are sent to register 60 via 52. The status or decode bits can be stored in register 60. The status or decode bits are also referred to as three way transfer bits or simply three way bits. Line 54,56
And 58 couple register 60 to address decoder 50. Lines 54, 56 and 58 provide the means by which register 60 transfers the 3-way transfer bit to register 50.

The three-way transfer bit includes (1) start address, trigger,
Bit, (2) end address trigger bit, and
(3) A tag bit is included. In the preferred embodiment of the invention, the tag bit is the fifth bit of the starting address associated with the three-way transfer operation. In other words, the tag bit is the start address (A0,A
2,..., A4,...) A4 bits.

The start address trigger bit, end address trigger bit, and tag bit are transmitted from address decoder 50 to register 60 for storage. The bits stored in register 60 can also be cleared and reset. The address decoder 50 is
Additionally, the bit at the ending address in the write buffer 30 can be sampled and transmitted to the register 60 via line 52 for storage. In the preferred embodiment of the invention, the fifth bit of the ending address is sampled and held. In other words, the A4 bit of the end address is sampled and saved.

The start address trigger bit provided by address decoder 50 is used to prevent further writes during a three-way transfer operation. The start address trigger bit further indicates that the next write operation will be a write to the start address. address·
The decoder 50 will generate an end address trigger bit as soon as there is a write to the start address. The end address trigger bit indicates that the next write operation will be a write to the end address.

Address decoder 130 and register 140 on the right side of FIG.
Perform the same function as the address decoder 50 and the register 60, respectively. Address decoder 130 decodes the address transmitted from write buffer 110 over line 114. Address decoder 130 transmits control signals to data cache 120 via line 122. Address decoder 130 stores the 3-way bit (ie, the decode or status bit) in register 1 via line 132 for storage.
Transmit to 40. The 3-way bit includes a start address trigger bit, an end address trigger bit, a tag (indicator) bit, and an end address bit in the same arrangement order as the tag (indicator) bit. Register 140 can be cleared and the 3-way bit stored in register 140 can be reset. Register 140 has lines 134,136
And address decoder 130 via 138. Thus, the contents of register 140 are
And 138 to the address decoder 130.

The programmable array logic element (“PAL”) 150
It contains the control logic for the circuit 10 of the digital computer. PAL 150 receives an input signal on line 152 and emits a control signal on line 154. Circuit 10 of PAL160
Control logic for PAL 160 receives input on line 162 and emits control signals on line 164.

PALs 150 and 160 control all of the cycles of bus 70. The PALs 150 and 160 determine if the bus 70 is requested. The PALs 150 and 160 ultimately determine whether a read/write operation should be performed or a three-way transfer operation should be performed. PAL150 and 160
Monitors the three-way transfer operation. The PALs 150 and 160 determine whether the write operation should be suppressed during the three-way transfer operation. PALs 150 and 160 monitor the status of the 3-way bits in registers 60 and 140 and receive the 3-way bits to make control decisions. PALs 150 and 160 ensure that the 3-way bit is saved, restored or cleared, depending on whether there is an interrupt and at what stage the circuit 10 is during the 3-way transfer operation. PALs 150 and 160 send control signals to transceivers (not shown) that control the direction of address and data flow through most of circuit 10.

In the preferred embodiment of the present invention, PALs 150 and 160 consist of flip-flops, state machines, and logic gates. In another embodiment of the invention, the PA
The control by L150 and 160 is microcoded. The logic used to program, or microcode, the PALs 150 and 160 follows the method described herein for performing a three-way transfer of digital information.

The three-way transfer operation of the present invention provides an efficient means of transferring data to the graphics management board (not shown) of graphics subsystem 90.

In the preferred embodiment of the invention, polygon tiling is used to display the graphical image on the display of the digital computer. In polygon tiling, an image is composed of a plurality of relatively small polygons.
The coordinates of each of these polygons are determined by the graphics subsystem 90
Must be transmitted from the bus 70 to the graphics subsystem 90 so that it can be received in the graphics pipeline of At each vertex of each polygon, the spatial components of X, Y and Z, and R, G, B
Color codes (ie red, green, blue) are associated. Thus, each vertex of each polygon has an X word, a Y word,
There are Z, R, G and B words which must be transmitted to the graphics subsystem 90 via line 70. Each of these words is a floating point number. Assuming that 6 words are associated with each vertex and that a polygon usually has 4 vertices, there will be 24 words per polygon. Recalling that each image to be displayed consists of many polygons, a large number of data words must be transmitted to the graphics subsystem 90. Moreover, such words must be transmitted to the graphics subsystem 90 at a sufficiently high rate to optimize the performance of the graphics subsystem 90.

During the three-way transfer operation, the data block is (1) the main storage device 80 or (2) the cache 0 or the cache 120.
From either (if cache 40 or cache 120 has its own copy of the data) to graphics subsystem 90 via line 70. The data block to be transferred is (1) a start address which is the address of the first word in the data block, (2) an end address which is the address of the last word in the data block, and (3) data. It has a word count that represents the number of words in the block.

FIG. 2 illustrates data blocks that can be transferred as part of a three-way transfer operation. Each "X" in Figure 2 is a bus 70
Figure 7 illustrates the words of a data block transferred over. As described above, the storage device 80 and the caches 40 and 12
0s are organized by cache boundaries such as 301, 302, 304, 306 and 307 in FIG. The cache boundary is divided into groups of four data words.
Every time a bus operation, that is, a data transfer using the bus is performed, four words are transferred at the same time.

As shown in FIG. 2, blocks of data to be transferred as part of a three-way transfer operation can have various word lengths.
The data blocks can also have different starting addresses and different ending addresses. For example, the data block in column A of FIG. 2 has a word count of 3, a starting address of 0, and an ending address of 2. Further, row A
Block does not cross the boundary.

The data block in column B has start address 1, end address 3, and word count 3.

To transfer arbitrary data via bus 70, 4 at the same time
You have to transfer one word. On the other hand, to transfer the data block of column A via bus 70, the sequence of data words from address 0 to address 3 must be transferred. Therefore, the CPU 20 of FIG. 1 starts the data in column A starting at address 0 and ending at address 2.
Even if you want to transfer only the block, the data at address 3 is also transferred. As such, the configuration of data lines in the cache of circuit 10 may result in extra data being transferred as part of any three-way transfer operation.
Similarly, if CPU 20 wants to transfer the data block in column B of FIG. 2, the data at address 0 is transferred along with the data block having start address 1, end address 3 and data word 3.

Thus, if all of the data blocks that CPU 20 wants to transfer are within the sequence of 4 data words sandwiched by two adjacent boundaries, CPU 20 will transfer which particular word of those 4 word sequences. Unable to specify what they want to do, CPU 20 gets all four words, regardless of whether they need them. In other words, if the low order bits of an address only identify where a particular data word is within a sequence of four data words, then this low order bit of the address is meaningless. Is. That is, CPU20
Cannot obtain only a single data word out of a group of four data words and must also receive the transmission of other data words of the same group. The four data words grouped together in the cache are sometimes collectively referred to as a line of data or a data line.

The data block in column C of FIG. 2 has a starting address of 2,
It is a data word with end address 4 and word count 3.
The data block in column C intersects the boundary 302. However, in a single data transfer via bus 70, 2
Only transfer sequences of four data words between two adjacent boundaries. Therefore, a single bus transfer operation for the block in column C transfers a sequence of four data words starting at address 0 and ending at address 3. The data at address 4 in the column C data block is not transferred as part of the first single bus transfer operation. The reason is that only the data between boundaries 301 and 302 is transferred as part of a single bus transfer operation. In order to transfer the data at address 4, the CPU 20 must start the next bus transfer operation. Of course, as part of this second bus transfer operation, not only the data at address 4 is transferred, but also the data at addresses 5, 6, and 7 (these are the boundaries 302).
Between 304 and 304), so they are forwarded.

Similarly, for the transfer of the data block in column D with start address 3, end address 5 and word count 3, 2
Occasional bus transfer operations (such as three-way transfer operations) are required. During the first bus transfer operation, the data words at addresses 0, 1, 2 and 3 are transferred. During the second bus transfer operation, the data words at addresses 4, 5, 6 and 7 are transferred (because the data words are between adjacent boundaries 302 and 304).
Thus, even if a block of data should be transmitted to the graphics subsystem 90 during a three-way transfer operation, the sequence of four data words will be used during each single transfer.
Transmitted to 90. Column E of FIG. 2 shows that a data block to be transferred as part of a three-way transfer operation can have a word count of one. Column F of FIG.
It shows that a data block to be transferred as part of a three-way transfer operation can have a word count of four. The transfers for columns A, B, E and F each require only a single transfer of the data line as part of a three way transfer operation. However, the column C and column D data blocks that intersect the boundary 302 require two bus transfers as part of the three-way transfer operation. The transfer of the data block in column E means that the data at addresses 1, 2, and 3 will be transferred as well as the data at address 0.

The column G data block has a word count of 6, starting address 1 and ending address 6. The data block in column G also intersects cache boundary 302. Therefore, to transfer the entire column G data block, two bus transfers are required.

Column H of FIG. 2 shows a data block that intersects two boundaries 302 and 304. The data block in column H has a word count of 8, a start address of 2 and an end address of 9. Complete transfer of the column H data block requires three bus transfers as part of the three-way transfer operation. In this case as well, extra data at addresses 0, 1, 10, 11 is transferred as part of the bus transfer. The data block in column I of FIG. 2 has three boundaries 302, 304, 30.
Cross with 6.

The data block in column I has a starting address of 1, a word count of 14 and an ending address of 14. Four bus transfers are required to transfer the entire column I data block. In this case, the address 0 is also used as part of the bus transfer.
And 15 data are also transferred.

It will be appreciated that other data blocks having other starting addresses, other ending addresses and other word counts not shown in FIG. 2 can also be transferred in accordance with the present invention. For example, when transmitting a double precision number, a data block with a word count of 4 or greater can be transmitted.

FIG. 3 is a timing diagram showing the sequence of events that occur during a three-way transfer operation. The clock signal is shown at the top of FIG. In the preferred embodiment of the invention, the cycle time is defined as the length of time between the rising edge of the clock and the next rising edge of the clock.

Waveform NA in FIG. 3 indicates the "Next Address" line. Waveform NA in FIG. 3 shows the address output from write buffer 30 on lines 34 and 32. These addresses were generated by CPU 20 and transmitted to write buffer 30 via line 26.

The waveform TA in FIG. 3 shows the second level data cache 40.
It shows the tag address that appears inside. This tag address is generated by the CPU 20. The address that appears in the waveform TA is the waveform NA
It is simply a delay from the address appearing in.

The waveform DA in FIG. 3 shows the second level data address appearing in the data cache 40. The addresses shown in waveform DA are waveform TA and waveform NA.
It is simply a delay of the above address.

Waveform CD shows the data appearing on line 32 from write buffer 30. This data is generated from CPU20,
It is transmitted to the write buffer 30 via the line 26.

Viewed another way, the waveform NA is indicative of the next address generated by the CPU 100 and out of the write buffer 110 and appearing on lines 114 and 112. Similarly, the waveform TA can be seen as indicating a tag address in the data cache 120, and the waveform CD is generated from the CPU 100,
It can be seen as showing the data exiting the write buffer 110 and appearing on line 112.

As shown in FIG. 3, the CPU 20 starts the three-way transfer operation by writing to the three-way trigger address. In FIG. 3, "3WT" represents a three-way trigger address. This is the first address in waveform NA. The 3-way trigger address is transmitted from CPU 20 via line 26 to write buffer 30. The write buffer 30, the line 34, and the address decoder 50 form a decoding circuit,
This circuit decodes the address sent to the write buffer 30. The address decoder 50 sets the start address trigger bit to indicate that the next write operation by the CPU 20 is a write to the start address of the block of data to be transferred during the three-way transfer operation. Decode the 3-way trigger address. The setting of the start address trigger bit by the address decoder 50 also serves to inform the second level data cache 40 that the next two write operations are "special". The address decoder 50 is
The signal for notifying the above is sent to the address decoder 50 and the second
Line 42 coupled to and from level data cache 40
To the second level data cache 40 via. The start address trigger bit is sent from the address decoder via line 52 and stored in register 60.

The next two writes are "special" writes.
Both writes are second level data cache 40
Writing is suppressed. Both writes also prevent further modification of the storage device 80. The next two writes are partial writes. In the preferred embodiment of the invention, the next two writes are data cache
Automatically put 24 into invalid state. The reason is that when a partial write to the data cache 24 is attempted, the data cache 24 is configured to become invalid. The fact that the next two writes are partial writes also means that the low-order byte of data containing the graphics command and word count will eventually be transferred to bus 70.

The three-way transfer operation includes the following three types of writing.

(1) Writing to the trigger address (2) Writing to the first start address, or data
If the block is longer, write one or more times to the intermediate address following it (3) Write to the end address (only when necessary) In the write operation and the read operation, the data is
Always follow the address. In other words, the address appears first in the transfer of digital information. The address appears on the waveform NA, the data appears on the waveform CD. The data indicated by D0 in the waveform CD of FIG. 3 represents data that is not used. The reason is that the CPU 20 is performing a write operation to the trigger address and therefore is not concerned with the data associated with the write to the trigger address.

The waveform MPREQ in FIG. 3 shows the microprocessor bus request signal transmitted from the CPU 20 to the bus 70. The waveform MPGRNT shown in FIG. 3 represents a microprocessor bus license line signal transmitted from the bus 70 to the CPU 20 and the CPU 100.

As shown in waveform NA of FIG. 3, the next signal appearing on lines 32 and 34 is the start address A1 for the write operation. First start address for write operation is second level data
When encountering cache 40, microprocessor bus 70
Is required and the three-way transfer operation of the microprocessor bus is further executed.

CPU20 that waveforms MPREQ and MPGRNT are set to low level
Immediately upon finding, the CPU 20 transmits the information appearing in the waveform NA of FIG. 3 to the microprocessor bus 70. If waveform MPA represents the address appearing on the address line of microprocessor bus 70, this is apparent from FIG. Thus, after the start address A1 appears in the next address waveform NA, and after the signals MPREQ and MPGRNT have been made low, the start address A1 appears in the waveform MPA. Before being received by the microprocessor bus 70, the starting address has been transmitted from the CPU 20 via line 26 to the write buffer 30. The address decoder 50 decodes the starting address (sent to the address decoder on line 34). As a result, the 3-way start address trigger bit is cleared and the 3-way end address trigger bit is set. The 3-way start address trigger bit is cleared by transmitting a clear signal to register 60. Three-way end address trigger bit is
Set by decoder 50, register 60 via line 52
Sent to and stored. In this way the end address
The trigger bit is saved. The physical start address contained within write buffer 30 is then placed on the address line of microprocessor bus 70. This is the waveform MP in Figure 3
It is indicated by A1 in A.

Word counts and graphics commands are typically used by the microprocessor bus 70 during periods reserved for writeback of data.
Are placed on the lower 16 data lines of. The word count is represented by "W" in the waveform MPD (write) of FIG.
The figure command is represented by "C" in the waveform MPD (write) of FIG. The waveform MPD (write) and the waveform MPD (read) both represent data on the data lines of the microprocessor bus 70.

The graphics command directs how to process the data being transferred as part of the three-way transfer operation. An example of the graphic command is the command "polygon drawing". Graphic commands are generated from the software of the digital computer shown in circuit 10 of FIG.

At the beginning of a clock cycle, the data is on the bus
Placed at 70. At the end of the clock cycle,
Graphics subsystem 90 latches the data so that the data is transmitted from bus 70 to graphics subsystem 90 over line 92. Therefore, there is a gap between the beginning of the clock cycle (cycle) and the end of the clock cycle (cycle), so that the settling time of that data is obtained. By the time the word count and graphics commands reach the microprocessor bus 70, the graphics subsystem 90 has already latteed the starting address A1.

The 16-byte data line specified by the physical start address A1 is the second line if and only if the cache 40 has a private copy of the 16-byte modified data line. The level cache 40 places it on the microprocessor bus 70. The 16-byte data line specified by the physical address is
If main memory 80 has the latest version of a 16-byte data line and the other caches do not have a modified proprietary copy of the 16-byte data line, Located on microprocessor bus 70 by main memory 80.

Next, the graphics subsystem 90 is a microprocessor bus.
Acquire or latch a 70 to 16 byte data line (or data block). Thus, as part of a three-way transfer operation, graphics system 90 acquires a starting address on the microprocessor bus, a word count, a graphics command, and a 16-byte data line (ie, data block).

When the second write to the second address enters the data cache 40, the second bus transfer will be a three-way bus only if there are additional words that are not transferred during the first three-way transfer operation. Initiated as part of the transfer. This is determined by comparing the fifth address bit of the second write address (ie bit A4) with the fifth address bit stored from the first write address (ie bit A4). If the bits are different,
Additional microprocessor bus transfer operations are performed as part of the three-way transfer operation as shown in FIG.

The 3-way end trigger bit is cleared regardless of whether a subsequent 3-way transfer operation is performed.

Referring to FIG. 3, each of waveforms MCWREQ0, MCWREQ1, MCWREQ2 and MCWREQ3 corresponds to a corresponding level of write buffer 30. When each of the above waveforms is low, it indicates that the write buffer at a particular level is full of data.

The waveforms WACK0, WACK1, WACK2 and WACK3 are handshake signals associated with each level of the write buffer 30.

The waveform CWREQ in FIG. 3 is simply all the waveforms MCWREQ0 to MCWREQ.
It is the logical sum of three. Therefore, CWREQ indicates that at least one write is pending. Waveform WBSEL in Figure 3
Indicates which level of the write buffer 30 is in operation.

In one embodiment of the present invention, the second, third, fourth, fifth, etc. write operations are one of the three-way transfer operations only if there are additional words that are not transferred during the three-way transfer operation. Started as a department. As shown in FIG. 3, T1 represents the time of the first write operation on the bus 70 of the three-way transfer operation. Time T2 is
A second write operation on bus 70 is represented. Time T3 represents the last write operation on bus 70. Performing more write operations on longer data word blocks means that the time T4, T5, T6, etc. will continue before a large word count data block is completely transferred to subsystem 90. For example, the data block in column I of FIG. 2 would require four operations rather than the three operations shown in FIG.

The final write operation of a three-way transfer always involves the transmission of the end address. Note that in FIG. 3, the trigger address is not transmitted between the last but one write and end operations. T1 in the waveform NA of FIG.
Between the first write operation of T2 and the second write operation of T2, the trigger address appears. For example, if there are four write operations as a part of the three-way transfer operation, the write to the trigger address is performed between the second and third write operations, but the third and last write operations are performed. Not done between actions. The reason is that writing to the trigger address performs a reset type function.

When the three-way transfer operation is completed, the next writing becomes possible.

In one embodiment of the present invention, a preliminary calculation to determine the number of writes that need to be performed during a three-way transfer operation is performed before the end address is written as part of the three-way transfer operation. Done. The word count of the data block to be transferred is divided by N, where N is the number of data words between two adjacent cache boundaries. In other words, N is the number of data words transferred during any bus transfer operation. Next, 1 is subtracted from the quotient. If the result after this subtraction contains a fractional integer, the result is rounded to the next higher integer. For example, if the result is 1.25, the result is rounded to 2. This yields the integer X. In the previous example, X would be 2. X
Is a positive integer other than 0, X write operations are performed after the first write operation of the three-way transfer operation and before the last write operation. This calculation is PAL1
This can be done by software associated with 50 and 160.

In another embodiment of the invention, the number of data words transferred during each bus transfer operation may be N, where N
Is an integer greater than or equal to 1 and greater than or equal to the word count. That is, it means that N data words are between the boundaries of the adjacent caches.

CPU20's exception, and thus context switch,
It can occur during any of the three writes associated with the three-way transfer of FIG. Therefore, the circuit shown in FIG. 1 has a function of disabling, saving and restoring the state of the first two writings. This function saves the following: (1) three way start address trigger bit, (2) three way end address trigger bit,
(3) Provided by saving the tag bit (the fifth bit of the start address (ie bit A4)). These bits can be stored in register 60 of FIG. Circuit 10 of FIG. 1 also provides the ability to read and write the three bits in register 60. If an interrupt occurs during a three-way transfer operation, the operating
The system first reads and stores the state of the three bits stored in register 60. The operating system then disables the real bit in register 60.
If the operating system wants to restore and restore the system state just before the interrupt,
The system restores the three bits to the state in register 60 immediately before the interrupt. To do so, the operating system first reads and stores the state of the three bits before they are disabled.

In another embodiment of the present invention, one could write to the serial port, for example, rather than writing to graphics subsystem 90 as part of a three-way transfer operation. Further, it would be possible to write to the second memory without writing to the graphics subsystem 90 as part of the three-way transfer operation.

In yet another embodiment of the present invention, it would be possible to transfer a block of data directly from subsystem 90 via bus 70 to memory 80 as part of a three way transfer operation.

The invention has been described so far with reference to particular embodiments. However, it will be apparent that many changes and modifications may be made without departing from the spirit and scope of the invention as set forth in the appended claims. Therefore, the specification and drawings are to be regarded as illustrative rather than restrictive.

Front Page Continuation (72) Inventor Germorak, Thomas Allan United States 94025 California Los Altos St. Joseph Avenue 892 (56) Reference JP-A-63-70386 (JP, A) JP-A-3- 31947 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 13/38-13/42 G06F 12/08-12/12 G06F 13/10-13/14 G06F 15/16

Claims (1)

(57) [Claims] 1. A central processing unit, a decoding circuit coupled to the central processing unit, a cache memory coupled to the decoding circuit, a bus coupled to the cache memory, and a main circuit coupled to the bus. A method for performing a special write-initiated transmission operation on digital information consisting of a start address and a data block in a digital computer having a memory device and a graphics subsystem coupled to the bus. And in that special transmission operation, the digital information is transmitted to the graphics subsystem, (1) the starting address is the address of the first word of the data block, and (2) the number of words of the data block is the word count. (A) Initiate the special transmission by performing a first write operation of the central processing unit to transmit a trigger address from the central processing unit to the decoding circuit. (B) the trigger address is decoded by the decode circuit, and (1) one of the central processing units.
Preventing the main memory device and the cache memory from being changed by the second write operation subsequent to the second write operation and (2) the third write operation subsequent to the second write operation of the central processing unit. (C) The second write operation of the central processing unit is executed to transfer from the central processing unit to the cache memory and the bus, (1) a start address, and (2).
Transmitting data including word counts and graphics commands; (d) transmitting a start address from the bus to the main memory and the graphics subsystem; (e) transmitting the main memory and graphics sub from the bus Transmitting the data, including word counts and graphics commands, to the system; (f) if only the cache memory has a modified sequence of N data words, the cache memory is proprietary. The modified sequence is transmitted directly from the cache memory to the graphics subsystem via the bus without being sent to the central processing unit that initiated the special transmission, where N
Is an integer greater than or equal to the word count, one of the data words in the sequence of N data words is at the start address, and the data block is contained in the sequence of N data words; (g) if , N data words have the latest sequence in the main memory and the cache memory does not have a modified sequence dedicated to that cache memory, the N data words A method of transmitting the latest sequence directly from the main storage device to the graphics subsystem via the bus without sending it to the central processing unit which initiated the special transmission.