JP3116587B2 - ATM cell processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an asynchronous transfer mode (ATM: Asynchronous Transfer) suitable for use in a communication path device of a broadband ISDN exchange.
r Mode) packet (cell) transmission circuit, in particular, an ATM suitable for causing packets (cells) input from a plurality of input lines to be discarded in the buffer memory equally to packets input to each input line. It relates to a cell multiplex buffer circuit or a cell switch circuit.

[0002]

2. Description of the Related Art A conventional cell switch circuit comprises a multiplexing circuit for periodically time-division multiplexing and outputting ATM cells input from a plurality of input lines, a buffer memory for storing the ATM cells output from the multiplexing circuit, It comprises a demultiplexer for periodically time-division multiplexing and demultiplexing ATM cells output from the buffer memory to respective output lines, and a control circuit for controlling input / output of ATM cells of the buffer memory and address management. In such a conventional cell switch circuit, when storing ATM cells in a buffer memory, it is necessary to discard the input ATM cells when the storage capacity of the buffer memory is exceeded. There is a problem in that, due to the timing relationship of the separation circuit, there is a non-uniformity between a certain outgoing line and each incoming line. This is because, for example, the number of cells in the buffer memory, which is input immediately after the output from the buffer memory to a certain output line, is always reduced immediately after the cells are output from the buffer memory, It can always be stored in the buffer memory without being discarded. On the other hand, a cell for an outgoing line that is input at the timing immediately before outputting to a certain outgoing line from the buffer memory may be filled with other cells until the output immediately before the buffer memory becomes full. There is a possibility that it may be discarded.

[0003] In response to the above problem, the document "Y.
Take, et. al. , "A One-Chip S
callable 8 * 8 ATM Switch LS
IEmpling Shared Buffer
Architecture, "IEEE J. Sel.
ect. Areas Commun. , Vol.
9, No. 8, pp. 1248-1254, Oct. 1
No. 991, a method is used in which the multiplexing method of the incoming line of the multiplexing circuit is not always time-division multiplexed at a fixed cycle, but is controlled so that the multiplexing order is changed and the multiplexing timing is evenly changed. For example, if there are four incoming lines 0, 1, 2, 3, first multiplex in the order of 0, 1, 2, 3, then 1, 2, 3, 0, then 2, 3, 0 The multiplex timing is periodically changed to 1, 1, and then 3, 0, 1, and 2 so that the input line timing relationship with the buffer memory output line timing is equal to each input line. .

[0004]

In the method disclosed in the above-mentioned document, the cells of each incoming line are always stored once in the multiplexing circuit and then output to the buffer memory, and the cells arrive from each incoming line even during the output of the multiplexing circuit. Therefore, a circuit for storing twice as many cells as the total number of input lines is required. Therefore, when a gate circuit such as a flip-flop or the like is used, a multiplexing circuit that only needs to store cells for the number of input lines required to perform periodic time-division multiplexing has a smaller amount of hardware than a multiplexing circuit described in the literature. Is small. In the case of a multiplexing circuit that only performs periodic time-division multiplexing, the amount of hardware can be reduced as disclosed in Japanese Patent Laid-Open No. 3-101441. Further, Japanese Patent Application Laid-Open No. 3-34
As disclosed in Japanese Patent Publication No. 48, 15
A switch circuit with only 0 Mb / s input line
A separation circuit for performing time division multiplexing / demultiplexing from 0 Mb / s to 150 Mb / s is provided only as an external circuit, and 600 Mb / s is provided.
In order to realize an input line, it is necessary to make a multiplex circuit in the switch circuit a multiplex circuit that only performs periodic time division multiplexing.

In the present invention, in order to take advantage of the use of a multiplexing circuit which only performs periodic time division multiplexing, this multiplexing circuit is used, and the cell discarding becomes equal regardless of the relationship between incoming and outgoing lines. A switch circuit and a cell multiplex buffer circuit are realized.

[0006]

SUMMARY OF THE INVENTION According to the present invention, a determination as to whether an input cell for an output line is stored or discarded in the buffer memory is made immediately after the cell to the output line is read from the buffer memory. Is determined by the relationship between the number of cells to the outgoing line in the buffer memory at the timing of and the threshold value. That is, if the number of cells in the buffer memory exceeds the threshold at that timing, the input cells to the outgoing line are discarded, and if not, even if the cells in the buffer memory exceed the threshold at the time of input. Store in buffer memory.

[0007]

In the above method, all input cells are stored in the buffer memory in the read cycle from the time immediately after the cell is read to the next read timing, with the number of cells immediately after the cell is read from the buffer memory. To be discarded. For this reason, during the read cycle, it is determined whether the input cell is stored in the buffer memory or discarded without depending on the output timing of the multiplexing circuit with respect to the incoming line, so that cell discarding becomes equal regardless of the relationship between the incoming line and the outgoing line. .

[0008]

FIG. 1 is a block diagram showing an embodiment of a cell multiplex buffer circuit having an equal control function. Incoming line L0, L
The cells input at 1, L2 and L3 are periodically time-division multiplexed by the multiplexer 1 and output to the line L4. The cells are stored in the FIFO memory 2 via lines L5 to L7 and Output to L8. As is well known, a cell is composed of a header part of several bytes and data (information) of several tens to several hundreds of bytes. In the header, for example, a logical channel number for identifying a call (source subscriber) and a header error are detected. Error check code etc. The buffer write / read management of the FIFO memory 2 is performed by the buffer control circuit 0.

The incoming lines L0, L1, L2, and L3 have the same transmission speed, and the transmission speed of the line L4 is four times that of each incoming line by the multiplexer 1. FIG. 2 shows an example of the operation timing of the multiplexer 1. Cells are stored in the order of L0, L1, L2, and L3 at each incoming line, and the cells are sequentially output at a quadruple transmission speed (1/4 timing of the incoming line). In this multiplexer 1, the incoming line L
The cells are always output in the order of 0, L1, L2, L3.

The FIFO memory 2 stores the transmission speed of the incoming line at 4
This is provided to match the transmission speed of the cell input at double with the transmission speed of the outgoing line L8. In this embodiment, it is assumed that the transmission rates of the incoming line and the outgoing line are the same.

Next, the buffer control circuit 0 will be described. The header of the cell output from the multiplexer 1 is supplied to a header analysis circuit 0-1.
A determination is made as to whether or not the cell is to be stored in the O memory 2. This determination output (header number) is supplied to the write terminal WEN of the FIFO memory 2 through the AND gates 0-2, and performs cell write control to the memory. . At this time, the counter 0-3 counts the number of cells stored in the FIFO memory 2 in response to the judgment output of the header analysis circuit 0-1, and counts each time writing is permitted at the write terminal WEN of the FIFO memory 2. Up. The read permission signal generation circuit 0-5 determines the transmission permission signal in accordance with the transmission speed of the output line L8.
A read permission signal is generated, supplied to the read terminal REN of the FIFO memory 2 through the AND gates 0-6, and controls reading from the memory. At this time, the counter 0-3 receives the read permission signal passed through the AND gate 0-6, and counts down by the signal. Note that when the counter value becomes 0, the counter 0-3 sets F
The comparator 0-4 outputs a signal indicating that there is no cell to be read from the IFO memory 2, and the comparator 0-4 receives the output and outputs "0". The read enable signal is output to the output side of the AND gate 0-6. Prevent output.

The count value a of the counter 0-3 is compared with the threshold value b of the threshold value register 0-7 by the comparator 0-8. When the counter value a exceeds the threshold value b (a> b), "0" is output. And flip-flops (FF) 0-9 and AND gate 0
Through −2, control is performed to prohibit the write operation of the cell into the FIFO memory 2. At other times (a ≦ b)
Is controlled to execute the cell write operation.
Here, in the present invention, FF0-9 and delay gate (D)
0-10 are added to realize equal control, that is, control in which cell discarding is equal for each incoming line regardless of the relationship between incoming and outgoing lines. In the FF0-9, the read permission signal generated from the read permission generation signal generation circuit 0-5 is slightly delayed by the delay gate D0-10, that is, the output signal of the read permission signal generation circuit 0-5 passes through the AND gate 0-6. Counting down by the counter 0-3, delaying the output until it becomes a timing at which the data can be taken in by the FF0-9 through the comparator 0-8, and taking in the signal of the comparator 0-8, immediately after reading the cell. The comparison result between the counter value and the threshold value is taken.

FIG. 3A is a circuit diagram of a cell multiplexing buffer circuit,
F0-9 and D0-10 are removed, and comparators 0-8 and AN
FIG. 3B shows the timing of each unit when the D gates 0-2 are directly connected, and FIG. 3B shows the timing of each unit when the FFs 0-9 and D-10 are provided. FIG. 3A shows a case where equal control is not performed, and FIG. 3B shows a case of the present invention where equal control is performed. The write cell of the FIFO memory 2 is input every time from each input line, the counter value starts from N-2, and the read permission signal is compared every time at the input cell timing of the input line L3. However, the threshold value is N. In the case of FIG. 3A, cell discarding occurs because the counter value becomes N at the timing of the first incoming line L2, and thereafter, cell discarding also occurs at the input cell timing of the incoming line L3. Since cells are read at the input cell timing of the input line L3, the counter value becomes N-1 at the input cell timing of the input line L0, and cell writing can be performed at the input cell timing of the input line L0. When a cell is stored at the input cell timing of the input line L0, the counter value becomes N. Thereafter, at the input cell timings of the inputs L1, L2, and L3, the counter value does not decrease and cell discarding occurs. Thereafter, at the input cell timing of the input line L0, the counter value is reduced to N-1 and the cells are stored. To repeat this operation, the cells of the incoming line L0 can always be stored in the FIFO memory 2, but the cells of the other incoming lines L1 to L3 are discarded, and the cells of the incoming line L0 are not discarded. Is performed.

In FIG. 3B, the counter value is compared with the threshold value at timing L0 immediately after reading. At the first timing L0, since the counter value is N-2 and smaller than the threshold value N, all cells from the first L0 to L3 are stored. Therefore, the counter value exceeds N at the time of the first L3, and becomes N + 1. At the next time point L0, the counter value becomes N + 1. Therefore, from L0 to L3, all input cells are discarded. In the third L0, the counter value becomes N, so that the cell is discarded even in the third period from L0 to L3. At the fourth L0, the counter value becomes N-1, so that the cell writing to the FIFO memory 2 is performed in the period from L0 to L3. Since the counter value is N + 2, cell discard is performed at L0 to L3. As described above, in the case of FIG. 3B, the storage / discard of the cell is determined for each period from L0 to L3.
In the period of L3, cells are stored in the input line L0,
In No. 3, it can be seen that there is no inequality such that cell discarding is performed, that is, it is possible to perform equal control without input line and cell discarding. FIG. 4 is a block diagram showing a configuration example of the multiplexer 1 of FIG. The cells input from the input line L0 are stored in flip-flops (FF) 1-0 to 1-3 for one cell, and when the head of the cell is stored in FF1-3, the selectors 1-16 to 1-19 switch to FF1- Select cells 0 to 1-3 and output cells to line L4. The cells input from the input line L1 are stored in flip-flops (FF) 1-4 to 1-7 for one cell, and when the head of the cell is stored in FF1-7, the selectors 1-16 to 1-19 switch to FF1- 4-1-7
And outputs a cell to the line L4. Cells input from the input line L2 are flip-flops (FF) 1-8 to 1
When one cell is stored in −11 and the head of the cell is stored in FF1-11, the selectors 1-16 to 1-19 operate in FF1
-8 to 1-11 are selected to output the cell to the line L4. The cells input from the input line L3 are stored in flip-flops (FF) 1-12 to 1-15 for one cell.
When the cell head is stored in 1-15, the selector 1-1
6 to 1-19 select the FFs 1-112 to 1-15 and output cells to the line L4. Since a cell is input from each incoming line at the timing shown in FIG. 2, the timing at the head of the cell is slightly shifted, and FF1-3, 1-7, 1
Since the time when the head of the cell arrives at -11 and 1-15 is different, when the selectors 1-16 to 1-19 select the FF, they do not select two at the same time.

In the configuration of the multiplexer, since the cell input at each input line is immediately output, only the FF holding one cell is required at each input line. The amount of hardware is small as compared with the method that needs to be held separately. Also, Japanese Patent Application Laid-Open No. 3-344
The use of Japanese Patent Publication No. 8 makes it possible to further reduce the amount of hardware compared to the configuration of FIG.

FIG. 5 is a block diagram showing an example of the configuration of an output buffer type switch circuit. This circuit corresponds to the FIFO in the cell multiplexing buffer circuit with equal control function shown in FIG.
An O memory 2 and a buffer control circuit 0 are provided for each output line. The header analysis circuit 0-1 (see FIG. 1) in the buffer control circuit 0a selects a cell to go to the outgoing line L8a. Header analysis circuit 0- in buffer control circuit 0b
1 (see FIG. 1) selects a cell to go to the outgoing line L8b. Header analysis circuit 0-1 in buffer control circuit 0c
(See FIG. 1) selects a cell to go to the outgoing line L8c. Header analysis circuit 0-1 in buffer control circuit 0d
(See FIG. 1) selects a cell to go to the outgoing line L8d. In this way, a switch that outputs a cell corresponding to each output line can be configured.

This switch uses the same principle as that of the cell multiplexing buffer circuit of FIG. 1 and, when the input conditions are the same, the cell discard rate becomes equal for each input line regardless of the timing between the input and output lines.

FIG. 6 shows a configuration example of a common buffer type switch. Cells input from the input lines L0 to L3 are periodically time-division multiplexed by the multiplexer 1 and stored in a common memory 2 'including a cell memory and a next address memory via lines L4 to L7. The cells read from the common memory 2 'are time-division-multiplexed and separated periodically by the separator 3, and each output line L
9 to L12. Buffer control circuit 0 '
Performs write / read control of the common memory 2 ′.
The operation timing of the demultiplexer 3 is opposite to that of the multiplexer 1. In FIG. 2, the right side is an input side and the left side is an output side.

Next, the buffer control circuit 0 'will be described.
First, write control is performed as follows. The output buffer management circuits 0'-A-0 to 0'-A-3 are provided corresponding to the outgoing lines L9 to L12, respectively, and perform write / read address management of the common memory 2 'for each outgoing line. ing. The header analysis circuit 0'-1 analyzes the output line to be output from the header of the input cell coming from the line L6, and outputs the output line number (header number) to each output buffer management circuit 0'-A-0. 0'-A-3, the output buffer management circuit corresponding to the outgoing line outputs the write address WA, and the output address is SEL0'-1.
2 and output to the common memory 2 '. At this time, the empty address FIFO memory 0'-11 storing an unused address in the common memory 2 'outputs an address to which the next input cell is to be written on this output line. This next address is written to the next address memory at the same address as the write address when the cell is written to the common memory 2 ', and further transferred to the output buffer management circuit that issued the write address WA. By repeating this operation, an address chain can be formed for each output line, in which the next address is read out at the time of reading out the cell and the address of the cell to be read out next is known. It should be noted that the output buffer management circuit 0 'which has taken in the outgoing line number (header number)
Any of -A-0 to A-3 is a write enable signal W
EN is issued, and this signal is supplied to the next address memory through the OR gate 0'-13 to permit writing of the cell to the common memory 2 '. However, in a state where writing cannot be permitted, the write enable signal WEN is not issued and the signal is not issued. Discard the cell. That is, storage of the cell in the memory is prohibited.

The read control is performed as follows.
First, the read output selection circuit 0'-5 issues the same output line number as the time division multiplexed demultiplexer of the demultiplexer 3, and the RNo of each output buffer management circuit 0'-A-0 to 0'-A-3. Is input to The output buffer management circuit corresponding to the outgoing line number outputs the read address RA, and passes through the SEL0'-15 for selecting one of the output buffer circuits in accordance with the outgoing line number. The data is supplied to the address memory to control cell reading from the cell memory. At this time, since the read address output from the next address memory becomes an unused address of the common memory 2 ', it is stored in the empty address FIFO memory 0'-11. Further, the next address is read from the next address memory of the common memory 2 ′, is taken into the output buffer management circuit that has output the read address RA, and is used as a read address when reading the next cell.

Further, the selected output buffer management circuit issues a read enable signal REN, and the read enable signal REN is ORed.
The data is supplied to the next address memory of the common memory 2 'through the gates 0'-14 and read permission is performed. When there is no cell to be read in the common memory 2', the signal REN is not issued and the common memory 2 'is not issued. Do not read cells.

Next, an example of the configuration of the output buffer management circuit 0'-A will be described with reference to FIG. The write address register A0 issues a write address WA, and the read address register A1 issues a read address RA. The comparator A5 that has input the write outgoing line number WNo issues a write enable signal when the outgoing line number managed by this circuit is the same (D = No). The signal is supplied to the write address register A0 through the AND gate A2, and the register is made writable, and the next address NWA is stored in the write address register A0. The comparator A6, to which the read out line number RNo has been input, issues a read permission signal when the line number is the same as the outgoing line number managed by this circuit (D = No). The signal is supplied to the read address register A1 through the AND gate A3, and the read address register A1 is made readable, and the next address NRA is stored in the read address register A1.

The counter A4 counts the number of cells to be output to the output line managed by this circuit in the common memory 2 'in response to the supply of the write permission signal and the read permission signal. It counts up when the write enable signal WEN is issued from the gate A2,
The countdown is performed when the read permission signal REN is issued from the AND gate A3. When the count value of the counter A4 is larger than 0, the output of the comparator A7 of the order becomes "1". As a result, the AND gate A3 outputs a read permission signal for the comparator A6. When the count value is 0, there is no cell to be read from the common memory 2 ', so the value of the comparator A7 is'0', and the read enable signal REN of the comparator A6 is blocked by the AND gate A3.
The value of the counter A4 and the value of the threshold register A9 are
8 and the output is delayed by the FFA 10 to the delay gate A
11 is latched by the timing clock immediately after the read operation. Here, FFA10 and delay gate A1
1 indicates that the count value immediately after reading is smaller than the threshold value (a <
b) In the case, the AND gate A2 is controlled to generate a write enable signal until the next reading is completed. In other cases, the AND gate A2 always outputs "0", that is, writing is disabled. Control. FFA
10 outputs the determination result of the count value of the counter A4 at the timing immediately after the reading, so that the write enable / disable prohibition of the FFA 10 becomes constant within the read cycle. , And cell discard can be equalized without depending on.

FIG. 8 shows an example of the configuration of another output buffer management circuit. FIG. 8 shows a configuration in which A12 to A31 are added except for the comparator A8, the FFA10, and the delay gate A11 in FIG. 7, and the writable condition based on the counter value and the threshold is different from that in FIG. A value obtained by subtracting the counter value from the threshold value is output from the subtractor A12, and is taken in by the FFA 15 by the timing clock immediately after the reading generated in the delay gate A16. If the subtraction value (ba) is equal to or greater than the number of incoming lines, the value of the counter A4 exceeds the threshold value in this read cycle, that is, in the period from immediately after the cell read to the next cell read even if the cell write is performed. Never. Therefore, in the comparator A13, the subtraction value is larger than 4 (D>
3) That is, if it is determined that the value is equal to or greater than the number of incoming lines,
The R gate A14 is always set to "1" to enable cell writing.

When the subtraction value of the output of the FFA 15 is smaller than the number of input lines, the circuits A17 to A31 operate effectively.
These circuits generate the same number of write time slots as the subtracted value, keep the write permission below the subtracted value,
It is a circuit that prevents the counter value from exceeding the threshold,
Further, a device is added in which the write time slot is generated equally for each incoming line timing. The counter A18 is a counter that counts up every reading cycle. When the counter value becomes 4, the comparator A31 is reset to "0". Thereby, the counter A18
Outputs values 0 to 3 periodically and evenly. Counter A2
Reference numeral 2 denotes a counter for generating a write time slot, the count value of which is changed as much as the number of input lines. That is,
When the input number is 0 to 3, 0, 1, 2, 3 and the count value are output. The count value of the counter A18 is latched by the FFA 19 at the timing immediately after the reading, and the value is added by the adder A17 to the subtraction value of the output of the FFA15.
When this addition value is 3 or less, that is, when it is smaller than the number of input lines, the comparator A21 outputs “0”, and when the count value of the counter A22 is 0 (D = 0), the comparator A25
Outputs '1', AND gate A29, OR gate A
28, the SR flip-flop A30 is reset to "0". The counter A22 counts up, and F
When it matches the output of FA19 (a = b), the comparator A2
4. The SR flip-flop A30 is set to "1" via the OR gate A26. The circuit A20 outputs a remainder obtained by dividing the value of the adder A17 by 4. When the output of the adder A17 is 3 or less, the added value is directly input to the comparator A23. When the counter A22 further counts up and becomes equal to the added value (a = b), the comparator A23 outputs the SR through the OR gate A28.
The flip-flop A30 is reset to “0”. With this operation, the write enable signal on the write timing is generated by the subtraction value of the output of the FFA 15.

The added value of the adder A17 exceeds 3 (D>
In the case of 3), the value of the circuit A20 becomes a value obtained by subtracting 4 and becomes smaller than the value of the FFA19. In this case, the comparator A21 is set to "1", and when the counter A22 is 0, the SR flip-flop A30 is set to "1" via the comparator A25, the AND gate A27, and the OR gate A26. , When the counter A22 becomes equal to the circuit of A20, the comparator A23, the OR gate A28
, Resets the SR flip-flop A30 to “0”, and when the counter A22 becomes equal to the FFA19, sets the SR flip-flop A30 to “1” via the comparator A24 and the OR gate A26. With this operation, the write enable signal on the write timing
It is generated by the subtraction value of the FFA15 output.

In order to prevent a set / reset signal from being simultaneously input to the SR flip-flop A30 by the comparator A24 and the comparator A25, the output of the AND gate A29 becomes "0" by the "1" output of the comparator A24. It is like that. Also, S is determined by the comparator A23 and the comparator A25.
In order to prevent a set / reset signal from being simultaneously input to the R flip-flop A30, the output of the AND gate A27 is set to "0" by the "1" output of the comparator A23. When the subtraction value of the FFA 15 is 0, the comparators A23 and A24 output '1' at the same time,
A set / reset signal is input to the SR flip-flop A30 at the same time. However, when the subtraction value is 0, cell writing is not performed, so that the SR flip-flop A30 needs to be a reset priority circuit.

The output buffer management circuit shown in FIG. 8 is a system which gives equal writable timing to each incoming line within a read cycle within a range where the number of cells does not exceed a threshold value. 7 is different from the circuit of FIG. 7 which takes only one of the possible and impossible states in that there may be an input line for which writing is permitted and an input line for which writing is not permitted in the read cycle. That is, the method of FIG.
0 to L3 are all written or discarded,
In FIG. 8, when there is a buffer for storing two cells, for example, the input lines L0 and L3 are discarded, but the input lines L1 and L2 are stored.

[0029]

As described above, according to the present invention, after a cell is multiplexed by a multiplexing circuit that periodically performs time division multiplexing,
The determination of whether to input or discard a cell of an outgoing line into the buffer memory is made based on the number of cells for the outgoing line in the buffer memory and the threshold value immediately after the cell of the outgoing line is read from the buffer memory. Because of the relationship
That is, if the number of cells in the buffer memory exceeds the threshold value at that time, the input cells to the outgoing line are discarded. According to such a method, all cells are read in the read cycle from immediately after the cell is read to the next read timing and the number of cells immediately after the cell is read from the buffer memory. It is determined whether the input cell is stored in the buffer memory or discarded. For this reason, during the read cycle,
Whether the input cell is stored in the buffer memory or discarded is determined without depending on the output timing of the multiplexing circuit for the incoming line, the cell can be discarded equally regardless of the relationship between the incoming line and the outgoing line.

Further, according to the present invention, it is possible to use a multiplexing circuit which only performs periodic time-division multiplexing, thereby making it possible to reduce the amount of hardware. Also, since the multiplexing circuit in the switch circuit is a multiplexing circuit that only performs periodic time-division multiplexing, for example, a switch circuit having only a 150 Mb / s input line is used to convert 600 Mb / s to 150 Mb / s.
It is possible to realize a 600 Mb / s input line only by providing a demultiplexing circuit for time division multiplexing and demultiplexing at b / s as an external circuit. In other words, even if a multiplexing circuit that only performs periodic time-division multiplexing having these advantages is used, a cell multiplexing buffer circuit that equalizes cell discarding regardless of the relationship between incoming and outgoing lines due to buffer memory write control. And an effect that a cell switch circuit can be realized.

[Brief description of the drawings]

FIG. 1 is an embodiment of a cell multiplex buffer circuit with an equal control function according to the present invention.

FIG. 2 is an operation timing of the multiplexer 1 in FIG.

FIG. 3 is a timing chart of each part in the cell multiplex buffer circuit of FIG. 1;

FIG. 4 is an embodiment of the multiplexer 1 in FIG. 1;

FIG. 5 is an embodiment of the output buffer type switch of the present invention.

FIG. 6 is an embodiment of a common buffer type switch of the present invention.

FIG. 7 is an embodiment of the output buffer management circuit in FIG. 6;

FIG. 8 is another embodiment of the output buffer management circuit in FIG. 6;

[Explanation of symbols]

0, 0a, 0b, 0c, 0d, 0 '... buffer control circuit, 1 ... multiplexer, 2, 2a, 2b, 2c, 2d ... FIFO memory, 2' ... common memory, 3 ... separator, L0, L1, L2, L3 ... incoming lines, L8, L8a, L8b, L8c, L8d, L9, L1
0, L11, L12 ... outgoing line, 0-1, 0'-1 ... header analysis circuit, 0-2, 0-6, A2, A3, A27, A29 ... AND
Gate, 0-3, A4, A18, A22 ... Counter, 0-4, 0-8, A5, A6, A7, A8, A13, A
21, A23, A24, A25, A31: comparator, 0-5: read permission signal generation circuit, 0-7, A9: threshold register, 0-9, 1-0 to 1-15, A10, A15, A19 ...
Flip-flop, 0-10, A11, A16 ... delay gate, 1-16 to 1-19, 0'-12, 0'-15 ... selector, 0'-5 ... read output selection circuit, 0'-11 ... empty Address FIFO memory, 0'-13, 0'-14, A14, A26, A28 ... O
R gate, 0'-A-0 to 0'-A-3: output buffer management circuit, A0: write address register, A1: read address register, A12: subtractor, A17: adder, A20: MOD circuit, A30 ... SR flip-flop.

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Yutaka Ito 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture In-house Information and Communications Division, Hitachi, Ltd. (56) References JP-A-4-276943 (JP, A) 2-1669 (JP, A) JP-A-3-143139 (JP, A) JP-A-6-85843 (JP, A) Technical report of the Institute of Electronics, Information and Communication Engineers, IN92-92 (58) .Cl. ⁷ , DB name) H04L 12/28 H04L 12/56

Claims (2)

(57) [Claims] 1. A packet (cell) comprising a header section and a data section, which is supplied via a plurality of incoming lines, is periodically time-division multiplexed, temporarily stored in a memory, and the stored time-division multiplexed packet. To output to one or more outgoing lines
In an ATM mode system having a cell processing circuit, the circuit comprises: a multiplexer 1 for periodically time-division multiplexing a packet (cell) composed of a header and data supplied through a plurality of input lines; A buffer memory 2 for storing a time-division multiplexed packet of the multiplexer, a header of the time-division multiplexed packet of the multiplexer, and storing and storing the packet in the buffer memory in accordance with the header. Packets from the buffer memory
A buffer control circuit 0 for controlling the fetching. The buffer control circuit manages packets in the buffer memory in one or more groups, and immediately after a packet in a certain group is read from the buffer memory. From the relationship between the number of packets in the buffer memory and a predetermined threshold value indicating the storage allowable value of the buffer memory, the number of packets for each incoming line is determined immediately after packet reading in that group until packet reading in the next group. Or an ATM cell processing circuit, comprising: a buffer control unit that determines storage and discard of a packet input to the buffer memory for all incoming lines. 2. The buffer memory according to claim 1, wherein the buffer control circuit receives a header of the time-division multiplexed packet from the multiplexer and writes a packet corresponding to the header into the FIFO memory. Means for reading a packet from the FIFO memory based on a data read permission signal; writing and reading of the packet by the packet writing means and the packet reading means; A buffer control unit for controlling the packet read operation; the buffer control unit counts the number of packets in the FIFO memory in response to the number of times of writing and reading by the writing unit and the reading unit; Read from buffer memory Means for prohibiting a read operation from the buffer memory based on the packet read permission signal in a state indicating that there should be no more packets, and comparing the count value and the threshold value when reading cells from the FIFO memory. 2. The AT according to claim 1 , further comprising means for outputting, when the count value exceeds the threshold value, a signal for inhibiting an operation of writing the packet into the buffer memory by the writing means.
M cell processing circuit.