JP3113676U - Plasma television and power circuit - Google Patents

Abstract

Various power supply voltages are prevented from being output to a PDP in an inappropriate order due to a malfunction of a microcomputer.
Each of a first erase voltage generation circuit, a second erase voltage generation circuit, and a scan voltage generation circuit generates an address voltage and outputs each sub voltage from an address voltage generation circuit that outputs the address voltage to a PDP. The first erase voltage Vset, the second erase voltage Ve, and the scan voltage Vscan based on each of the sub voltages are provided on the precondition that the sustain voltage generation circuit 52 is activated and the sustain voltage Vsus is output. Each power supply voltage can be generated and output.
[Selection] Figure 2

Description

  The present invention relates to a plasma television and a power supply circuit.

FIG. 6 is a block diagram showing a part of a power supply circuit for driving a plasma display panel (PDP) in a conventional plasma television.
The power supply voltages required for driving the PDP usually include a sustain voltage Vsus, an address voltage Vadd, a first erase voltage Vset, a second erase voltage Ve, and a scan voltage Vscan. These various power supply voltages have ideal voltage levels, and the conventional power supply circuit generates such various power supply voltages and outputs them to the PDP with the configuration shown in FIG.

  That is, the rectifier circuit 110 receives an AC voltage from a commercial AC power supply outside the television and converts the AC to a DC voltage. Then, the converted DC voltage is output in parallel to the generation circuits 121 to 125 for the sustain voltage Vsus, the address voltage Vadd, the first erase voltage Vset, the second erase voltage Ve, and the scan voltage Vscan, respectively. Each of the generation circuits 121 to 125 includes a transformer having a specific turn ratio, and the DC voltage is input to the primary side of the transformer, and the sustain voltage having a desired voltage level is input to the secondary side of the transformer. The voltage Vsus, the address voltage Vadd, the first erase voltage Vset, the second erase voltage Ve, and the scan voltage Vscan are taken out.

  In the power supply circuit, a control unit (microcomputer) (not shown) controls the start timing of each of the generation circuits 121 to 125 based on a predetermined sequence. For example, the microcomputer activates the address voltage generation circuit 122 and the sustain voltage generation circuit 121 in this order when the television is turned on, and then the first erase voltage generation circuit 123, the second erase voltage generation circuit 124, and the scan. The supply of various power supply voltages to the PDP is controlled based on specific ideal timing so that the voltage generation circuit 125 is activated almost simultaneously.

As a conventional technique, a display device is known in which the power supply unit 11 outputs the high voltage Vs to the display unit after the low voltage Vcc or the ground potential GND fed back from the display unit 12 is input (for example, patents). Reference 1).
Further, Patent Documents 2 and 3 are known as related prior arts.
JP-A-8-314407 JP 7-191623 A JP 2004-222485 A

In the conventional power supply circuit described, the direct current from the rectifier circuit 110 is output in parallel to the generation circuits 121 to 125, and the activation timing of the generation circuits 121 to 125 is left only to the control of the microcomputer. It has been.
Therefore, when the microcomputer malfunctions, for example, the first erase voltage generation circuit 123, the second erase voltage generation circuit 124, and the scan voltage generation circuit 125 precede the address voltage generation circuit 122 and the sustain voltage generation circuit 121. There is a risk that various power supply voltages may be supplied to the PDP in an inappropriate order and timing ignoring the above sequence. When various power supply voltages are supplied to the PDP in such an inappropriate order and timing, a heavy burden is placed on the PDP, causing a failure.

  Further, the above-mentioned document 1 and the like control the activation timing of each circuit such as the address voltage generation circuit 122, the sustain voltage generation circuit 121, the first erase voltage generation circuit 123, the second erase voltage generation circuit 124, and the scan voltage generation circuit 125. It is not intended to prevent various power supply voltages from being supplied in an inappropriate order and timing to the PDP when a malfunction occurs in the microcomputer.

  The present invention has been made in view of the above problems, and even when a malfunction occurs in the control unit that controls the power supply circuit, the supply timing of various power supply voltages to the PDP is prevented from being disturbed. An object of the present invention is to provide a plasma television and a power supply circuit for protection.

  In order to achieve the above object, the invention of claim 2 generates a plurality of power supply voltages including at least an address voltage and a sustain voltage, and outputs the generated power supply voltages to the plasma display panel to drive the plasma display panel. A rectifier circuit that inputs an AC voltage to generate a DC voltage, and inputs the DC voltage to a primary winding of a transformer, and an address voltage and a sustain voltage at a predetermined voltage level in the secondary winding. Voltage and output the generated address voltage and sustain voltage to the plasma display panel, and a plurality of sub-voltages having different voltage levels from the lead wires having different winding positions in the secondary winding. A drive voltage generator that outputs each sub-voltage to the outside, and inputs each of the plurality of sub-voltages. The plurality of sub-voltage adjustment output units that adjust the input sub-voltage to a predetermined voltage level and output to the plasma display panel, and the plurality of sub-voltage adjustments from any one of the address voltage and the sustain voltage. The power supply voltage of the switch circuit that activates the output unit is generated, and the switch circuit power supply unit that activates each sub-voltage adjustment output unit by supplying the generated power supply voltage to the switch circuit.

In the second aspect configured as described above, the rectifier circuit receives an AC voltage and generates a DC voltage. The drive voltage generation unit inputs the DC voltage to the primary winding of the transformer, generates an address voltage and a sustain voltage at a predetermined voltage level in the secondary winding, and generates the address voltage Sustain voltage is output to the plasma display panel. Further, the drive voltage generation unit derives a plurality of sub-voltages having different voltage levels from the conducting wires having different winding positions in the secondary winding, and outputs each sub-voltage to the outside. On the other hand, a plurality of sub-voltage adjustment output units each input a specific sub-voltage, adjust the input sub-voltage to a predetermined voltage level, and output it to the plasma display panel.
Further, the switch circuit power supply unit generates a power supply voltage of the switch circuit that activates the plurality of sub voltage adjustment output units from either the address voltage or the sustain voltage, and supplies the generated power supply voltage to the switch circuit. Then, the switch circuit is turned on to activate each sub-voltage adjustment output unit.

  That is, each sub voltage adjustment output unit is provided with a sub voltage via a drive voltage generation unit that generates an address voltage and a sustain voltage, and the power supply voltage itself to the switch circuit that drives the sub voltage adjustment output unit Is generated based on the output voltage of the drive voltage generator. As a result, each sub voltage adjustment output unit does not start unless the drive voltage generation unit is activated to generate and output the address voltage and the sustain voltage, and the address voltage and the sustain voltage are erroneously output. In this state, it is possible to reliably prevent the output voltage of the sub voltage adjustment output unit from being supplied to the PDP.

According to a third aspect of the present invention, in the power supply circuit according to the second aspect, each of the drive voltage generators has a transformer and generates and outputs an address voltage and a sustain voltage. The address voltage generating unit is configured to derive the plurality of sub-voltages from conductive wires having different winding positions in the secondary winding of the transformer.
With this configuration, the sub voltage is supplied from the address voltage generation unit to each sub voltage adjustment output unit as the address voltage is generated in the address voltage generation unit. When a voltage is output, the address voltage is always output to the PDP.

According to a fourth aspect of the present invention, in the power supply circuit according to the third aspect, the switch circuit power supply unit is provided on an output side of the sustain voltage generation unit, and a predetermined voltage is generated by dividing the output sustain voltage. The power supply voltage to the switch circuit at the voltage level is acquired.
The switch circuit power supply unit is provided on the output side of the sustain voltage generation unit and divides the sustain voltage to acquire the power voltage of the switch circuit. Therefore, the switch circuit is turned on and each sub voltage adjustment output unit is activated. In this case, the sustain voltage generator is always activated, and the sustain voltage is already output to the PDP together with the address voltage.

The invention of claim 5 is the power supply circuit according to any one of claims 2 to 4, wherein the plurality of sub voltage adjustment output units adjust the sub voltage to generate and output a scan voltage. An output unit, a first erase voltage output unit that generates and outputs a first erase voltage by adjusting a sub voltage, and a second erase voltage output unit that generates and outputs a second erase voltage by adjusting the sub voltage It is constituted as follows.
That is, as specific examples of the sub voltage adjustment output unit, a scan voltage output unit that generates and outputs a scan voltage, a first erase voltage output unit that generates and outputs a first erase voltage, and a second erase voltage are provided. A second erase voltage output unit that generates and outputs the power supply voltage is considered. The power supply voltage generated by each unit is output to the PDP on the condition that the address voltage and the sustain voltage are output to the PDP.

The invention of claim 6 is the power supply circuit according to any one of claims 2 to 5, wherein the sub-voltage adjustment output unit uses a shunt regulator when adjusting and outputting the input sub-voltage. The output voltage is stabilized by a stabilization circuit.
In other words, since each sub voltage output from the drive voltage generation unit may have an unstable voltage level, each sub voltage adjustment output unit adjusts the voltage output to the PDP to a desired voltage level. It outputs after making it stable DC. As specific examples of the stabilization circuit, circuits using various configurations such as a shunt regulator, a series regulator, and a switching regulator can be employed.

  Based on the above configuration, the invention of claim 1 generates a plurality of power supply voltages including at least an address voltage and a sustain voltage, and outputs the generated power supply voltages to the plasma display panel. In a plasma television having a power supply circuit for driving a rectifier, a rectifier circuit that inputs an AC voltage and generates a DC voltage, and the DC voltage is input to a primary winding of a transformer and a predetermined value is applied to a secondary winding A voltage-level address voltage is generated and output to the plasma display panel, and a plurality of sub-voltages having different voltage levels are derived from conductors having different winding positions in the secondary winding, and each sub-voltage is Address voltage generator for output to the outside, and the DC voltage is input to the primary winding of the transformer to the secondary winding A sustain voltage generator for generating a sustain voltage of a predetermined voltage level and outputting the sustain voltage to the plasma display panel; and inputting any one of the plurality of sub voltages and adjusting the sub voltage to a predetermined voltage level. A scan voltage output unit that generates a scan voltage and outputs it to the plasma display panel, and inputs one of the plurality of sub-voltages and adjusts the sub-voltage to a predetermined voltage level to generate a first erase voltage A first erasing voltage output unit for outputting to the plasma display panel; and inputting any one of the plurality of sub-voltages and adjusting the sub-voltage to a predetermined voltage level to generate a second erasing voltage, A second erasing voltage output unit for outputting to the plasma display panel and an output side of the sustain voltage generating unit; And generating a power supply voltage for each switch circuit for driving the scan voltage output unit, the first erase voltage output unit, and the second erase voltage output unit by dividing the output sustain voltage, and A switch circuit power supply unit that supplies the generated power supply voltage to each switch circuit to drive the scan voltage output unit, the first erase voltage output unit, and the second erase voltage output unit, respectively, and further outputs the scan voltage output The first erase voltage output unit and the second erase voltage output unit are configured to stabilize the output voltage by a stabilization circuit using a shunt regulator when adjusting and outputting the sub-voltage.

  Thus, in claim 1 having a more specific configuration, it goes without saying that the same operations and effects as in claims 2 to 6 are exhibited.

  As described above, according to the present invention, as long as the address voltage and the sustain voltage are not generated and output among the various power supply voltages for driving the PDP, the scan voltage, the first erase voltage, Since the power supply voltage based on the sub voltage such as the erase voltage of 2 is not generated and outputted, the output voltage of the sub voltage adjustment output unit is erroneously supplied to the PDP before the address voltage or the sustain voltage. Therefore, it is possible to eliminate overloading and failure of the PDP caused by inputting various power supply voltages to the PDP in an order different from the original order.

(1) Configuration of Plasma Television FIG. 1 is a block diagram showing a schematic configuration of a plasma television according to an embodiment of the present invention.
In the figure, a plasma television 100 is generally composed of a PDP 40, a video processing circuit 20, a tuner circuit 10, a microcomputer 60, a panel drive circuit 30, and a power supply circuit 50. The tuner circuit 10 receives TV radio waves from the antenna 10a, and extracts video signals and the like from TV radio waves in a frequency band designated by the microcomputer 60.

The video processing circuit 20 generates a digital video signal based on the video signal input from the tuner 10. The digital video signal generated by the video processing circuit 20 is input to the panel drive circuit 30, and the drive signal for the PDP 40 is generated by the panel drive circuit 30.
With the above configuration, video based on TV radio waves can be reproduced on the PDP 40. Of course, not only the TV image received by the antenna 10a but also the TV image by CATV may be reproduced, or the image signal input from an external device such as a DVD video deck may be reproduced. The video processing circuit 20 only needs to support each signal format, and the TV radio wave input to the tuner circuit 10 may be in a digital format or an analog format.

  The power supply circuit 50 inputs commercial AC power via a power cable 57, and as a power supply voltage for driving the PDP 40, a sustain voltage Vsus, an address voltage Vadd, a first erase voltage Vset, and a second erase voltage Ve and the scan voltage Vscan are generated and output to the PDP 40. The power supply circuit 50 supplies necessary power to each circuit constituting the plasma television 100 including the microcomputer 60 in addition to the PDP 40.

  The sustain voltage Vsus and the address voltage Vadd are respectively supplied to the sustain electrode and the address electrode in the cell provided in the PDP 40, and the scan voltage Vscan is supplied to the scan electrode in the cell provided in the PDP 40. In the PDP 40 of the present embodiment, a surface discharge method is employed in which a pulse voltage is applied between the scan electrode and the sustain electrode in the cell in which preliminary discharge is performed by the address electrode, thereby causing discharge in the display surface direction of the PDP 40. . The first erase voltage Vset and the second erase voltage Ve power supply are used for erasing the charge remaining in the cell.

  Each of the power supply voltages has an ideal voltage level for output to the PDP 40. In this embodiment, the sustain voltage Vsus is desirably 205V, and the address voltage Vadd is desirably 65V. The first erase voltage Vset is preferably 175V, the second erase voltage Ve is preferably 85V, and the scan voltage Vscan is preferably -220V.

  Further, it is desirable that each power supply voltage is output to the PDP 40 in a specific order and timing when the plasma television 100 is started. In this embodiment, when the main power supply of the plasma television 100 is input, the power supply circuit 50 first generates and outputs the address voltage Vadd within a predetermined time, and then within the predetermined time. A sustain voltage Vsus is generated and output. When the supply of the address voltage Vadd and the sustain voltage Vsus is stabilized, the first erase voltage Vset, the second erase voltage Ve, and the scan voltage Vscan are generated and output within a predetermined time.

Such an order and timing of generating and outputting various power supply voltages are realized by the microcomputer 60 controlling the power supply circuit 50 based on a predetermined sequence.
Here, there is no problem when the microcomputer 60 operates normally and the above sequence is observed. However, when the microcomputer 60 malfunctions and the above sequence is broken, the address voltage Vadd and the sustain voltage are not affected. Prior to Vsus, the first erase voltage Vset, the second erase voltage Ve, and the scan voltage Vscan may be output to the PDP 40.
Therefore, in the present invention, the power supply circuit 50 is configured as follows to prevent the above-described inconvenience seen in the past.

(2) Power Supply Circuit FIG. 2 is a block diagram showing a part of the power supply circuit 50 according to the present invention.
In the figure, first, the rectifier circuit 51 receives an AC voltage and converts the AC into a DC voltage.
Next, the DC voltage output from the rectifier circuit 51 is input in parallel to the address voltage generation circuit 53 and the sustain voltage generation circuit 52. Each of the address voltage generation circuit 53 and the sustain voltage generation circuit 52 includes a transformer having a specific turn ratio inside, and the address voltage having the ideal voltage level on the secondary side of each transformer. Vadd and the sustain voltage Vsus are taken out. The address voltage Vadd and the sustain voltage Vsus thus generated are output to the PDP 40 thereafter. Note that the order and timing at which the address voltage generation circuit 53 and the sustain voltage generation circuit 52 are activated and the above processing is executed are controlled by the microcomputer 60 as described above.

  In the embodiment, a first erase voltage generation circuit 54, a second erase voltage generation circuit 55, and a scan voltage generation circuit 56 for generating the first erase voltage Vset, the second erase voltage Ve, and the scan voltage Vscan, respectively. Are not directly connected to the output side of the rectifier circuit 51 but are connected via an address voltage generation circuit 53 therebetween. That is, the first erase voltage generation circuit 54, the second erase voltage generation circuit 55, and the scan voltage generation circuit 56 are configured to receive voltage supply from the address voltage generation circuit 53.

FIG. 3 schematically shows a part of the power supply circuit 50 with a focus on the internal structure of the address voltage generation circuit 53.
A power source converted into a direct current by the rectifier circuit 51 including the rectifier bridge is input to one end of the primary winding of the transformer 53a. The other end of the primary side winding of the transformer 53a is connected to the collector of the switching transistor Tr3, and the voltage transmitted to the secondary side can be adjusted according to the duty ratio of the base current of the switching transistor Tr3. It is possible. The base current of the switching transistor Tr3 is generated by a feedback circuit 53b that monitors the voltage at the secondary winding of the transformer 53a. The feedback circuit 53b reduces the duty ratio of the base current of the switching transistor Tr3 when the secondary side of the transformer 53a becomes a high voltage. On the other hand, when the secondary side of the transformer 53a becomes a low voltage, the duty ratio of the base current of the switching transistor Tr3 is increased. Thereby, the secondary side voltage of the transformer 53a can be made constant.

From the secondary winding of the transformer 53a, four conducting wires having different unwinding positions are derived, and different values of voltage are output to each conducting wire. The DC voltage output from the conductor whose output voltage is adjusted to about 65 V is the address voltage Vadd, and this address voltage Vadd is output to the PDP 40.
Further, a sub-voltage Vsub1 is output from a conducting wire whose output voltage is adjusted to about 175 V, and this conducting wire is connected to a first erase voltage (Vset) generation circuit 54. Similarly, the sub-voltage Vsub2 is output from the conductor whose output voltage is adjusted to about 85V, and this conductor is connected to the second erase voltage (Ve) generation circuit 55, and the output voltage is adjusted to about -220V. The sub-voltage Vsub3 is output from the conducting wire, and this conducting wire is connected to the scan voltage (Vscan) generating circuit 56.

  With the above configuration, the sub-voltage Vsub1 adjusted to about 175 V is input to the first erase voltage generation circuit 54 via the address voltage generation circuit 53, and the second erase voltage generation circuit 55 is about The sub voltage Vsub2 adjusted to 85V can be input, and the sub voltage Vsub3 adjusted to about −220V can be input to the scan voltage generation circuit 56. That is, in a state where the sub voltages Vsub1 to Vsub3 are input to each circuit, the address voltage is always generated and output to the PDP 40.

In each of the first erase voltage generation circuit 54, the second erase voltage generation circuit 55, and the scan voltage generation circuit 56, the sub-voltage input to each is adjusted to adjust the first erase voltage Vset, the second erase voltage Ve, and the scan. A process of generating the voltage Vscan and outputting it to the PDP 40 is executed.
Here, in the present embodiment, whether or not the first erasure voltage generation circuit 54, the second erasure voltage generation circuit 55, and the scan voltage generation circuit 56 are activated to execute the generation and output processing of each power supply voltage is determined. Control is performed using the presence or absence of the output voltage of the sustain voltage generation circuit 52.

As shown in FIG. 2, the output side of the sustain voltage generating circuit 52 is connected to each of the first erase voltage generating circuit 54, the second erase voltage generating circuit 55, and the scan voltage generating circuit 56, and the switch circuit SW The power supply voltage (SW power supply) can be supplied.
FIG. 4 shows the switch circuit SW provided in the first erase voltage generation circuit 54. Such a switch circuit SW is also provided in the second erase voltage generation circuit 55 and the scan voltage generation circuit 56, respectively, and the configuration and operation thereof are common.

As shown in the figure, the switch circuit SW is mainly constituted by a transistor Tr1, and the SW power generated by dividing the output voltage from the sustain voltage generation circuit 52 is input to the collector. A voltage level of the SW power supply can be about 15V.
On the other hand, a control signal of about 5 V output from the microcomputer 60 at a predetermined timing is input to the base of the transistor Tr1. The control signal is output from the microcomputer 60 to each switch circuit SW of each circuit of the first erase voltage generation circuit 54, the second erase voltage generation circuit 55, and the scan voltage generation circuit 56 at a specific timing based on the above sequence. Each circuit basically starts when a control signal is input, and generates and outputs a corresponding power supply voltage.

  Here, the switch circuit SW is configured such that a current flows between the collector and the emitter when the control signal is input in a state where the SW power is supplied. The first erase voltage generation circuit 54 (the same applies to the second erase voltage generation circuit 55 and the scan voltage generation circuit 56) is activated when the current (SW signal) flowing in this manner is detected, and the first erase voltage generation circuit 54 is activated. Generation and output processing of the voltage Vset (second erase voltage Ve, scan voltage Vscan) is executed.

  That is, each of the first erase voltage generation circuit 54, the second erase voltage generation circuit 55, and the scan voltage generation circuit 56 outputs the SW power to the switch circuit SW when the sustain voltage Vsus is output from the sustain voltage generation circuit 52. Is supplied and the control signal is input to the switch circuit at a specific timing from the microcomputer 60.

Generation processing of the first erase voltage Vset, the second erase voltage Ve, and the scan voltage Vscan in each circuit of the first erase voltage generation circuit 54, the second erase voltage generation circuit 55, and the scan voltage generation circuit 56 performed in the present embodiment The main processing is stabilization processing for the input sub voltages Vsub1 to Vsub3.
FIG. 5 shows a stabilization circuit 54 a included in the first erase voltage generation circuit 54. The second erase voltage generation circuit 55 and the scan voltage generation circuit 56 are also provided with the same stabilization circuit, and a voltage stabilization process as described below is executed.

The stabilization circuit 54a is a so-called shunt regulation type stabilization circuit.
The sub-voltage Vsub1 of about 175 V supplied from the address voltage generation circuit 53 is input to the circuit. At this time, the stabilization circuit 54a divides the output voltage by R1 and R2, and adjusts the current flowing through the transistor Tr2 so that the potential at the point A becomes 2,5V which is the reference voltage. That is, when the input voltage rises, the output voltage rises accordingly, and the potential at point A also rises. Since the error amplifier 54a1 amplifies the difference between the potential at the point A and the reference voltage, when the output voltage rises, the output of the error amplifier 54a1 also rises, and the current flowing through the transistor Tr2 increases. As a result, the voltage drop on the input side increases and the output voltage rise can be suppressed. The error amplifier 54a1 and the transistor Tr2 constitute a shunt regulator.

  Further, a smoothing capacitor C1 is provided on the output side of the stabilization circuit 54a. With this configuration, the first erase voltage generation circuit 54 stabilizes the sub-voltage Vsub1, which is about 175V, but the voltage level may be unstable, and supplies the stable DC voltage to the PDP 40 as the first erase voltage Vset. It becomes possible to output. Note that a photocoupler may be provided in the circuit such as between the error amplifier 54a1 and the transistor Tr2, if necessary, so that the PDP side and the input side are insulated.

(3) Summary As described above, according to the present invention, each of the first erase voltage generation circuit 54, the second erase voltage generation circuit 55, and the scan voltage generation circuit 56 generates an address voltage and outputs it to the PDP 40. The first erase voltage Vset based on each of the sub-voltages on the precondition that the sub-voltage is supplied from the voltage generation circuit 53 and the sustain voltage generation circuit 52 is activated to output the sustain voltage Vsus. Generation and output processing of each power supply voltage called the second erase voltage Ve and the scan voltage Vscan can be executed.

  That is, as long as the address voltage generation circuit 53 and the sustain voltage generation circuit 52 are not activated, the first erasure voltage generation circuit 54, the second erasure voltage generation circuit 55, and the scan voltage generation circuit 56 have the corresponding power supply voltages. It can never be generated and output. Therefore, when the microcomputer 60 malfunctions and the control signal is issued in the order and timing ignoring the above sequence, for example, before the microcomputer 60 activates the address voltage generation circuit 53 and the sustain voltage generation circuit 52, Even if the control signal is output to the first erase voltage generation circuit 54, the second erase voltage generation circuit 55, and the scan voltage generation circuit 56, the first erase voltage generation circuit 54, 2 Since each circuit of the erase voltage generation circuit 55 and the scan voltage generation circuit 56 does not start, an overload or failure of the PDP that may occur when various power supply voltages are input to the PDP 40 in an order different from the original order Can be eliminated.

The block diagram which showed schematic structure of the plasma television concerning this invention. The block diagram which showed a part of power supply circuit. The circuit diagram which showed a part of power supply circuit centering on the address voltage generation circuit. The figure which showed the switch circuit. The circuit diagram which showed the stabilization circuit. The block diagram which showed a part of conventional power supply circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Tuner circuit 20 ... Video processing circuit 30 ... Panel drive circuit 40 ... PDP
DESCRIPTION OF SYMBOLS 50 ... Power supply circuit 51 ... Rectification circuit 52 ... Sustain voltage generation circuit 53 ... Address voltage generation circuit 53a ... Transformer 54 ... 1st erasure voltage generation circuit 54a ... Stabilization circuit 54a1 ... Error amplifier 55 ... 2nd erasure voltage generation circuit 56 ... Scan voltage generation circuit 60 ... Microcomputer 100 ... Plasma television

Claims (6)

In a plasma television having a power supply circuit that generates a plurality of power supply voltages including at least an address voltage and a sustain voltage, and outputs the generated power supply voltage to the plasma display panel to drive the plasma display panel.
A rectifier circuit that inputs an AC voltage and generates a DC voltage;
The DC voltage is input to the primary winding of the transformer, an address voltage of a predetermined voltage level is generated in the secondary winding and output to the plasma display panel. In the secondary winding, An address voltage generation unit for deriving a plurality of sub-voltages having different voltage levels from conductive wires having different winding positions, and outputting each sub-voltage to the outside
A sustain voltage generator that inputs the DC voltage to the primary winding of the transformer, generates a sustain voltage at a predetermined voltage level in the secondary winding, and outputs the sustain voltage to the plasma display panel;
A scan voltage output unit that inputs any one of the plurality of sub voltages and adjusts the sub voltage to a predetermined voltage level to generate a scan voltage and output the scan voltage to the plasma display panel;
A first erase voltage output unit configured to input any one of the plurality of sub voltages and adjust the sub voltage to a predetermined voltage level to generate a first erase voltage and output the first erase voltage to the plasma display panel;
A second erase voltage output unit that inputs one of the plurality of sub-voltages and adjusts the sub-voltage to a predetermined voltage level to generate a second erase voltage and output the second erase voltage to the plasma display panel;
Each switch circuit that is provided on the output side of the sustain voltage generator and activates the scan voltage output unit, the first erase voltage output unit, and the second erase voltage output unit by dividing the output sustain voltage. Switch circuit power supply unit that generates the power supply voltage of the power supply and activates the scan voltage output unit, the first erase voltage output unit, and the second erase voltage output unit by supplying the generated power supply voltage to each switch circuit And
Further, the scan voltage output unit, the first erase voltage output unit, and the second erase voltage output unit stabilize the output voltage by a stabilization circuit using a shunt regulator when adjusting and outputting the sub voltage. A plasma television characterized by In a power supply circuit that generates a plurality of power supply voltages including at least an address voltage and a sustain voltage, and outputs the generated power supply voltage to the plasma display panel to drive the plasma display panel.
A rectifier circuit that inputs an AC voltage and generates a DC voltage;
The DC voltage is input to the primary winding of the transformer to generate an address voltage and a sustain voltage at a predetermined voltage level in the secondary winding, and the generated address voltage and sustain voltage are used as the plasma display. A driving voltage generation unit that outputs to the panel, derives a plurality of sub-voltages having different voltage levels from the conducting wires having different winding positions in the secondary winding, and outputs each sub-voltage to the outside;
A plurality of sub-voltage adjustment output units that input the plurality of sub-voltages to each other, adjust the input sub-voltages to a predetermined voltage level, and output the sub-voltages to the plasma display panel;
The power supply voltage of the switch circuit that activates the plurality of sub voltage adjustment output units is generated from either the address voltage or the sustain voltage, and the generated power supply voltage is supplied to the switch circuit to output each sub voltage adjustment output. A switch circuit power supply unit for starting the unit,
A power supply circuit comprising:   The drive voltage generation unit includes an address voltage generation unit that generates and outputs an address voltage each having a transformer, and a sustain voltage generation unit that generates and outputs a sustain voltage. The address voltage generation unit includes the transformer. The power supply circuit according to claim 2, wherein the plurality of sub-voltages are derived from conductive wires having different winding positions in the secondary winding.   The switch circuit power supply unit is provided on the output side of the sustain voltage generation unit, and obtains a power supply voltage to the switch circuit at a predetermined voltage level by dividing the output sustain voltage. The power supply circuit according to claim 3.   The plurality of sub voltage adjustment output units adjust the sub voltage to generate and output a scan voltage, and the first erase voltage adjusts the sub voltage to generate and output a first erase voltage. 5. The power supply circuit according to claim 2, comprising: an output unit; and a second erase voltage output unit that generates and outputs a second erase voltage by adjusting the sub-voltage.   6. The sub-voltage adjustment output unit stabilizes the output voltage by a stabilization circuit using a shunt regulator when adjusting and outputting the input sub-voltage. The power circuit according to.

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