JP3113486B2 - CPU system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CPU system,
More specifically, a non-volatile memory (EEPRO) with a limited number of times of writing for holding backup of system startup information
M). Today, all electronic devices include a CPU in a control unit, and the CPU starts up a system (device) to a predetermined function according to predetermined startup information after a power-on reset or a reset by an operation or a program. Such startup information may be stored in a ROM if it is fixed from the time of manufacture. For example, in a mobile radio telephone (mobile device), the startup information includes an equipment number, a telephone number, and various other information. Control data and the like are included, and the data changes during operation of the mobile device.

Therefore, it is necessary to hold the start-up information as a backup. As a means for this, a non-volatile memory (EEPRO) with a smaller number of writes and a limited number of times of writing is conventionally available.
M) is often used, but when the number of times of writing reaches the limit, the mobile device itself becomes unusable, so how to extend the use of the nonvolatile memory is an important issue.

[0003]

2. Description of the Related Art Conventionally, when a main power supply is turned off, a battery is backed up for a predetermined time, and the start-up information is unconditionally saved in a non-volatile memory using this time.

[0004]

SUMMARY OF THE INVENTION However, the EEPROM
A non-volatile memory such as the above requires much time (for example, 10 mS per byte) for data writing processing as compared with a RAM. For this reason, the conventional device is inconvenient and the backup battery is quickly consumed. Power supply OF
Since the number of times of writing in the non-volatile memory increases each time the
The writing limit (for example, tens of thousands of times) is reached before the age passes, and the life of the conventional device is sometimes limited by this.

SUMMARY OF THE INVENTION An object of the present invention is to provide a nonvolatile memory for backing up system startup information which has a long life.
It is to provide a PU system.

[0006]

The above-mentioned problem is solved by the structure shown in FIG. That is, the CPU system of the present invention
A CPU 1 for performing main control of the system, a non-volatile memory 2 for backing up system startup information, and a volatile for storing the startup information of the non-volatile memory 2 and updating its contents as necessary. Memory 3, a backup power supply 32 for backing up power supply to the system for a predetermined time when the main power supply 31 of the system is cut off, and a cutoff detection circuit 35 for generating a first interrupt to the CPU 1 by detecting the cutoff of the main power supply. The CPU 1 compares the start-up information of the nonvolatile memory 2 and the start-up information of the volatile memory 3 in the first interrupt processing, and stores the start-up information of the volatile memory 3 only when there is a mismatch. This is to write in the memory 2.

[0007]

When the power of the system is turned on, the CPU 1 starts up the system with the startup information of the nonvolatile memory 2 and loads the startup information of the nonvolatile memory 2 into the volatile memory 3. Alternatively, the startup information of the non-volatile memory 2 is loaded into the volatile memory 3 and the system is started using the startup information of the volatile memory 3. In any case, by accessing the volatile memory 3 during operation, the startup information can be read and written (updated) at high speed.

When the main power supply 31 of the system is turned off, the backup power supply 32 backs up power supply to the system for a predetermined time. At the same time, the disconnection detection circuit 35 generates a first interrupt to the CPU 1 by detecting the disconnection of the main power supply. Then, in the first interrupt processing, the CPU 1 compares the activation information of the nonvolatile memory 2 and the activation information of the volatile memory 3 and, when there is a mismatch, interprets the activation information of the volatile memory 3 as the nonvolatile memory. Write to 2.

Therefore, in practice, the start-up information of the volatile memory 3 is often not updated during the operation of the system. In such a case, writing to the non-volatile memory 2 is not performed. long lasting. Preferably, an interrupt generation circuit 10 that generates a second interrupt to the CPU 1 by a reset signal generated by an operation or a program, and the interrupt caused by the reset signal by the CPU 1 in the second interrupt processing. a first storage means 3 ₃ is set to a specific information indicating that the delay circuit delays a predetermined time the input to CPU1 of the reset signal 12
The CPU 1 operates at the time of starting up the system.
With identifying the content of the storage unit 3 _3, if the contents of said specific information launch system startup information in the volatile memory 3, the nonvolatile memory 2 otherwise
Start the system with the startup information.

Since the startup information of the volatile memory 3 is not destroyed at the time of startup other than when the main power is turned off, even if the contents of the volatile memory 3 have been updated, it is not necessary to save the updated content to the nonvolatile memory 2. Absent. Accordingly, even in such a case, writing to the nonvolatile memory 2 is not performed, and the nonvolatile memory 2 lasts longer. Also preferably, a second storage means 14 which is set / reset by a power-on reset signal and reset / set by a reset signal generated by an operation or a program, is provided.
Reference numeral 1 denotes the contents of the second storage means 14 when the system is started, and when the contents are set / reset, the system is started based on the start-up information of the nonvolatile memory 2; The system is started based on the startup information of the volatile memory 3.

Therefore, in the same manner as described above, the nonvolatile memory 2
And the CPU system can be realized with simpler circuits and control. Also preferably, the non-volatile memory 2 to a plurality of memory blocks 2 ₁ to 2 _n capable of storing up information up the respective write count launch information of one memory block F has exceeded a predetermined value Thus, writing to the next memory block is performed.
Therefore, the apparent life of the nonvolatile memory 2 is significantly extended.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments according to the present invention will be described below in detail with reference to the accompanying drawings. Note that the same reference numerals indicate the same or corresponding parts throughout the drawings. FIG. 2 shows a CPU according to the embodiment.
FIG. 1 is a block diagram of an application system. The CPU application system includes a control unit 100 including a CPU, a function unit 200 that implements functions unique to the device, and a power supply unit 300.

In the control unit 100, reference numeral 1 denotes a CPU for performing main control of the system, and 2 denotes a backup memory (BME) composed of a nonvolatile memory for limiting the number of times of writing, for example, an EEPROM for holding backup of system startup information.
M) 2 _{1 to} 2 _n are a use flag UF for holding an unused / used / used state of use, and a write counter CTR for counting the number of times of writing to this area and holding it.
And a storage area for startup information BDAT. 3 is a data memory comprising a volatile memory such as a RAM (DMEM), 3 ₁ launched information (AD
AT), 3 ₂ register pointer to the memory block _{2 1 ~2 n (P),} 3 3 holds the reset factor CR
A EG (corresponding to the first memory means 3 _3).

Further, reference numeral 4 denotes a program memory (PME) comprising a ROM storing the control programs of FIGS.
M), the common bus is 5 CPU 1, a power-on reset circuit 6, 6 ₁ Schmitt trigger circuit (ST), 7 a manual reset button, 8 inverter circuit (I),
9 is a pulse generator (P) that generates a manual reset pulse MRP having a predetermined pulse width at the fall of the input.
G), 10 is an OR gate circuit O (corresponding to the interrupt generation circuit 10), 11 is a program that decodes a reset command (program reset) of the CPU 1 and outputs a program reset pulse P
A bus decoder (BD) for generating RP, 12 is a delay circuit (DL), and 13 is a NOR gate circuit (NO).

In the functional unit 200, reference numeral 21 denotes an extension bus of the CPU 1, and reference numeral 22 denotes a functional circuit (FC) for realizing functions of a mobile communication device or the like. Further, in the power supply unit 300, 31 is a main power supply composed of a battery, 32 is a backup power supply composed of the same battery, and 33 is a power supply O.
An N / OFF switch; 34, a switch circuit composed of a semiconductor switch element or a relay;
It is.

FIG. 3 is an operation timing chart of the CPU application system of the embodiment. Hereinafter, the operation will be described with reference to FIG. FIG. 3A shows a timing chart when a reset signal is generated during operation of the system. When the reset button 7 is pressed and released, a manual reset pulse MRP (= reset pulse RP) is generated in synchronization with the release. Alternatively, when the CPU 1 sends a reset command to the common bus 5, a program reset pulse PRP (= reset pulse RP) is generated in synchronization with this. The reset pulse RP is input to the second interrupt input terminal I ₂ of the CPU 1, the falling of the reset pulse RP CPU 1 executes the reset factor recording process described below.

On the other hand, the delay circuit 12 has a delay time T ₁ longer than the completion of the processing, and when the time T ₁ elapses, a delay reset pulse RPD is generated, whereby the CPU 1 is actually reset. . Then, when the delayed reset pulse RPD disappears, a start-up process of a system described later starting from a predetermined address of the program memory 4 is executed.

FIG. 3B shows the state of the main power supply V during the operation of the system.
4 shows a timing chart in the case where is disconnected.
When the power ON / OFF switch 33 is turned off, the main power supply V drops rapidly, and upon detecting this, the Schmitt trigger circuit 35 generates a power interruption at the first interrupt terminal I ₁ of the CPU 1. On the other hand, the transistor Q is conducting a while for the accumulated charge the capacitor C _2, thereby the switch circuit 34 is kept ON, the continued backup power V'is supplied from the backup power supply 32 in the system. During this time, the CPU 1 executes the below-described main power supply interruption process by the fall of the main power supply interruption signal. Time T ₂ the transistor Q is conducting has a greater time than execution completion of the main power-off process, during which CPU1
Ends the main power cutoff process. Then, when the time T ₂ has elapsed, the transistor Q is turned off, whereby the power supply of the backup power supply V ′ is stopped, and the system turns off the power supply OF.
The state becomes the F state.

[0019] Then, when the power ON / OFF switch 33 to ON, the main power source V is rapidly charged capacitor C ₂ through the diode D _4, rapidly to ON transistor Q. The main power source V is powered on the switch circuit 34 via the diode D _2, and switch circuit 34
Is turned on, the main power supply V is supplied to the system. Incidentally, the diode D ₃ in this state is reverse biased, no depletion of the backup power supply 32 has.

When the main power supply V is supplied to the system, the power-on reset circuit 6 outputs a power-on reset signal PWR.
Occurs. As a result, the power-on reset of the CPU 1 is performed, and when the power-on reset signal PWR is lost, the CPU 1 executes a system start-up process described later starting from a predetermined address of the program memory 4. FIG. 4 is a flowchart of the CPU application system of the embodiment. In addition,
In this example, the case where the backup memory 2 has one memory block will be described.

When a reset signal RP generated by an operation or a program is generated during operation of the system, an interrupt is input to a reset factor recording process. In such a restart process based on the reset signal RP, even if the start information ADAT in the data memory 3 has been updated, it can be used at the time of restart.
You do not need to evacuate to this, and you will know this when restarting. That is, in step S1, information (for example, reference symbol "G") indicating that the reset factor has been generated by an operation or a program while the CPU is operating is set in the reset factor register CREG, and in step S2, the CPU 1 is set to the idle state. Become.

When the main power supply interruption is detected during the operation of the system, an interrupt is inputted to the main power supply interruption processing. In step S11, "0" is set in the reset factor register CREG.
In this embodiment, it is assumed that the contents of the data memory 3 composed of the volatile RAM become “0” due to the power-off, so that the processing in step S11 is not necessarily required. In step S12, the startup information ADA of the data memory 3
T is compared with the start-up information BDAT of the backup memory 2, and in step S13, it is determined whether or not all match. If they do not all match, the start-up information ADAT of the data memory 3 is stored in the backup memory 2 in step S14.
To the startup information BDAT. If all match, the process of step S14 is skipped. Step S
At 15, CPU 1 enters an idle state and waits for the backup power supply to be turned off.

After the reset signal RS is input, the CPU 1 executes a common start-up process. Step S
At 21, the content of the reset cause register CREG is "G".
It is determined whether or not. If it is not “G” (G is discarded), the power has been turned off, so the startup information BDAT of the backup memory 2 is loaded into the startup information ADAT of the data memory 3 in step S22. Thereafter, the data memory 3 enables high-speed reading and high-speed writing (updating). In the case of "G", the data memory 3
Since the startup information ADAT is not destroyed, the process of step S22 is skipped. In step S23, the system is started with the start information ADAT in the data memory 3. In step S24, a function control specific to the CPU system is performed, and when the startup information ADAT needs to be updated, the update is performed as appropriate.

FIG. 5 is a flowchart of a main power-off process according to another embodiment. In this example, the backup memory 2 includes a plurality of memory blocks 2 ₁ to 2 _n , and is a process for extending the life of the backup memory 2 by using them sequentially. The processing in steps S31 to S33 is the same as the processing in steps S11 to S13 in FIG. If not all match in the determination in step S33,
In step S34, it is determined whether or not the content CTR (P) of the write counter indicated by the current pointer P is greater than the write limit number m. If CTR (P)> m, step S
Proceeding to 39, the startup information ADAT of the data memory 3 is saved to the startup information BDAT (P) of the memory block indicated by the pointer P in the backup memory 2.

If CTR (P)> m, step S
At 35, the content of the use flag pointed to by the pointer P is rewritten from "in use" to "used", and at step S36, the pointer P is updated to the next memory block. Step S37
In step S41, it is determined whether or not the pointer P has exceeded the maximum block number n. If the pointer P has exceeded the maximum block number n, the buzzer (not shown) of the functional section 200 Generate an alarm on the alarm lamp.

If P> n is not satisfied, the use flag UF (P) of the updated memory block is rewritten from "unused" to "in use" in step S38, and the start-up information ADAT of the data memory 3 is changed in step S39. Is saved in the startup information BDAT (P) of the backup memory 2. In step S40, the content of the write counter CTR (P) is incremented by +
Do one.

In the case where the determinations in step S33 are all coincident, the process enters the idle state in step S42 without doing anything. Therefore, m × n times of writing can actually be performed using an EEPROM with the number of times of writing = m, and the life of the device is significantly extended. FIG. 6 is a block diagram of a CPU application system according to another embodiment. In FIG. 6, reference numeral 14 denotes a flip-flop circuit FF (corresponding to the second storage means 14) provided in place of the reset factor register CREG.

The flip-flop circuit 14 is set at the fall of the power-on reset signal PWR and is reset by a reset signal RP by operation or program. Therefore, when starting up the system,
U1 is an output signal C of the flip-flop circuit 14 via the common bus 5 in the determination processing of step S21 of FIG.
By inspecting the
It is possible to reliably determine whether or not the startup is due to the reset signal during operation.

Therefore, according to this embodiment, the reset factor register CREG shown in FIG. 2 is not required, and the reset factor recording process for controlling the reset factor register CREG is not required. I
Neither ₂ nor the delay circuit 12 for completing the processing is required. Therefore, the circuit and processing are simplified in this embodiment.

In the above embodiment, the start-up information is used only when the system is started up. However, in view of the fact that telephone numbers and other parameter information are included, the start-up information of the present invention is also used when the equipment is operated. It is clear that reference is made. Further, the reset source register CREG3 ₃ R
Although provided in AM3, it is not limited to this. A register that is not reset by the reset signal RS in the CPU 1 may be used, or a special register may be connected to the common bus 5. When a special register is connected to the common bus 5, if the power is always supplied to this by the backup power supply 32, the set information is not lost.

Although the preferred embodiment of the present invention has been described, it goes without saying that various changes in the configuration and control can be made without departing from the spirit of the present invention.

[0032]

As described above, according to the present invention, the CPU
Reference numeral 1 denotes a comparison between the startup information of the nonvolatile memory 2 and the start-up information of the volatile memory 3 in the first interrupt processing based on the detection of the interruption of the main power supply.
Is written to the nonvolatile memory 2, the number of times of writing to the nonvolatile memory 2 with the limited number of times of writing can be significantly reduced, and the life of the device is significantly extended.

Further, since the nonvolatile memory 2 is formed into a plurality of memory blocks 2 ₁ to 2 _n and these are sequentially used, the apparent write limit of the nonvolatile memory 2 is greatly increased.

[Brief description of the drawings]

FIG. 1 is a diagram showing the basic configuration of the present invention.

FIG. 2 is a block diagram of a CPU application system according to the embodiment;

FIG. 3 is an operation timing chart of the CPU application system of the embodiment.

FIG. 4 is a flowchart of the CPU application system of the embodiment.

FIG. 5 is a flowchart of a process according to another embodiment.

FIG. 6 is a block diagram of a CPU application system according to another embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 Non-volatile memory 3 Volatile memory 31 Main power supply 32 Backup power supply 35 Disconnection detection circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G06F 1/30 G06F 1/00 370 G06F 12/16 340 G11C 16/02

Claims (4)

(57) [Claims] A CPU for performing main control of the system;
A non-volatile memory (2) for backing up system startup information; a volatile memory for storing the startup information of the non-volatile memory (2) and updating its contents as needed by the CPU (1). Power supply (32) for backing up the power supply to the system for a predetermined time when the main power supply (31) of the system is cut off
And a disconnection detection circuit (35) for generating a first interrupt to the CPU (1) upon detection of the disconnection of the main power supply. CPU which compares the startup information of the volatile memory (2) with the startup information of the volatile memory (3) and writes the startup information of the volatile memory (3) to the nonvolatile memory (2) only when there is a mismatch. system. 2. An interrupt generating circuit (10) for generating a second interrupt to a CPU (1) by a reset signal generated by an operation or a program, and a CPU (1) in said second interrupt processing. ) by a first storage means該割write is set specific information to the effect that due to the reset signal (3 _3), a delay circuit for a predetermined time delay the input to the CPU (1) of the reset signal ( 12) and provided with, CPU (1) along with identifying the contents of raising the first storage unit when the system (3 _3), if the contents of the specific information of the volatile memory (3) 2. The CPU system according to claim 1, wherein the system is started with the start information, and otherwise, the system is started with the start information of the nonvolatile memory. 3. A method of setting / resetting a power-on reset signal.
A second storage means (14) which is reset and reset / set by a reset signal generated by an operation or a program, wherein the CPU (1) stores the second storage means (14) at system start-up; The contents are discriminated, and if the contents are set / reset, the system is started with the start-up information of the nonvolatile memory (2). If the contents are reset / set, the system is started with the start-up information of the volatile memory (3). The CPU system according to claim 1, wherein the CPU system is started up. 4. A nonvolatile memory (2) comprising a plurality of memory blocks (2 ₁ to 2 _n ) each capable of storing start-up information.
2. The CP according to claim 1, wherein when the number of times of starting information writing to one memory block exceeds a predetermined value, writing to the next memory block is performed.
U system.