JP3112144U - Self-excited inverter circuit and LCD TV - Google Patents

Abstract

In a self-excited inverter circuit, an object of the present invention is to suppress a simultaneous on operation associated with a peak current generated at the time of alternate energization switching of both FETs and obtain a stable lamp lighting state.
When a pulse voltage is alternately applied from a drive winding 19c to both gates of first and second FETs 18a and 18b, a gate potential is predetermined by the first and second Zener diodes 18c and 18d. The on-time T is shortened by clamping to the potential.

Description

  The present invention provides a self-excited inverter circuit in which a pulse voltage is applied to the gates of a pair of switching elements via a drive winding to alternately turn on and off the pair of switching elements, and the self-excited inverter circuit is for dimming It is related with the liquid crystal television prepared.

  Conventionally, a self-excited inverter circuit has been widely used as a device for dimming the lighting state of a lamp. In this self-excited inverter circuit, in general, the frequency is determined by an inverter transformer and a resonant capacitor, and dimming is performed. However, in the method in which such a frequency is determined by the inverter transformer and the resonant capacitor, the frequency is changed by changing the strength of the resonance, so that delicate adjustment of the frequency has been difficult.

  Therefore, the following conventional techniques are known as conventional techniques for facilitating such frequency adjustment.

  In Japanese Patent Laid-Open No. 2001-157461 (Patent Document 1), first and second switching elements (FETs) are connected in series, and first and second FETs are alternately turned on and off by self-excited driving means. An inverter circuit for supplying a high-frequency current to a load circuit including an LC resonance circuit by turning on and off and means for feeding back to the input side of the inverter circuit are provided, and the on-duty of the second FET is reduced.

  In Japanese Patent Laid-Open No. 2002-299096 (Patent Document 2), a pulse voltage is applied to the gates of a pair of switching elements (FETs) via two secondary windings of an inductor to alternately turn on and off the pair of FETs. A self-excited inverter is provided, and a variable zener diode that changes the gate voltage is provided between the gate and source of any of the pair of FETs.

  According to the self-excited inverter circuit in which the FETs are provided as a pair of switching elements as in the above-described conventional technologies, the frequency is easily adjusted accurately by controlling the duty of the pulse voltage applied to the gate of the FET. be able to.

  However, in the method of dimming the lighting state of the lamp by the self-excited inverter circuit using FETs as a pair of switching elements as in each of the prior arts described above, the current flows between the drain and the source when switching between the FETs. It is inevitable that a steep peak current occurs in the current.

  That is, when the gate voltage of the first FET is turned off as shown in the voltage waveform of FIG. 5A and when the gate voltage of the second FET is turned on as shown in the voltage waveform of FIG. The current flowing between the drain and source of the FET of 1 causes a steep peak waveform Pi as shown in the current waveform of (c), and the current flows for the time T1 immediately after the gate voltage is turned off. On the other hand, when the gate voltage of the second FET is turned on, a current already flows between the drain and source of the second FET during time T1, and at time T1, both FETs overlap. Simultaneous on operation will occur. As a result, there is a problem that the lighting state of the lamp becomes unstable.

  In Patent Document 1 described above, a Zener diode is connected between the gate and source of each FET, but this is only for clipping the gate drive voltage to a predetermined voltage.

  Also in Patent Document 2, a Zener diode is connected to the gate of each FET in order to protect the gate voltage of the FET from exceeding the rating.

  Therefore, neither of the above-mentioned patent documents 1 and 2 can solve the above-described simultaneous ON operation at the time of switching between both FETs.

  The present invention has been made in view of the above problems. In a self-excited inverter circuit using a pair of FETs, which can easily adjust the frequency easily by controlling the duty of the pulse voltage applied to the gate. , A self-excited inverter circuit that suppresses simultaneous on-operation due to the peak current generated at the time of alternating energization switching of both FETs and obtains a stable lamp lighting state, and a liquid crystal provided with the self-excited inverter circuit for dimming The purpose is to provide television.

  In order to solve the above problem, the device according to claim 1 applies a pulse voltage that is duty controlled to the gates of a pair of switching elements via a drive winding to alternately turn on and off the pair of switching elements. A self-excited inverter circuit for dimming, wherein the self-excited inverter circuit includes a pair of FETs as the pair of switching elements and the pair of FETs on the primary side. And a transformer in which a lamp is disposed on the secondary side. In the first FET constituting the pair of FETs, a first Zener diode is provided between the gate connected to the power supply and the ground and the drain. The first main coil is connected between the power supplies, and the ground is connected to the source. On the other hand, in the second FET constituting the pair of FETs, the supply power A second Zener diode is connected between the gate and the ground connected to each other, a second main coil is connected between the drain and the power supply, and a ground is connected to the source. The drive winding is connected to the first FET. When the pulse voltage is alternately applied from the drive winding to both gates of the first and second FETs, the first and second Zener diodes are provided between the gates of the first FET and the second FET. A configuration in which the gate potential is clamped to a predetermined potential to shorten the on-time, and the simultaneous on operation associated with the peak current generated when the first FET and the second FET are alternately switched from on to off is suppressed. It is said.

  According to the device of the first aspect configured as described above, when the pulse voltage is alternately applied from the drive winding to the gates of the first and second FETs, the first and second Zeners are applied. The gate potential is clamped to a predetermined potential by the diode to shorten the on time. As a result, the simultaneous on operation due to the peak current generated when the first FET and the second FET are alternately switched from on to off is suppressed.

  The invention described in claim 2 is a self-excited inverter circuit that applies a pulse voltage that is duty controlled via a drive winding to the gates of a pair of switching elements to alternately turn on and off the pair of switching elements. The self-excited inverter circuit includes the pair of switching elements that are voltage-driven and a transformer in which the pair of switching elements are disposed on the primary side and a lamp is disposed on the secondary side. In the first switching element constituting the switching element, a first gate voltage clamping means is provided between the gate connected to the power supply and the ground, and a first main coil is provided between the drain and the power supply as a source. Are connected to the power supply in the second switching elements constituting the pair of FETs, while the grounds are connected to each other. A second gate voltage clamp means is connected between the gate and the ground, a second main coil is connected between the drain and the power supply, and a ground is connected to the source, and the drive winding is connected to the first switching element. And when the pulse voltage is alternately applied to both gates of the first and second switching elements from the drive winding, the first and second gates are provided between the gates of the first switching element and the second switching element. The voltage clamping means clamps the gate potential to a predetermined potential to shorten the on-time, and simultaneously with the peak current generated when the first switching element and the second switching element are alternately switched from on to off. The on-operation is suppressed.

  According to the device of the second aspect configured as described above, when the pulse voltage is alternately applied from the drive winding to both gates of the first and second switching elements, the first and second The gate voltage is clamped to a predetermined potential by the gate voltage clamping means to shorten the on time. As a result, the simultaneous on operation due to the peak current that occurs when the first switching element and the second switching element are alternately switched from on to off is suppressed.

  The invention described in claim 3 is a self-excited inverter circuit that applies a pulse voltage that is duty controlled to the gates of a pair of switching elements via a drive winding to alternately turn on and off the pair of switching elements. The first and second switching elements are FETs, the first and second gate voltage clamping means are Zener diodes, and the self-excited inverter circuit is provided for dimming a liquid crystal television. When the pulse voltage is alternately applied from the winding to the gates of the first and second FETs, the gate potential is clamped to a predetermined potential by the first and second Zener diodes to shorten the on time. The simultaneous on operation due to the peak current generated when the first FET and the second FET are alternately switched from on to off is suppressed. It is set to.

  According to the invention described in claim 3 configured as described above, as in the case of claim 1, the pulse voltage is alternately applied to both gates of the first and second FETs from the drive winding. With the first and second Zener diodes, the gate potential is clamped to a predetermined potential to shorten the on time. As a result, the simultaneous on operation due to the peak current generated when the first FET and the second FET are alternately switched from on to off is suppressed.

  According to the first aspect of the present invention, the simultaneous on operation due to the peak current generated when the first FET and the second FET are alternately switched from on to off is suppressed, and a stable lamp can be turned on. A liquid crystal television provided with a self-excited inverter circuit for obtaining the state for dimming can be provided.

  According to the second aspect of the present invention, the simultaneous on operation due to the peak current generated when the first switching element and the second switching element are alternately switched from on to off is suppressed, and the stable lamp It is possible to provide a self-excited inverter circuit that obtains a lighting state.

  According to the third aspect of the present invention, the simultaneous on operation due to the peak current generated when the first FET and the second FET are alternately switched from on to off is suppressed, and the stable lamp can be turned on. A self-excited inverter circuit that obtains a state can be provided.

  Embodiments embodying the present invention will be described below.

(1) Configuration of the liquid crystal television device:
FIG. 1 is a block configuration diagram showing a configuration in an embodiment of a self-excited inverter circuit according to the present invention and a liquid crystal television provided with the self-excited inverter circuit for dimming.

  In FIG. 1, a liquid crystal television device 10 as a liquid crystal television is roughly composed of a tuner 11, a video signal processing circuit 12, a liquid crystal panel 13, a microcomputer 14, and a selector circuit 15. The video signal processing circuit 12 includes a digital signal processing circuit 12a and a liquid crystal driver circuit 12b therein, and a control circuit 12c and a microcomputer I / F 12d are connected via a bus 12e such as an IIC bus. A microcomputer 14 is connected to the microcomputer I / F, and the microcomputer 14 can control each circuit of the video signal processing circuit 12 via the microcomputer I / F 12d.

  Here, an operation panel 14a, a remote control I / F 14b, a ROM 14c, a RAM 14d, and a backlight drive circuit 14e are connected to the microcomputer 14, and the microcomputer 14 reads various control programs stored in advance in the ROM 14c, The RAM 14d is executed as a work area, and the control of each circuit described above is executed. A backlight unit 14e1 is connected to the backlight drive circuit 14e. Here, the resolution of the liquid crystal panel 13 is not particularly limited, and may be a resolution of 640 pixels * 480 pixels (VGA size) or a resolution of 1024 pixels * 768 pixels (XGA size). Also good. The backlight unit 14e1 connected to the backlight drive circuit 14e is disposed on the back surface of the liquid crystal panel 13, and light emitting elements substantially equivalent to the pixels of the liquid crystal panel 13 are arranged in a matrix. The light emitting element is driven by a backlight drive circuit 14e described later in detail based on the control of the microcomputer 14, and emits light with a predetermined light emission luminance.

  The tuner 11 is a tuner for analog television, and receives television broadcast radio waves with a connected antenna 11a. The tuner 11 outputs a television broadcast signal (composite video signal) as an analog video signal based on the received television broadcast radio wave. The liquid crystal television apparatus 10 also receives an external input terminal 15a for inputting an analog video signal (composite video signal) from the VTR as an external input terminal, and an analog video signal (composite video signal) from the LD player. And an external input terminal 15c for inputting an analog video signal (composite video signal) from the DVD player.

 The tuner 11 and the external input terminals 15a to 15c are connected to the selector circuit 15. The composite video signal (television broadcast signal) output from the tuner 11 and the composite video signal input from the external input terminal 15a and the external input. One composite video signal can be selected from the composite video signal input from the terminal 15b and the composite video signal input from the external input terminal 15c. This selection is performed by an operation using a remote controller that is input via an operation panel 14a connected to the microcomputer 14 and a remote controller I / F 14b. The composite video signal selected by the selector circuit 15 is sent to the video signal processing circuit 12. The sent composite video signal is input to the digital signal processing circuit 12 a inside the video signal processing circuit 12.

The digital signal processing circuit 12a includes an analog / digital conversion circuit 12a1, a Y / C separation circuit 12a2, a chroma decoder circuit 12a3, an image adjustment circuit 12a4, and a matrix circuit 12a5. In such a configuration, when the analog / digital conversion circuit 12a1 receives a composite video signal, a predetermined signal level range between a white level and a black level in the composite video signal is converted into a digital signal having a gradation corresponding to each signal level. Convert to Subsequent predetermined signal processing is executed based on this digital signal. The Y / C separation circuit 12a2 performs separation processing into a Y signal and a C signal based on this digital signal. The separated Y signal and C signal are input to the chroma decoder circuit 12a3 and subjected to predetermined signal processing. Later, it is output as a YUV signal.

 The image quality adjustment circuit 12a4 of the digital signal processing circuit 12a adjusts sharpness, color, and TINT for the YUV signal. The matrix circuit 12a5 performs an RGB matrix conversion process on the YUV signal whose image quality has been adjusted by the image quality adjustment circuit 12a4 to generate an RGB signal. The generated RGB signal is sent to the liquid crystal driver circuit 12b. The liquid crystal driver circuit 12b includes a pixel number conversion circuit 12b1, an image quality adjustment circuit 12b2, an output processing circuit 12b3, and a frame memory 12b4. The pixel number conversion circuit 12b1 receives the RGB signal generated by the digital signal processing circuit 12a, and performs an RGB signal for one screen displayed on the liquid crystal panel 13 while performing a scaling process on the RGB signal. Generate. Then, the RGB signal for one screen is stored in the frame memory 12b4.

 The image quality adjustment circuit 12b2 of the liquid crystal driver circuit 12b is subjected to scaling processing by the pixel number conversion circuit 12b1, and adjusts brightness, contrast, black balance, and white balance for the RGB signals stored in the frame memory 12b4. Do. The output processing circuit 12b3 performs gamma correction, dither processing, etc. on the RGB signal whose image quality has been adjusted by the image quality adjustment circuit 12b2, and adds a background signal, an OSD signal, a blanking signal, etc. To display the image.

(2) About the backlight drive circuit:
FIG. 2 shows the backlight drive circuit 14e having a self-excited inverter circuit 18 for driving the cold cathode tube 17 which is a light source of the backlight unit 14e1 as a lamp of the liquid crystal television device 10 to light.

  The AC adapter 14k generates and outputs a DC output V + stabilized to 12V from the commercial power supply 14l. The microcomputer 14 generates a positive output stabilized from the DC output V + to 5 V, and outputs the positive output to the IC unit 14 f of the backlight drive circuit 14 e.

  The backlight drive circuit 14e includes a self-excited inverter circuit 18 that lights a cold cathode tube (discharge tube) 17, a luminance control circuit 14g, a switching control circuit 14h, and a protection circuit 14j. Each of these circuits is appropriately configured including an IC section 14f and an external discrete element.

  The switching control circuit 14h generates and outputs a switching control output 14h1 based on duty control for driving the self-excited inverter circuit 18 in accordance with the signal output from the luminance control circuit 14g. The luminance control circuit 14g calculates the current detection signal 16a output from the current detection circuit 16, and outputs a control signal 14g1 to the switching control circuit 14h and the protection circuit 14j. The signal 14g1 is also set to 0 when the current detection signal 16a indicates that the current value is 0.

  The protection circuit 14j includes an internal latch circuit 14i. When the positive output voltage is changed from 0V to 5V and the IC unit 14f of the backlight drive circuit 14e shifts to the operating state, the latch circuit 14i Non-latching state. The latch circuit 14i in the non-latching state has a current detection signal 16a output from the current detection circuit 16 when the voltage detection signal 15a output from the voltage detection circuit 15 indicates an increase in voltage abnormality. In order to indicate 0 of the current, when the signal 14g1 indicates 0, the latch state is entered. Further, when the voltage of the positive output decreases, the latch state is entered.

  When the latch circuit 14i shifts to the latch state, the protection circuit 14j stops the operation of the switching control circuit 14h. The latch state of the latch circuit 14i is canceled when the voltage of the IC positive output is set to 0 V (or a value close to 0 V), but is not canceled by an external signal or the like.

  FIG. 3 shows a schematic circuit diagram of the self-excited inverter circuit 18.

  The self-excited inverter circuit 18 includes a pair of FETs 18a and 18b as a pair of switching elements, and the pair of FETs 18a and 18b on the primary side, and a cold light that serves as a light source of a backlight as a lamp on the secondary side. And a transformer 19 in which the cathode tube 17 is disposed.

  The pair of FETs includes a first FET 18a and a second FET 18b. In the first FET 18a, a first Zener diode 18c as a first gate voltage clamping means is provided between the gate connected to the power supply and the ground, and the first main coil 19a is provided between the drain and the power supply. However, the ground is connected to each source.

  On the other hand, in the second FET 18b, a second Zener diode 18d as second gate voltage clamping means is provided between the gate connected to the power supply and the ground, and a second main diode 18d is provided between the drain and the power supply. The coil 19b and the source are connected to the ground.

  The transformer 19 is provided with a drive winding 19c connected between the gate of the first FET 18a and the gate of the second FET 18b, and is input from the switching control circuit 14h via the drive winding 19c. The applied pulse voltage is alternately applied to both gates of the first and second FETs 18a and 18b.

  That is, at the time of start-up, a current flows through the drive winding 19c to the gate of the first FET 18a, and the FET 18a is turned on. Next, a current flows through the drive winding 19c so as to extract the gate voltage applied to the first FET 18a, and the FET 18a is turned off. Subsequently, a similar ON / OFF operation is performed in the second FET 18b, and a high-voltage sine wave is supplied to the secondary cold cathode tube 17.

(3) About operation:
In this embodiment, as described above, the first Zener diode 18c is connected between the gate of the first FET 18a and the ground, and the second Zener diode 18d is connected between the gate of the second FET 18b and the ground. , Each is provided. Accordingly, when both the zener diodes 18c and 18d are installed, the gate voltage is applied to both the zener diodes 18c and 18d when the pulse voltage is alternately applied from the drive winding 19c to both gates of the first and second FETs 18a and 18b. It is clamped (limited) to a predetermined potential Va set in advance.

  As a result, the gate voltages applied to both gates of the first and second FETs 18a and 18b have waveforms as shown in FIGS. 4 (a) and 4 (b), respectively. Accordingly, the current flowing between the drain and source of the first and second FETs 18a and 18b has a waveform as shown in FIG.

That is, by clamping the gate voltage applied to both gates of the first and second FETs 18a and 18b to a predetermined voltage by both the Zener diodes 18c and 18d, the on-time T of the FETs 18a and 18b is shortened. Will be. Therefore, by setting the clamp voltage value of the gate voltage so that the shortening amount of the ON time T is equal to or more than the time T1 in which the simultaneous ON operation is performed in the prior art of FIG. The peak current portion generated when switching from on to off, which has occurred in the current waveform flowing between the drain and source of both FETs, is eliminated, and the simultaneous on operation can be suppressed.
As a result, in the self-excited inverter circuit using a pair of FETs that can easily adjust the frequency accurately by duty-controlling the pulse voltage applied to the gate, it occurs at the time of alternating energization switching of both FETs. It is possible to provide a self-excited inverter circuit that suppresses the simultaneous ON operation associated with the peak current and obtains a stable lamp lighting state, and a liquid crystal television including the self-excited inverter circuit for dimming.

  In addition, this invention is not limited to the structure of a present Example, About the structure listed below, it can change suitably.

1. The specific circuit configuration of the self-excited inverter circuit described in this embodiment is merely an example, and the present invention is not limited to this. In short, what is necessary is just to have a configuration in which the gate voltage of the switching element is clamped at a predetermined voltage to shorten the ON time of the switching element.

2. The specific configuration of the liquid crystal television described in this embodiment is merely an example, and the present invention is not limited to this.
In short, any device may be used as long as it can provide a self-excited inverter circuit that clamps the gate voltage of the switching element with a predetermined voltage and shortens the ON time of the switching element.

3. In this embodiment, the liquid crystal television has been described as an example of a suitable device provided with a self-excited inverter circuit that clamps the gate voltage of the switching element at a predetermined voltage and shortens the on-time of the switching element. However, this is merely an example. However, the present invention is not limited to this. The present invention can be applied to various devices other than a liquid crystal television including a lamp that is controlled by a self-excited inverter circuit.

4). In this embodiment, the FET is described as an example of the pair of switching elements. However, the present invention is not limited to this, and other switching elements that are turned on / off by voltage control that can be clamped may be used.

5). Similarly, in this embodiment, an example in which a Zener diode is applied as the gate voltage clamping means has been described. However, the present invention is not limited to this, and other means capable of voltage clamping similar to the Zener diode are used. May be.

6). It goes without saying that the voltage value for clamping the gate voltage, that is, the amount of on-time reduction of the switching element can be appropriately set according to the situation such as the lamp characteristics.

  In the self-excited inverter circuit using a pair of FETs, which can easily adjust the frequency accurately by controlling the pulse voltage applied to the gate, the peak current generated when the two FETs are switched alternately. Provided are a self-excited inverter circuit that suppresses the accompanying simultaneous ON operation and obtains a stable lamp lighting state, and a liquid crystal television provided with the self-excited inverter circuit for dimming.

It is a schematic block diagram explaining Example 1 of the present invention. It is a schematic block diagram explaining Example 1 of the present invention. 1 is a schematic circuit diagram illustrating Example 1 of the present invention. It is a schematic wave form diagram explaining Example 1 of this invention. It is a schematic waveform diagram explaining the prior art with respect to this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Liquid crystal television apparatus as a liquid crystal television 17 ... Lamp 18 ... Self-excited inverter circuit 18a ... 1st FET as 1st switching element
18b ... Second FET as second switching element
18c: first Zener diode as first gate voltage clamping means 18d: second Zener diode as second gate voltage clamping means 19 ... transformer 19a ... first main coil 19b ... second main coil 19c … Drive winding T… On time

Claims (3)

A liquid crystal television equipped with a self-excited inverter circuit for dimming that applies a duty-controlled pulse voltage to a gate of a pair of switching elements via a drive winding to alternately turn on and off the pair of switching elements. And
The self-excited inverter circuit is
A pair of FETs as the pair of switching elements;
A transformer having a pair of FETs disposed on the primary side and a lamp disposed on the secondary side;
In the first FET constituting the pair of FETs, a first Zener diode is provided between the gate connected to the power supply and the ground, a first main coil is provided between the drain and the power supply, and a ground is provided at the source. While each is connected
In the second FET constituting the pair of FETs, a second Zener diode is provided between the gate connected to the power supply and the ground, a second main coil is provided between the drain and the power supply, and a ground is provided at the source. Are connected to each other,
The drive winding is provided between the gate of the first FET and the gate of the second FET;
When the pulse voltage is alternately applied from the drive winding to the gates of the first and second FETs, the gate potential is clamped to a predetermined potential by the first and second Zener diodes to shorten the on-time. And a simultaneous on operation associated with a peak current generated when the first FET and the second FET are alternately switched from on to off. A self-excited inverter circuit that applies a pulse voltage that is duty-controlled via a drive winding to the gates of a pair of switching elements to alternately turn on and off the pair of switching elements,
The self-excited inverter circuit is
The pair of switching elements that are voltage driven;
A transformer having a pair of switching elements disposed on the primary side and a lamp disposed on the secondary side;
In the first switching element constituting the pair of switching elements, a first gate voltage clamping means is provided between the gate connected to the power supply and the ground, and a first main coil is provided between the drain and the power supply. While the ground is connected to each source,
In the second switching element constituting the pair of FETs, a second gate voltage clamping means is provided between the gate connected to the power supply and the ground, and a second main coil is provided between the drain and the power supply. Is connected to the ground,
The drive winding is provided between the gate of the first switching element and the gate of the second switching element;
When the pulse voltage is alternately applied from the drive winding to the gates of the first and second switching elements, the gate potential is clamped to a predetermined potential by the first and second gate voltage clamping means. A self-excited inverter circuit characterized in that time is shortened and simultaneous on operation associated with a peak current generated at the time of alternate switching from on to off between the first switching element and the second switching element is suppressed. A self-excited inverter circuit that applies a pulse voltage that is duty-controlled via a drive winding to the gates of a pair of switching elements to alternately turn on and off the pair of switching elements,
The first and second switching elements are FETs;
The first and second gate voltage clamping means are Zener diodes;
The self-excited inverter circuit is provided for light control of a liquid crystal television,
When the pulse voltage is alternately applied from the drive winding to the gates of the first and second FETs, the gate potential is clamped to a predetermined potential by the first and second Zener diodes to shorten the on-time. And a self-excited inverter circuit that suppresses simultaneous on operation due to a peak current generated when the first FET and the second FET are alternately switched from on to off.

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