JP3104678B2 - Clock signal distribution design circuit, method therefor, and recording medium recording control program therefor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock signal distribution design circuit and method, and a recording medium on which a control program is recorded, and more particularly to a CAD (Computer A).
The present invention relates to a clock signal distribution design method in an LSI (Large Scale Integrated Circuit) layout design using an integrated design.

[0002]

2. Description of the Related Art Conventionally, in the layout design of an LSI using CAD, after circuit connection information is input, layout design is performed in the same manner as other signals without particularly distinguishing clock signal nets.

However, when the layout is performed by this method, the time required for the clock signal to reach the element to which the clock is input varies. When the arrival time of the clock signal to each element varies and the clock skew (difference in the arrival time of the clock signal) increases, the reliability of the design circuit is greatly reduced.

In order to avoid this, the arrangement positions of clock input elements and clock wiring paths are manually created. In addition, in order to avoid the arrangement of the elements and the creation of the wiring path, a method of distributing clock signals by a mesh method or a tree method is generally used.

In the mesh method, wiring is arranged around a chip in a grid pattern, a buffer cell is connected near the grid, and a clock signal is connected to a clock input element via the buffer cell. This method simplifies the configuration and reduces the number of buffer insertion stages from the clock top buffer to the clock input element.

On the other hand, in the tree system, as shown in FIG. 18, buffers 41 to 47 are connected in parallel for each stage to form a multistage structure, and a tree-shaped wiring path is taken for each buffer. This tree method is used for all clock input elements 51.
This is a technique for reducing clock skew by making the arrival times of clock signals to ５８58 theoretically the same. This method has an advantage that the design skew is smaller than the mesh method.

The above tree method is disclosed in
There is a method disclosed in Japanese Patent No. 54100. In this method, a branch point of a binary tree-like clock wiring path is once set, and then a connection is made between sibling branch points having a common parent branch point, and a new point at which the RC delay is balanced at a point on the actual wiring path. The location of the parent branch point is updated, and this is repeated bottom-up to determine a detailed wiring route.

Further, in the hierarchical clock distribution system by inserting buffer cells, after the detailed position of the buffer cell is determined, a detailed wiring is provided by including a detour portion in a path near the buffer cell so as to equalize the delay in the same layer. Is going. Furthermore, for the part except the intra-cluster route,
Wiring is performed using a dedicated wiring layer.

[0009]

The above-mentioned conventional LSI
In the layout design, a method of distributing clock signals by a mesh method or a tree method is used in order to avoid manually arranging the arrangement positions of elements for inputting clocks and the wiring paths of clocks.

[0010] However, in the mesh method, skew occurs depending on where the clock signal is extracted from the mesh. However, due to the speeding up of the design circuit due to the recent miniaturization of the LSI manufacturing process, the skew generated in this method cannot be ignored. Has become.

In the tree method, the clock signal net is formed in a tree shape under the situation where the number of elements for inputting clocks is dramatically increasing due to the recent miniaturization of the LSI manufacturing process and the enlargement of the LSI. In such a case, a large amount of buffers are inserted on the clock path, which reduces the capacity of the LSI.

Furthermore, due to the increase in the operating speed of circuit elements due to the miniaturization of the LSI manufacturing process, the influence of transistor speed variations on the design circuit cannot be ignored. In this tree method, a plurality of buffers are inserted on the path until the clock signal reaches the element to which the clock is input, so that it is liable to be affected by variations in transistor operating speed.

[0013] Due to the variation in the transistor operation speed of the buffer on the intermediate route of the clock, the measured value of the clock skew after the LSI is manufactured becomes large.
In a method of distributing clock signal nets in a tree shape, an operation speed expected at the time of design may not be obtained.

Here, the variation in the transistor operating speed refers to the variation in the transistor operating speed due to the non-uniformity of the degree of chemical reaction in the LSI manufacturing process in the LSI.

Accordingly, an object of the present invention is to solve the above-mentioned problems, to reduce the occurrence of clock skew, to suppress the increase in clock skew after LSI fabrication due to variations in transistor operation speed, and to suppress the LSI accommodation capacity. It is an object of the present invention to provide a clock signal distribution design circuit and a method thereof which can eliminate the problem, and a recording medium recording a control program therefor.

[0016]

A clock signal distribution design circuit according to the present invention is a clock signal distribution design circuit that performs a clock signal distribution design in a layout design of a large-scale integrated circuit based on at least circuit connection information. A clock main line for supplying the clock signal to a clock input element for inputting the clock signal, the clock main line being arranged in a comb shape, and the clock main line being based on a target delay value calculated according to a delay value in the clock main line. Wiring is provided between the clock input element and a clock buffer disposed between a clock main line and the clock input element, and the type of the clock buffer is set to the clock main line.
The delay is changed according to the delay value .

Another clock signal distribution design circuit according to the present invention is a clock signal distribution design circuit for performing a clock signal distribution design in a layout design of a large-scale integrated circuit performed at least based on circuit connection information. A arranging means for arranging a clock main line for supplying the clock signal to a clock input element for inputting a signal in a comb-tooth shape, and a target delay value calculated according to a delay value in the clock main line. Wiring means for arranging wiring between the clock input element and a clock buffer disposed between a clock main line and the clock input element; and changing the type of the clock buffer to the clock main line.
And changing means for changing according to the delay value .

A clock signal distribution design method according to the present invention is a clock signal distribution design method for performing a clock signal distribution design in a layout design of a large-scale integrated circuit performed at least based on circuit connection information. A clock trunk for supplying the clock signal to a clock input element to be input is provided in a comb shape, and the clock trunk and the clock input are based on a target delay value calculated according to a delay value in the clock trunk. so as to install the wiring between the clock buffer disposed between the element and the clock input device, said clock
To the delay value in the clock main line.
They are changed accordingly .

Another clock signal distribution design method according to the present invention is a clock signal distribution design method for performing a clock signal distribution design in a layout design of a large-scale integrated circuit based on at least circuit connection information. Arranging a clock main line for supplying the clock signal to a clock input element for inputting a signal in a comb-teeth shape, and the clock main line based on a target delay value calculated according to a delay value in the clock main line. the clock and the step of installing the wiring between the clock buffer and the clock input device is disposed between the input element, the clock trunk line the type of the clock buffer and
Changing according to the delay value in .

A recording medium on which a clock signal distribution design control program according to the present invention is recorded is a clock signal for causing a processor to perform a clock signal distribution design in a layout design of a large-scale integrated circuit based on at least circuit connection information. A recording medium on which a distribution design control program is recorded, wherein the clock signal distribution design control program provides the processor with a comb-like clock trunk line for supplying the clock signal to a clock input element for inputting the clock signal. A clock buffer disposed between the clock main line and the clock input element based on a target delay value calculated according to a delay value in the clock main line, and a wiring between the clock input element and the clock buffer. And set the type of the clock buffer to the
It is changed according to the delay value on the clock main line .

That is, the clock signal distribution design circuit of the present invention combines clock trunk lines, conversion of buffers, and target delay lines in an LSI layout design. As a result, it is possible to make all the arrival times of the clocks to the clock input element constant, so that the variation in the time when the clock signal arrives at the clock input element, which occurs in the conventional clock signal distribution method ( Clock skew) can be suppressed.

Further, even if the number of elements for inputting clocks increases, the use of the comb-shaped clock trunk enables the number of clock buffers to be inserted on the clock path to be reduced. There is no need to insert multiple buffers in series on top. This prevents an increase in clock skew after LSI fabrication due to variations in transistor operating speed.

Furthermore, even if the number of clock input elements increases, the use of the comb-shaped clock trunk enables the number of clock buffers to be inserted on the clock path to be reduced, and the clock can be reduced as in the prior art. There is no need to insert an extra buffer for distribution. Therefore, it is possible to eliminate the pressure on the accommodation capacity of the LSI due to the clock buffer.

[0024]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a clock signal distribution design circuit according to a first embodiment of the present invention. In the figure, a clock signal distribution design circuit according to a first embodiment of the present invention includes a logical connection information / library information input unit 1, an arrangement information input unit 2, and a cluster generation unit 3.
A clock main line creating unit 4, a clock buffer generating unit 5, a target delay time calculating unit 6, a clock buffer converting unit 7, a clock wiring creating unit 8, a layout result output unit 9, a logical connection information / library Information table 10
And an arrangement information table 11.

The logical information / library information input unit 1 has L
In the layout design of an SI (Large Scale Integrated Circuit), in order to automatically obtain a clock wiring layout with a small clock skew, logical connection information between blocks constituting a circuit, the size of an LSI, the size of each logic element, Physical library information necessary for laying out the LSI, such as size, terminal position, and wiring width, and delay library information required for calculating delays of each block and wiring are input, and the information is logical connection information.・ Library information table 10
Is stored in

Block arrangement position information is input to the arrangement information input section 2, and the information is stored in the arrangement information table 11. The cluster generating unit 3 generates a cluster (not shown) by collecting a plurality of elements to which clocks are input. The clock trunk line creation unit 4 creates a clock trunk line (not shown) based on the cluster created by the cluster generation unit 3 and preset characteristics and the like. The clock buffer generator 5 generates a clock buffer (not shown) for each cluster created by the cluster generator 3.

The target delay time calculation section 6 calculates a target delay time from the clock buffer to each clock input element (not shown) in consideration of the delay value of the clock main line. The clock buffer conversion unit 7 changes the type of the clock buffer. The clock wiring generator 8 performs wiring from the clock buffer to each clock input element according to the target delay time. The layout result output unit 9 outputs the result of the layout described above. Each of the above units can be realized by a computer (not shown) executing a program in a control memory (not shown). As the control memory, a floppy disk or a ROM (read only memory) can be used. is there.

FIG. 2 is a diagram showing an example of cluster generation by the cluster generation section 3 of FIG. In the figure, an LSI 21 has n equal lines (n = 4 in the first embodiment of the present invention) 22a.
To 22c and 23a to 23c are equally divided into 16 areas, and clusters 24a, 24b, 24c,
…… has been generated.

FIG. 3 is a diagram showing the configuration of the cluster 24a of FIG. In the figure, the clock input elements 25a-1 to 25a-10 and the clock buffer 26a are included in the cluster 24a.

FIG. 4 is a diagram showing an example of a clock main line created by the clock main line creation section 4 of FIG. In the figure, the above-mentioned clusters 24a, 24b, 2
4c,..., Horizontal clock trunk lines 27c to 27
k is set in a comb shape.

The horizontal clock trunks 27c to 27k are connected to the vertical clock trunks 27a and 27b, and the vertical clock trunks 27a and 27b are connected to the trunk driving buffer 2a.
8a to 28f are connected.

FIG. 5 shows the clock trunk lines 27c to 27k of FIG.
FIG. 6 is a diagram illustrating an example of connection of a clock buffer to the multiplexed clock. In the figure, a branch line 2 is connected to clock main lines 27h, 27i, and 27j.
Clock buffers 26a to 26c via 9a to 29c
Is connected.

Here, d1 indicates the distance from the main line driving buffer 28e to the clock buffer 26a, and d2, d
3 is a clock signal from the main line driving buffer 28c to the clock buffer 26.
b, 26c are shown.

FIG. 6 is a diagram showing the calculation of the target delay time, the change of the type of the clock buffer, and the installation of the bypass wiring according to the first embodiment of the present invention. In the figure, if the target delay value of the wiring to the clock buffer 26c and the clock input element 25c is 270 ps [see FIG. 6 (1)], the shortest wiring of the wiring to the clock input element 25c is determined. The delay time (50 ps) is calculated from the estimation [see FIG. 6 (2)].

The target delay time calculator 6 calculates the difference (270-50 = 220) between the delay time and the target delay value, and sends the calculated value to the clock buffer converter 7. The clock buffer converter 7 sets the type of the clock buffer 26c to a buffer having a delay value that does not exceed the difference (220 ps) between the delay time and the target delay value (for example, a 200 ps buffer).
[See FIG. 6 (3)].

After the type of the clock buffer 26c is changed by the clock buffer converter 7, the clock wiring generator 8 calculates the difference (270-200 = 70) between the delay value of the clock buffer 26c and the target delay value, and The bypass wiring is performed so that the delay value of the wiring to the input element 25c is equal to the difference between the delay value of the clock buffer 26c and the target delay value [see FIG. 6 (4)].

If a restriction is placed on the clock buffer 26c immediately below the clock trunk 27j at the time of cluster generation, it is necessary to consider the delay of the branch line 29c connecting the clock buffer 26c and the clock trunk 27j. Disappears.

FIG. 7 and FIG. 8 are diagrams showing examples of creating clock wiring by the clock wiring creating unit 8 of FIG. FIG. 7 shows a wiring example of the clock wiring 30 when the target delay value between the clock buffer 26 and the clock input element 25 is small, and FIG. 8 shows that the target delay value between the clock buffer 26 and the clock input element 25 is small. Clock wiring 3 when large
3 shows an example of wiring.

FIG. 9 is a diagram showing an example of a layout result output from the layout result output unit 9 of FIG. In the figure, clock buffers 26-1, 26-2 are connected to a clock trunk 27 connected to a trunk drive buffer 28, and clock input elements 25-1, 25-2 are respectively connected to the clock buffers 26-1, 26-2. , 25-3,25-
4, ..., 25-11,25-12,25-13,25
-14,... Are connected.

FIG. 10 is a flowchart showing a processing operation of clock signal distribution design according to the first embodiment of the present invention, and FIG. 11 is a flowchart showing a processing operation of target delay value creation according to the first embodiment of the present invention. It is. These figures 1
The processing of the clock signal distribution design according to the first embodiment of the present invention will be described with reference to FIGS.

The logical connection information / library information input section 1 is an information input step. In this step, logical connection information, physical library information, and delay library information required for layout design are input. It is stored in the logical connection information / library information table 10 (step S1 in FIG. 10).

Here, the logical connection information is information on a logical connection relationship between blocks constituting a circuit, and the physical library information is a size of an LSI to be designed, a size and a terminal position of each type of a logical element, wiring, and the like. Is necessary information for laying out the LSI, such as the width of the LSI. The delay library information describes information for calculating a delay value of the wiring between logic elements such as a capacitance value per unit area of the wiring, a resistance value, and the like, a delay value of each logic element, and the like.

Block arrangement position information is input from the arrangement information input section 2, and the information is stored in the arrangement information table 11 (step S2 in FIG. 10). This arrangement information is obtained by using a conventional automatic arrangement method or manually designating the arrangement position of each block. At this stage, there is no particular need to consider the clock wiring, and there is no particular restriction on the arrangement position of the clock input element.

Thereafter, the cluster generation unit 3 performs clustering of the clock input elements (step S in FIG. 10).
3). There are many possible clustering methods, but here it is necessary to combine nearby elements.

For example, as an example, there is a method as shown in FIG. In this method, the entire surface of the LSI 21 is divided into n equal lines 2
2a to 22c and 23a to 23c, the clock input elements 25 therein are divided into certain areas, and the clock input elements 25 therein are put together into one group (cluster) 24a, 24b, 24c,
......

In this case, the clusters 24a, 24b, 24
The size of c,... varies depending on the accommodating capacity of the LSI 21 and the driving ability of the clock buffer to be used, but if the clock input elements 25 are uniformly arranged on the entire surface of the LSI 21, the size of c,. The number of clock input elements can be determined.

For example, if the clock input element 25 is
If there are 1000 elements in 1 and the number of elements that can be connected to one clock buffer is 5, the clusters 24a, 24
.. can be calculated to be 200, and if the area of the arrangement region inside the LSI 21 is 50 mm ² , the area of each of the clusters 24a, 24b, 24c,. .25 mm ² , and the LSI 21 may be divided into 0.5 mm units, which is the square root, to generate clusters 24 a, 24 b, 24 c,.
In this case, the clock trunk line is created in units of 0.5 mm.

The clock input element 2 in the LSI 21
In the case where the arrangement of the LSI 5 is uneven and there is a portion where the arrangement is concentrated, the division width of the LSI 21 is reduced and the cluster 24
The size of a, 24b, 24c,... may be reduced.

Subsequently, the clock main line creating section 4 creates the clusters 24a, 24b, 24 created by the cluster creating section 3.
When the number of clock input elements 25 in c,... reaches a predetermined value (step S4 in FIG. 10), the clusters 24a, 24b, 24c,
.. And the clock trunk lines 27a to 27k in the LSI 21 are created based on the preset characteristics of the clock trunk line (step S5 in FIG. 10).

In this case, the shape of the clock trunk lines 27a to 27k created by the clock trunk line creation section 4 is comb-shaped as shown in FIG. 4, and the number and wiring of the clock trunk lines 27c to 27k in the horizontal direction crossing the LSI 21. Is changed depending on the wiring length to the clock buffer, the number of elements to be clustered, and the like at the time of clustering in the cluster generation unit 3.

The clock buffer generator 5 is a group (cluster 24) clustered by the cluster generator 3.
a, 24b, 24c,...)
a to 26c are generated and arranged (step S in FIG. 10).
6).

As shown in FIG. 3, the clock buffers 26a to 26c are arranged at the respective locations of the clock input elements 25.
A place where the wiring to a-1 to 25a-10 is as short as possible. If the clock buffers 26a to 26c cannot be arranged (Step S7 in FIG. 10), the clock buffer generator 5 searches around the target arrangement position to find a position that can be arranged (Step S15 in FIG. 10).

Thereafter, the clock buffer generator 5 connects the clock buffers 26a to 26c to the horizontal clock trunks 27c to 27k (step S in FIG. 10).
8). The connection between the clock buffers 26a to 26c and the clock main lines 27c to 27k in the horizontal direction is performed by using a conventional wiring means so as to connect to the clock main line closest to the clock buffers 26a to 26c.

Here, the main line driving buffers 28a to 28f
From the clock input elements 25a-1 to 25a-10 are divided into three types and delay values are considered. From main line driving buffers 28a to 28f to clock buffers 26a to 2
The delay value generated in the horizontal clock trunk lines 27c to 27k up to 6c is α, the internal circuit delay value of the clock buffers 26a to 26c is β, and the wiring from the clock buffers 26a to 26c to the clock input elements 25a-1 to 25a-10. Assuming that the delay value is γ, the main line driving buffers 28a to 28f
From the clock input elements 25a-1 to 25a-10 can be expressed as α + β + γ.

If this value can be set to the same value for all the clock input elements 25a-1 to 25a-10, the clock skew can be set to zero.

The target delay time calculator 6 sends the clock input element 2 from the clock buffers 26a to 26c in the following procedure.
A target delay value (target value of β + γ) of the clock wiring to 5a-1 to 25a-10 is set.

First, from the positions of the clock buffers 26a to 26c arranged by the clock buffer generator 5,
The delay values (α) of the horizontal clock trunks 27c to 27k are obtained. The delay of the clock signal generated in the clock trunk lines 27c to 27k in the horizontal direction can be easily calculated by arranging the clock trunk lines 27a to 27k in a comb-teeth shape. It can be calculated by a method of calculating a delay value depending on the length.

In the method of approximation, as shown in FIG. 5, if clock buffers 26a to 26c are generated, distances d1 to d3 between main line driving buffers 28a to 28f and clock buffers 26a to 26c are determined. Figure 5
(Step S9 in FIG. 11)
a).

Many methods for calculating the delay value of the wiring can be considered in view of the balance between the calculation accuracy and the calculation time. For example, the capacitance value or resistance value per unit area of the clock trunk lines 27c to 27k and the clock trunk lines 27c to 27k are determined in advance. If the delay value per unit length of the wiring is calculated in advance from the width or the like, it can be approximated by a simple linear expression, and can be expressed by α = ax. Here, α is the delay value of the main line, x is the wiring length, and a is the delay value per unit length (step S9b in FIG. 11).

As a result of calculation from the capacitance value or resistance value per unit area of the clock main lines 27c to 27k and the width of the clock main lines 27c to 27k, 1
If a delay of ps (picoseconds) occurs, the distance d between the main line driving buffer 28e and the clock buffer 26a
If 1 is 1 mm, the delay value generated on the clock main line 27h is 10 ps.

If the distance d2 between the main line driving buffer 28c and the clock buffer 26b is 5 mm, it can be calculated that the delay value generated on the clock main line 27i is 50 ps. If the total target delay value from the main line driving buffers 28a to 28f to the clock input elements 25a-1 to 25a-10 is 500 ps, the clock buffer 2
The target delay value from 6a to the clock input elements 25a-1 to 25a-10 is calculated as 500ps-10ps,
It can be calculated as 490 ps.

Similarly, with respect to the clock buffer 26b, it can be calculated as 500ps-50ps, that is, 450ps. Similarly, all clock buffers 26a-26
A target delay value (target value of β + γ) is calculated for c and stored (step S9 in FIG. 10) (steps S9a to S9e in FIG. 11) (see FIG. 6).

The horizontal clock trunk lines 27c to 27c
When calculating the delay value generated at 27k, the clock buffers 26a to 26k are connected to the clock trunk lines 27c to 27k in the horizontal direction.
The delay calculation formula for each of the horizontal clock trunks 27c to 27k can be changed or the capacitance and resistance values of the wiring from the horizontal clock trunks 27c to 27k to the clock buffers 26a to 26c can be changed depending on the number of connected c. In consideration of the above, it is also possible to adopt a method of changing the delay calculation formula for each of the horizontal clock trunk lines 27c to 27k, thereby improving the accuracy of the delay calculation. In this case, clock skew can be further reduced.

In the above calculation, the clock trunk lines 27c to 27c in the horizontal direction are output from the trunk line driving buffers 28a to 28f.
Since the delay in the vertical clock trunk lines 27a and 27b up to 27k is estimated to be small, it is not included in the calculation.

With the above procedure, the value of the delay (α) generated in the horizontal clock trunk lines 27c to 27k is determined.
Internal delay of clock buffers 26a-26c + clock input elements 25a-
The target value of the wiring delay from 1 to 25a-10 (the target value of β + γ) can be calculated.

The type of the clock buffers 26a to 26c is changed by the clock buffer converter 7 and the target delay wiring is performed by the clock wiring generator 8 so as to satisfy the target value.

The clock buffer converter 7 changes the type of each of the clock buffers 26a to 26c (step S10 in FIG. 9). As a specific method, several buffers having different internal delay values are prepared in advance, and the buffers are replaced. For example, 100p
s, 150ps, 200ps, 250ps, 300ps
Is prepared, and if the target delay value is 270 ps, the internal delay value is 250 p.
If the change is made so as to use the buffer type of s, the delay required for the wiring is only 20 ps, and the bypass wiring by the clock wiring creating unit 8 can be minimized.

However, in this case, if the buffer type is changed while completely ignoring the delay generated in the wiring, there is a possibility that wiring cannot be performed so as to satisfy the target value later. Therefore, the clock buffer converter 7 changes the buffer type more accurately by subtracting the estimated value of the wiring delay from the target delay value.

For example, if the target delay value is 270 ps and the estimated value of the wiring delay is 50 ps, the delay to be absorbed by the buffer type change and the bypass wiring can be calculated to be 220 ps because 270 ps−50 ps.
Therefore, a buffer having an internal delay value of 200 ps is selected as the buffer type, and 270 ps−200 ps = 70
Since the clock is ps, the target delay wiring of 70 ps is performed by the clock wiring creating unit 8.

There are various methods for estimating the wiring, and there is a method of estimating by creating a half-perimeter of a rectangle surrounding the wiring or a simple Steiner tree. If the target delay calculated by the target delay time calculator 6 can be satisfied only by the bypass wiring of the clock wiring generator 8, the change of the buffer type by the clock buffer converter 7 may be omitted.
In this case, the internal circuit delay value β of the clock buffers 26a to 26c is set to a constant value.

In the above procedure, the actual clock trunk line 2
Delay generated by 7c to 27k + clock buffer 26
The internal delay values (α + β) of a to 26c can be determined. Therefore, it is possible to calculate the target value (target value of γ) of the wiring delay from the clock buffers 26a to 26c to the clock input elements 25a-1 to 25a-10.

Thereafter, the clock wiring creating section 8 sends the clock input elements 25a- from the clock buffers 26a to 26c.
The wiring from 1 to 25a-10 is performed (step S1 in FIG. 9).
1). At that time, wiring is performed so as to satisfy the target delay value (target value of γ) obtained by the target delay time calculation unit 6 and the clock buffer conversion unit 7. As shown in FIG. 7, the wiring means used in a normal LSI layout usually has the shortest distance between terminals (between the clock output terminal 31 of the clock buffer 26 and the clock input terminal 32 of the clock input element 25). The wiring 30 is set.

However, when the wiring 30 is too short and becomes smaller than a target delay value in the above-described wiring method in which the distance between terminals is minimized, as shown in FIG. 33 is created. The length of the detoured wiring 33 can be calculated from the target delay value of the wiring.

Many methods of calculating the delay value of the wiring can be considered in consideration of the calculation accuracy and the calculation time. However, the capacitance value and the resistance value per unit area of the wirings 30 and 33, the widths of the wirings 30 and 33, etc. are determined in advance. To wiring 3 per unit length
By calculating the delay values of 0 and 33 in advance, it can be approximated by a linear expression, and can be represented by γ = bx. Here, γ is a target delay value, x is a wiring length, and b is a delay value per unit length.

If the value obtained in advance from the capacitance value or resistance value per unit area of the wirings 30 and 33 and the width of the wirings 30 and 33 is 5 μm per 1 ps, if the target delay value is 10 ps, If so, this equation can be used to calculate the need for a 50 micron detour. Further, at this time, the wiring of the general signal has not been performed yet in the LSI 21 and the wiring area is free, so that the detour wiring can be easily created.

The above processing operation is performed by each of the clusters 24a and 24a.
b, 24c,... (step S6 in FIG. 10).
To S13, S15), all clusters 24a, 24b,
When the processing for 24c,... Is completed (step S13 in FIG. 10), the arrangement of the clock buffers 26a to 26c and the clock input element 25 created by the processing are completed.
The wirings a-1 to 25a-10 are output as layout results from the layout result output unit 9 (step S14 in FIG. 10). By using this layout result,
Wiring of general signals is performed.

By the flow of the series of processes (steps S1 to S15 in FIG. 10), it is possible to automatically perform the clock signal distribution design while suppressing the skew of the clock signal, and to automatically realize the layout result output. be able to.

As described above, clock trunk lines 27c-2c
7k and clock buffers 26, 26a to 26c, 26-
By combining the conversion of 1, 26-2 and the target delay wiring, the clock input elements 25, 25a-1 to 25a
a-10, 25-1 to 25-4, 25-11 to 25-1
4 can be made constant, so that in the layout design of the LSI 21, the clock signals generated by the conventional clock signal distribution method are replaced by the clock input elements 25, 25a-1 to 25a-10, 2
Variations in the time to reach 5-1 to 25-4 and 25-11 to 25-14 (clock skew) can be suppressed.

The clock input elements 25, 25a-1
~ 25a-10, 25-1 ~ 25-4, 25-11 ~ 2
Even if the number of 5-14 increases, the clock trunk lines 27c-27
4 and 9, the clock buffers 26, 26-1, 26-2, 26a to 26c to be inserted on the clock path are small, Since there is no need to insert a plurality of buffers in series on the clock path as in the related art, an increase in clock skew after manufacturing the LSI 21 due to variations in transistor operating speed does not occur.

Further, the clock input elements 25, 25a-
1-25a-10, 25-1-25-4, 25-11-11
Even if the number of clock lines 25-14 increases, the clock trunk lines 27c-2
As shown in FIG. 4 and FIG. 9, the clock buffers inserted on the clock path are 26, 26-1, 26-2, and 26a to 26c. Since there is no need to insert an extra buffer for distributing clocks as in the related art, the accommodation capacity of the LSI 21 is not reduced as in the related art.

FIG. 12 is a flowchart showing the processing operation of the clock signal distribution design according to the second embodiment of the present invention. In the drawing, the second embodiment of the present invention is the same as the processing operation of the clock signal distribution design according to the first embodiment of the present invention shown in FIG. 10 except that the method of arranging the clock buffers by the clock buffer generator 5 is different. The same steps are denoted by the same reference numerals as in the first embodiment of the present invention. The operation of the same step is the same as that of the first embodiment of the present invention.

If the clock buffers 26a to 26c cannot be arranged (step S7 in FIG. 12), the clock buffer generator 5 places the clock buffers 26a on the already arranged elements.
To 26c are superposed and arranged (step S21 in FIG. 12). The already arranged elements other than the clock buffers 26a to 26c are moved and arranged (Step S22 in FIG. 12).

Thus, the clock buffers 26a to 26a
26c are located at appropriate positions in the clusters 24a, 24b, 24c,...
It is arranged in a place where the wiring to 1 to 25a-10 is as short as possible.

FIG. 13 is a diagram showing a configuration example of a clock main line according to the third embodiment of the present invention. In the figure, in the third embodiment of the present invention, clusters 24a,
4b, 24c,... In the horizontal direction according to the clock trunk line 27
c to 27k are set in a comb shape.

The horizontal clock trunks 27c to 27k are connected to the vertical clock trunks 27a and 27b, and the vertical clock trunks 27a and 27b correspond to the horizontal clock trunks 27c to 27k, respectively. 28
-1 to 28-18 are connected.

As a result, each cluster 24a, 24
b, 24c,..., clock buffers 26a to 26c
When placing the clock trunks 27a, 27b in the vertical direction,
There is no need to consider the delay due to

FIG. 14 is a diagram showing an example of dividing a cluster according to the fourth embodiment of the present invention. FIG. 14A shows an example in which the cluster 24a shown in FIG. 3 is divided into two in the vertical direction.
4B shows an example in which the cluster 24a shown in FIG. 3 is divided into two in the horizontal direction.

In the fourth embodiment of the present invention, as in the first embodiment of the present invention, first, as shown in FIG.
4a, 24b, 24c,... Are generated, but the number of clock input elements in these clusters 24a, 24b, 24c,.

In that case, the clusters 24a, 24b, 24
In order to set the number of clock input elements in c,... to a predetermined value, cluster generation may be performed again. For example, in the first embodiment of the present invention, the LSI 21 is equally divided into 16 regions, but it is also possible to divide the LSI into 25 regions. On the other hand, in the fourth embodiment of the present invention, only clusters having a predetermined number of clock input elements or more (in this embodiment, clusters 24a) are divided.

That is, as shown in FIG. 14A, the clock input element 25a- in the cluster 24a shown in FIG.
1 to 25a-10 to the clock input elements 25a-1, 25
a-2, 25a-4 to 25a-6, 25a-8, 25a
-9 and clock input elements 25a-3, 25
clusters 24a-1 and 24a-2 are generated so as to be divided into groups a-7 and 25a-10, and a clock buffer 26a- is provided in the clusters 24a-1 and 24a-2.
1, 26a-2 are arranged.

In this case, the clock buffers 26a-1,
Since it is not necessary to increase the number of horizontal clock trunk lines to which 26a-2 is connected, the cluster is divided in the vertical direction as much as possible during cluster division.

As shown in FIG. 14B, the clock input elements 25a-1 to 25a-1 in the cluster 24a shown in FIG.
25a-10 to the clock input elements 25a-1 to 25a-
5, 25a-7 and a clock input element 25a.
Clusters 24a-3 and 24a-4 are generated so as to be divided into groups of −6, 25a-8 to 25a-10, and clock buffers 26a-3 and 26a-4 are placed in the clusters 24a-3 and 24a-4. Have been placed.

If the cluster 24a cannot be divided into two in the vertical direction, it is divided in the horizontal direction as described above. In that case,
Although the clock buffers 26a-3 and 26a-4 can be connected to the same horizontal clock trunk, the clock buffers 26a-
It is more efficient to add another horizontal clock trunk to each of the 3, 26a-4. However, in this method, the number of horizontal clock trunk lines increases.

Although the above-described division method describes a method for dividing a cluster into two equal parts, if the number of clock input elements in the divided cluster still exceeds a predetermined number, the method is further divided into two equal parts. Alternatively, a method of dividing into four from the beginning can be considered.

FIG. 15 is a flowchart showing the processing operation of the clock signal distribution design according to the fourth embodiment of the present invention. In the drawing, the fourth embodiment of the present invention is the same as the processing operation of the clock signal distribution design according to the first embodiment of the present invention shown in FIG. Steps are denoted by the same reference numerals as in the first embodiment of the present invention. The operation of the same step is the same as that of the first embodiment of the present invention.

The cluster generator 3 creates the cluster 24
If the number of clock input elements 25 in a, 24b, 24c,... does not fall within a predetermined value (step S in FIG. 15).
4), it is determined whether or not a cluster in which the number of clock input elements 25 exceeds a predetermined value can be divided (step S3 in FIG. 15).
1).

The cluster generating unit 3 includes a clock input element 25
If the number of clusters exceeds a predetermined value, the cluster is divided by the above-described method (step S32 in FIG. 15). If the cluster in which the number of the clock input elements 25 exceeds the predetermined value is not divisible, the cluster generation unit 3 returns to step S3 and performs cluster creation again.

Thus, the number of clock input elements 25 in the clusters 24a, 24b, 24c,... Created by the cluster generation unit 3 can be kept within a predetermined value. The buffer is not overloaded.

FIG. 16 is a diagram showing a method of equalizing the delay of the horizontal clock trunks 27c to 27k to the trunk drive buffers 28a to 28f according to the fifth embodiment of the present invention. In the figure, in the fifth embodiment of the present invention, delay compensation wiring is provided according to the distance between the horizontal clock trunk lines 27c to 27k and the shortest trunk line driving buffers 28a to 28f. Trunk line driving buffers 28a to 28f for horizontal clock trunk lines 27c to 27k, respectively.
The delay for

Here, h1 to h3 are the distances from the horizontal clock trunks 27c to 27e to the shortest trunk drive buffer 28a, and h4 and h5 are the shortest distances from the horizontal clock trunks 27f and 27h. The distance to a certain trunk drive buffer 28b is shown.

FIG. 17 is a flowchart showing the processing operation of the clock signal distribution design according to the fifth embodiment of the present invention. In the figure, in a fifth embodiment of the present invention, clock buffers 26a to 26c are connected to clock trunk lines 27c to 27k.
10 is the same as the processing operation of the clock signal distribution design according to the first embodiment of the present invention shown in FIG. 10 except that the connection method is different, and the same steps are denoted by the same reference numerals as in the first embodiment of the present invention. I have. The operation of the same step is the same as that of the first embodiment of the present invention.

The clock buffer generator 5 includes clock buffers 26a to 26c and horizontal clock trunks 27c to 2c.
Before the connection with 7k, the horizontal clock trunk 27c
The vertical distance from the main line driving buffers 28a to 28f is calculated for the main buffers 27k to 27k (step S41 in FIG. 17).

When the clock buffer generator 5 completes the calculation of the vertical distance from the main line driving buffers 28a to 28f with respect to all the horizontal clock main lines 27c to 27k (step S42 in FIG. 17), the clock buffer generator 5 calculates A delay compensating wiring is created accordingly, and clock buffers 26a to 26a-2
6c and the horizontal clock trunk lines 27c to 27k are connected (step S43 in FIG. 17).

At this time, the delay compensating wires are connected to the main line driving buffers 28a to 28k of the horizontal clock main lines 27c to 27k, respectively.
8f, the main line driving buffers 28a to 28f
Horizontal clock trunk line 27c farthest from
It is set to have a delay of 27k. by this,
Delays of the horizontal clock trunks 27c to 27k to the trunk drive buffers 28a to 28f are made uniform.

As described above, the cluster generation unit 3 uses the LSI 2
1, the clock input elements 25, 25a-1 to 25a-1
Clusters 24a, 24b, 24c,... Are formed by collecting a plurality of clusters 24a, 24b, 24c,.
, and the clock trunk lines 27a to 27k are generated based on preset characteristics and the like, and the clock buffer generator 5 generates clock trunk lines 27a to 27k for each of the clusters 24a, 24b, 24c,. Are generated and arranged, and the target delay time calculation unit 6
26a-26c to each clock input element 25, 25a-
1-25a-10, 25-1-25-4, 25-11-11
The target delay time to 25-14 is calculated, the type of the clock buffers 26, 26a-26c is changed by the clock buffer converter 7, and the clock wiring generator 8 changes the clock buffers 26, 26a-26c according to the target delay time. Each clock input element 25, 25a-1 to 25a-10,
By performing wiring to 25-1 to 25-4 and 25-11 to 25-14 and outputting the layout result from the layout result output unit 9, clock skew is less likely to occur, and after the LSI 21 is manufactured due to variations in transistor operating speed. LSI without increasing clock skew
It is possible to eliminate the pressure on the accommodation capacity of the housing 21.

[0106]

As described above, according to the present invention, a clock input for inputting a clock signal at the time of designing a distribution of a clock signal in a layout design of a large-scale integrated circuit based on at least circuit connection information. A clock main line for supplying a clock signal to the element is arranged in a comb-tooth shape, and a wiring is provided between the clock buffer and the clock input element disposed between the clock main line and the clock input element. By setting the delay based on the target delay value calculated according to the value, the clock skew is less likely to occur, and L due to variation in the transistor operation speed is reduced.
Without increasing clock skew after SI manufacturing,
This has the effect of eliminating pressure on the accommodating capacity of the LSI.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a clock signal distribution design circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of cluster generation by a cluster generation unit in FIG. 1;

FIG. 3 is a diagram showing a configuration of a cluster in FIG. 2;

FIG. 4 is a diagram illustrating an example of a clock main line input from a clock main line input unit in FIG. 1;

FIG. 5 is a diagram illustrating an example of connection of a clock buffer to the clock main line in FIG. 4;

FIG. 6 is a diagram showing calculation of a target delay time, change of the type of a clock buffer, and installation of a bypass wiring according to the first embodiment of the present invention.

FIG. 7 is a diagram illustrating an example of creating a clock wiring by a clock wiring creating unit in FIG. 1;

FIG. 8 is a diagram showing an example of creating a clock wiring by a clock wiring creating unit in FIG. 1;

FIG. 9 is a diagram illustrating an example of a layout result output from the layout result output unit in FIG. 1;

FIG. 10 is a flowchart showing a processing operation of clock signal distribution design according to the first embodiment of the present invention.

FIG. 11 is a flowchart illustrating a processing operation of creating a target delay value according to the first embodiment of the present invention.

FIG. 12 is a flowchart illustrating a processing operation of a clock signal distribution design according to the second embodiment of the present invention.

FIG. 13 is a diagram showing a configuration example of a clock trunk line according to a third embodiment of the present invention.

14A is a diagram showing an example in which the cluster shown in FIG. 3 is divided into two in the vertical direction, and FIG. 14B is a diagram showing an example in which the cluster shown in FIG. 3 is divided into two in the horizontal direction.

FIG. 15 is a flowchart showing a processing operation of clock signal distribution design according to a fourth embodiment of the present invention.

FIG. 16 is a diagram illustrating a method for equalizing the delay of each horizontal clock main line to a main line driving buffer according to a fifth embodiment of the present invention;

FIG. 17 is a flowchart illustrating a processing operation of a clock signal distribution design according to a fifth embodiment of the present invention.

FIG. 18 is a diagram showing a tree-like layout example according to a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Logical connection information / library information input part 2 Arrangement information input part 3 Cluster generation part 4 Clock trunk line generation part 5 Clock buffer generation part 6 Target delay time calculation part 7 Clock buffer conversion part 8 Clock wiring generation part 9 Layout result output part 10 Logical connection information / library information table 11 Allocation information table

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 17/50 H01L 21/82 G06F 1/10

Claims (35)

(57) [Claims] 1. A clock signal distribution design circuit for performing a clock signal distribution design in a layout design of a large-scale integrated circuit performed at least based on circuit connection information,
A clock main line for supplying the clock signal to a clock input element for inputting the clock signal is arranged in a comb shape, and the clock main line is based on a target delay value calculated according to a delay value in the clock main line. the so as to install the wiring between the clock buffer disposed between the clock input element and the clock input device and, put the type of the clock buffer to the clock trunk line
A clock signal distribution design circuit, wherein the clock signal distribution design circuit is changed in accordance with a delay value . 2. The clock main line is connected to the clock input.
So that the number of elements is a predetermined number set in advance
According to multiple divided areas obtained by dividing a large-scale integrated circuit area
2. The clock signal distribution design circuit according to claim 1, wherein the clock signal distribution design circuit is arranged . 3. The clock of each of the plurality of divided areas.
When the number of input elements exceeds the predetermined number,
Claims, characterized in that as further dividing the frequency range
2. The clock signal distribution design circuit according to 2. 4. The clock buffer according to claim 2 , wherein
If the wiring to the clock input element in the split area becomes short
Claim 2 characterized in that it is arranged in a place
Is a clock signal distribution design circuit according to claim 3. 5. The clock buffer according to claim 1 , wherein
This is necessary when the wiring to the input element cannot be
Search around the position to find a position where it can be placed and place it
Clock signal distribution circuit design according to claim 4, characterized in that the the like. 6. The clock buffer according to claim 1 , wherein
Before when the wiring to the input element cannot be placed where it becomes short
After the clock is placed on the clock input device,
6. The clock signal distribution design circuit according to claim 5, wherein the input element is moved . 7. The clock trunk and each of the clock trunks.
Circuit delay between the stem line drive buffer for driving the line each
7. The clock signal distribution design circuit according to claim 1, further comprising a delay compensating wiring for equalizing the clock signal distribution within the circuit. 8. The process is performed based on at least circuit connection information.
Clock signals in layout design of large-scale integrated circuits
A clock signal distribution design circuit for performing distribution design of
The clock input element for inputting the clock signal is connected to the clock input element.
The clock main line for supplying the lock signal is arranged in a comb shape.
And the delay value in the clock main line.
The clock trunk based on a target delay value calculated accordingly.
A clock arranged between a line and the clock input element
Install wiring between the buffer and the clock input element
Wiring means and the type of the clock buffer
Means for changing according to the delay value on the backbone trunk line.
A clock signal distribution design circuit, comprising: 9. The clock input device according to claim 9 , wherein:
So that the number of
According to the multiple divided areas obtained by dividing the area of the model integrated circuit,
A clock main line is arranged.
The clock signal distribution design circuit according to claim 8. 10. The method according to claim 1 , wherein each of the plurality of divided areas has
When the number of input elements exceeds the predetermined number,
Including a dividing means for further dividing the region
The clock signal distribution design circuit according to claim 9. 11. The clock buffer according to claim 11 , wherein
The wiring to the clock input element in the divided area is shortened
10. The device according to claim 9, wherein the device is arranged at a place.
The clock signal distribution design circuit according to claim 10. 12. The clock buffer according to claim 1 , wherein
When the wiring to the input element cannot be
Search around the position to find a place where it can be placed and place it
12. The clock according to claim 11, wherein
Signal distribution design circuit. 13. The clock buffer according to claim 1 , wherein
When the wiring to the input element cannot be
After arranging it on the clock input element,
Wherein the input element is moved.
Item 12. The clock signal distribution design circuit according to Item 11 . 14. The clock trunk and each of the clocks
The delay between the main line driving buffer that drives each main line
Means for arranging delay compensation wiring to equalize in the road
14. Any one of claims 8 to 13, wherein:
Or a clock signal distribution design circuit according to any one of the preceding claims. 15. An operation which is performed based on at least circuit connection information.
Clock signals in the layout design of large-scale integrated circuits.
This is a clock signal distribution design method that performs signal distribution design.
Before the clock input element for inputting the clock signal.
The main clock line for supplying the clock signal is comb-shaped
And calculate according to the delay value in the clock main line.
The clock main line and the
Clock buffer disposed between clock input elements
And install the wiring between the clock input element and
And the type of the clock buffer is set in the clock main line.
The delay is changed according to the delay value
Clock signal distribution design method. 16. The number of clock input elements is preset.
Area of the large-scale integrated circuit so as to have a predetermined number.
The clock main line according to a plurality of divided areas obtained by dividing the area
16. The device according to claim 15, wherein a plurality of the radiators are provided.
Clock signal distribution design method. 17. The method according to claim 17 , wherein each of the plurality of divided areas has
When the number of input elements exceeds the predetermined number,
Claims characterized by further dividing the area
Item 18. A clock signal distribution design method according to Item 16. 18. The clock in the plurality of divided areas
Place the clock buffer where the wiring to the input element is
17. The device according to claim 16, wherein a key is provided.
18. The clock signal distribution design method according to claim 17, wherein 19. The wiring to the clock input element is short.
When you can not place it in a certain place, search around that position
Find the place where it can be placed and place the clock buffer
19. The clock according to claim 18, wherein:
Signal distribution design method. 20. The wiring to the clock input element is short.
When the clock buffer can not be placed
After the clock is placed on the clock input device,
The input element is moved.
19. The clock signal distribution design method according to claim 18. 21. Each of said clock trunks and said clock
The delay between the main line driving buffer that drives each main line
To arrange delay compensation wiring to equalize in the road
21. The method according to claim 15, wherein
The clock signal distribution design method described in the above. 22. An operation performed based on at least circuit connection information.
Clock signals in the layout design of large-scale integrated circuits.
This is a clock signal distribution design method that performs signal distribution design.
Before the clock input element for inputting the clock signal.
The main clock line for supplying the clock signal is comb-shaped
And delay in the clock trunk
Based on the target delay value calculated according to the
Clock between the clock trunk and the clock input element.
Wiring between the clock buffer and the clock input element.
Setting the clock buffer type to the
Step of changing according to delay value in clock main line
Clock signal distribution design method characterized by having
Law. 23. The step of arranging said clock trunk line.
Is a predetermined number of clock input elements set in advance.
The area of the large-scale integrated circuit is divided so as to be the number.
The clock main line is arranged according to a plurality of divided areas.
23. The clock signal according to claim 22, wherein
No. distribution design method. 24. Each of the plurality of divided areas has a clock.
When the number of input elements exceeds the predetermined number,
Further comprising the step of subdividing the region
The clock signal distribution design method according to claim 23. 25. The clock in the plurality of divided areas
Place the clock buffer where the wiring to the input element is
23. The device according to claim 23, wherein
25. The clock signal distribution design method according to claim 24. 26. The wiring to the clock input element is short.
When you can not place it in a certain place, search around that position
Find the place where it can be placed and place the clock buffer
26. The clock according to claim 25, wherein:
Signal distribution design method. 27. The wiring to said clock input element is short.
When the clock buffer cannot be placed
After the clock is placed on the clock input device,
The input element is moved.
25. The clock signal distribution design method according to claim 25. 28. Each of said clock trunks and said clock
The delay between the main line driving buffer that drives each main line
Steps for arranging delay compensation wiring to equalize in the path
28. The method according to claim 22, wherein
The clock signal distribution design method according to any one of the above. 29. An operation performed based on at least circuit connection information.
Clock signals in the layout design of large-scale integrated circuits.
Clock signal for causing the processor to perform signal distribution design
Is a recording medium that stores a signal distribution design control program.
The clock signal distribution design control program is
A clock input for inputting the clock signal to a processor;
Clock trunk for supplying the clock signal to an element
Are arranged in a comb shape, and the delay value in the clock main line is
The clock based on the target delay value calculated according to
A clock provided between the main line and the clock input element
Wiring between the clock buffer and the clock input element
And the type of the clock buffer is changed to the clock main line.
Characterized in that it is changed according to the delay value in
Recording medium recording lock signal distribution design control program
body. 30. The clock signal distribution design control program
The ram indicates to the processor the number of the clock input elements.
The large-scale integration so that is a predetermined number set in advance.
The circuit is divided into a plurality of divided areas to divide the circuit area.
30. A trunk trunk line is provided.
Recording of clock signal distribution design control program
Medium. 31. The clock signal distribution design control program
A ram is provided to the processor before each of the plurality of divided areas.
When the number of the clock input elements exceeds the predetermined number,
Claims characterized by further dividing the divided area
The clock signal distribution design control program described in Item 30 is described.
The recording medium on which it was recorded. 32. The clock signal distribution design control program
Ram to the processor, wherein the plurality of divided areas
Place the clock in a place where the wiring to the clock input element is
31. A buffer according to claim 30, further comprising:
32. The clock signal distribution design control program according to claim 31,
A recording medium on which a ram is recorded. 33. The clock signal distribution design control program
RAM is connected to the processor to the clock input device.
When it cannot be placed in a place where the line becomes short,
Search for the place where it can be placed and
33. The clock according to claim 32, wherein the clock is arranged.
A recording medium on which a signal distribution design control program is recorded. 34. The clock signal distribution design control program
RAM is connected to the processor to the clock input device.
When the clock back cannot be placed where the line becomes short,
After placing the device over the clock input element.
The clock input element is moved.
33. A clock signal distribution design control program according to claim 32.
A recording medium on which a system is recorded. 35. The clock signal distribution design control program
The ram provides the processor with each of the clock trunks and the
Between the main line driving buffer that drives each clock main line
A delay compensation wiring is provided to equalize the delay in the circuit.
Any of claims 29 to 34 characterized in that
Record the clock signal distribution design control program described
Recording medium.