JP3103416B2 - Priority encoder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a priority encoder (encoding circuit with priority), and more particularly, to a content addressable memory (content addressable memory).
The present invention relates to a priority encoder used to encode a plurality of matching address signals such as emory (CAM) in order according to a predetermined priority and obtain a binary address output.

[0002]

2. Description of the Related Art Conventionally, as a semiconductor memory circuit having a function of performing coincidence detection of search data and stored data in parallel with all bits and outputting a storage address or data of the matched data, an associative memory, that is, an associative memory, has been proposed. Parallel CAM (content access memory: Conte
nt Addressable Memory) is well known (see “Design of CMOS Ultra LSI”, edited by Takuo Sugano, Tetsuya Iizuka, Baifukan, P176-P177).

[0003] Content addressable memories (CAMs) are searched by content, not by physical memory address. Therefore, the basic function of the CAM is to input search data in the opposite manner to a normal memory and to output the address of a word in which data matching the search data is stored. However, the number of matching words is not limited to one, and a plurality of words may match. When a match is obtained in a plurality of words as described above, a normal encoder cannot obtain a correct encoded output. For this reason,
Before applying signals to a normal binary encoder, it is necessary to set an appropriate order so that only one signal becomes an ON potential, and the signals are sequentially switched and output in synchronization with a clock signal.

For this reason, a priority encoder (address encoder with priority) is used. For example, the conventional priority encoder 100, a combination of a plurality of inverters 102 and NAND gate 104 as shown in FIG. 12, the input signal A _3, A _2, A
_If A ₃ has the highest priority (priority) among A ₁ and A ₀ and decreases in the order of A ₂ and A ₁ , and A ₀ has the lowest priority, a plurality of coincidence signals with the input signals A _{3 to} A ₀ are assumed. Even if “1” H (high) is input, the address with the highest priority among the addresses whose input signal is “1” is output. That is, the priority encoder 100 has, for example, A ₃ = "0"
If A ₂ = “1”, then whatever the input signals A ₁ and A ₀ with lower priorities are, that is, “1” H (high) (match), “0” L (Row) (unmatched), regardless of the signal value, the address (N, X ₁ , X ₀ ) of the input signal A ₂ having the highest priority = (0, 1, 1)
0) is output.

In such a priority encoder, a truth table is directly realized by using a NAND gate 104. Even if a plurality of 1s exist in an input signal, the address of the input signal having the highest priority is always used. Although an output can be obtained, as the number of input signals increases, the circuit configuration rapidly becomes complicated, and there is a problem that the number of necessary elements such as gates becomes enormous. For example, in such a priority encoder, the gate of a low-priority input signal is configured to receive all higher-priority input signals. All the input signals are input to the provided NAND gate. When the number of input signals increases, it is impossible to form this gate in one stage, and it is necessary to increase the number of stages. To increase.

For this reason, only the address having the highest priority among input signals in which 1 exists in a plurality of addresses is set to 1,
A circuit that outputs a signal in which all input signals of other addresses are 0, which is referred to as a priority circuit in this specification, that is, a portion to which the priority is assigned is separated as a priority circuit, and thereafter, the output 1 A priority encoder configured to encode a signal in which only one address is 1 (a signal with priority) by an ordinary address encoder is disclosed in Japanese Patent Publication No. 02-47038. In the priority circuit disclosed herein, as shown in FIG. 13, the encoding circuit element provided for each signal input terminal has the same circuit configuration for all terminals regardless of the priority level. Such a priority circuit consists of an address on one side,
In the illustrated example, the lower the address, the higher the priority.

That is, the priority times shown in FIG.
The path 110 is connected to each signal input terminal IN0, IN1, IN2.
Is controlled by the input signal input from the
P-channel MOS transistor 112
₀ , 112₁ , 112_Two Connected serially,
Control signal input terminal P₀ Is “1” (H), and each
The input signal is provided between the transistors (on each upper side in the figure).
And these PMOS transistors 112₀ ~ 112_Two When
N-channel MOS transistor controlled exclusively (reverse)
Star 114₀ , 114₁ , 114_Two And the other end
Ground (fixed to “0” L potential) and each PMOS transistor
112₀ , 112₁ , 112_Two Below, that is, each code
Control signal input terminal P of the integrated circuit element₀ , P₁ , P_Two of
Signal and each signal input terminal IN0, IN1, IN2
Node Q connected through an NMOS transistor
₀ , Q₁ , Q_Two AND gate 1 for ANDing with the signal of
16 ₀ , 116₁ , 116_Two And output the result as OUT
0, OUT1, and OUT2. here
Then, if 1 is input to a plurality of IN0, IN1, IN2
However, for example, IN0 = “0”, IN1 = IN2 =
If it is “1”, first, the clock signal C₁ By
Node Q₀ , Q₁ , Q_Two Signal state is (Q₀ , Q₁ ,
Q_Two ) = (0,1,1) and the PMOS transistor
112₀ , 112 ₁ , 112_Two Is on, off, off, N
MOS transistor 114₀ , 114₁ , 114_Two Ha
Off, on, on, propagation control signal input terminal (P₀ , P₁ ,
P_Two ) = (1,1,0), and as a result, the output terminal
(OUT2, OUT1, OUT0) = (0, 1, 0)
And an output signal (0, 1, 0) is output. Sand
That is, an output signal for IN1 = “1” having a high priority
(0, 1, 0) is output first.

Next, a reset circuit 118 composed of an NMOS transistor to which the output signal (0, 1, 0) is input.
_0, 118 _1, 118 ₂ by the node (Q _0, Q _1,
Q ₂ ) = (0, 0, 1), that is, the output signal is “1”
Only the node Q ₁ is becomes "0" since the resetting "1". Therefore, the PMOS transistor 112
₁ changes from off to on, and the NMOS transistor 114 ₁ changes from on to off, that is, the propagation control signal “1”
Propagation to terminal P ₂ , propagation control signal input terminal P ₂ = 1
Output terminals (OUT2, OUT1, OUT0)
= (1,0,0), and the next priority IN2 = “1”
Is output as (1, 0, 0). In this way, even when a plurality of "1" are input to the signal input terminals IN0 to IN2, the lower one is preferentially selected, and a signal in which only one of the output terminals OUT0 to OUT2 is "1" is selected. Output sequentially. Here, output signals (0, 1, 0) and (1,
(0,0) is encoded by, for example, the conventional address encoder 90 shown in FIG. Even if the number of inputs further increases, the same operation may be performed by adding exactly the same priority circuit elements.

[0009]

Incidentally, the priority circuit shown in FIG. 13 has a uniform circuit configuration in all the priority circuit elements, and is combined with a conventional address encoder 90 shown in FIG. Even when used as an encoder, it has a smaller number of elements and operates at relatively high speed as compared with the configuration of the priority encoder shown in FIG. As the number of inputs increases, the above-described priority circuit elements are connected as many as the required number of inputs. Accordingly, the propagation control signal for determining the priority needs to be transmitted to the PMOS transistor 112 serially connected from the bottom to the top in response to this.
An output signal in which only one address is 1 is output, and the priority change after resetting by the reset circuit 118 using the output becomes slow. That is, there is a problem that it takes time until an output signal having the next priority is output.

Therefore, the present invention solves the above-mentioned problems of the prior art, and has a simple structure for sequentially outputting a plurality of addresses to which a coincidence signal is output one by one in a content addressable memory (CAM). It is an object of the present invention to provide a priority encoder which is composed of a small number of elements and operates at a high speed and can be applied to a large-capacity CAM.

[0011]

In order to achieve the above object, a first aspect of the present invention is to provide a semiconductor device in which a plurality of input signals include a signal to be encoded in at least two addresses. divided into an output signal only in the coded signal to be one address the input signal is included, and priority means for sequentially outputting with a predetermined priority, those
Encoding means for receiving, as an input signal, an output signal containing a signal to be coded only in the one address output with priority given by the priority means, and coding and outputting the address; Separate each
A priority encoder having to, the priority means, said plurality of the number of input signals smaller than the input signal by using the priority circuit of small units for receiving hierarchically structured, small unit priority circuit of the lower layer Is used as one input signal of the small unit priority circuit of the upper hierarchy, and the output signal of the priority circuit of the upper hierarchy at the address corresponding to the address of this one input signal is used as the enable signal of the priority circuit of the lower hierarchy. A priority encoder is provided.

Here, the priority circuit includes a plurality of priority circuit element strings, and the priority circuit element strings use a signal input terminal and an input signal input to the signal input terminal. a first switch circuit which generates a propagation control signal to before or after the priority circuit element sequence Te, the input signal
A second switch circuit that is controlled exclusively by the first switch circuit and propagates a propagation control signal propagating from the subsequent or previous priority circuit element sequence to the previous or subsequent priority circuit element sequence, respectively . A logic operation is performed between the propagation control signals before and after the priority circuit element sequence or between one of these propagation control signals and the input signal, and the result is output when the enable signal is activated. It is preferable to have an arithmetic means.

A second aspect of the present invention is the above-mentioned priority encoder, wherein the priority means is N
The number of input signals of the small unit priority circuit of the highest layer is 2 ^a (a ≧ 1), the number of input signals of the small unit priority circuit of the lowest layer is 2 ^b (b ≧ 1), and the number of input signals of the middle layer is small. When the unit priority circuit is (N−2 (N ≧
2)) When the number of input signals is 2 ^c (c ≧ 0) in the hierarchy, the encoding means is attached to 2 ^a outputs of the priority circuit of the highest hierarchy, and the encoding is performed. the upper encoder circuit which encodes the upper a bits of the address should do signals, attached to the output of the 2 ^b the priority circuit of the lowest layer,
And lower encoding circuit for encoding the lower b bits of the address, 2 ^c of the priority circuit of the intermediate hierarchy
And a N-2 intermediate encoding circuit attached to the output of the book and encoding the middle C bits of said address.

Further, a third aspect of the present invention is the above-mentioned priority encoder, wherein the priority circuit, at least one of the lower encoding circuit, the intermediate encoding circuit of (N-2), and the upper encoding circuit. And a priority encoder provided with a partial encoder therebetween.

[0015] A fourth aspect of the present invention is directed to each of the above aspects.
A priority encoder, the priority circuit is to provide a priority encoder, wherein the one in which priority can be selectively defined in one direction or in the reverse direction.

In each of the above aspects, it is preferable that the priority circuit sets the propagation control signal output from the lowest or highest priority circuit element sequence as the logical sum output, and the priority circuit includes: It is preferable to have means for directly performing a logical operation on all the input signals to be inputted and outputting the result as a logical sum output.

[0017]

The priority of the first embodiment of the present invention
An encoder is a circuit in which the number of constituent elements of a priority circuit element (a circuit unit for assigning a priority (priority)) to one input signal is reduced, for example, transistors that operate exclusively (reversely) by an input signal. And the logic operation means detects the propagation state of the propagation control signal or the signal state of the input signal before and / or after one of the serially connected transistors.
A circuit capable of outputting an output signal in which only one address is "1" is constituted, a plurality of these circuit elements are collected (stacked) and grouped to constitute a small unit priority circuit. Are grouped hierarchically using the required number of priority circuits.

Here, if the M priority circuit elements are arranged in N layers, the number of possible input signals is M ^N. Therefore, in the priority encoder of the present invention, the priority changes at this time, but it takes time of the order of M ² in the priority circuit of the small unit, and since this is an N layer, M ² · N It takes time to order. In contrast, Tokuhei 02-47
In the case of a single layer without grouping as in the encoding circuit disclosed in Japanese Patent No. 038, the total number of input signals is M
^If it is ^N , the order of (M ^N ) ² = M ^2N is required. Therefore, according to the present invention, when the number of all input signals is large as in the case where the present invention is applied to a large-capacity CAM, the change of the priority can be made extremely fast. If the number N of layers is not so large, it is not necessary to use so many elements for layering as compared with the case of a single layer. In this way, from a large number of input signals in which a plurality of coincidence signals exist, an output signal in which a coincidence signal exists in only one address in the order of priority, that is, a signal with priority is selected.
They can be output sequentially. Thereafter, the selected output signals are encoded one by one. Thus, according to the present invention, a high-speed priority encoder with a small number of elements can be realized.

In the priority encoder according to the second aspect of the present invention, the encoding of a required number of bits is performed by an encoding circuit attached to each of the small priority circuits of each layer of the layered priority means. Do. Therefore, according to this aspect, not only can the priority of the input signal be speeded up, but also the coding of the output signal to be output can be speeded up, and the overall operation can be greatly speeded up.

In a priority encoder according to a third aspect of the present invention, the encoding circuit is attached to the priority circuit of the small unit of each hierarchy via a partial encoder for each priority circuit, so that an address line of the encoding circuit is provided. Can be reduced, and the encoding operation, and thus the overall operation, can be speeded up.

A priority encoder according to a fourth aspect of the present invention is a signal processing apparatus, comprising: a single-layer or multi-layer priority encoder having a transmission control input of a serially connected transistor in the grouped priority circuit elements of the priority circuit. The direction in which the signal propagates can be controlled, and the logical operation means can be controlled by an exclusive OR (exclus).
ive) OR) circuit, the priority direction can be switched bidirectionally. Therefore, according to this aspect, a specific search such as a large-capacity CAM, a bidirectional search, and the like can be freely performed.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a priority encoder according to the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings.

FIG. 1 is a schematic diagram of an embodiment of the priority encoder according to the first aspect of the present invention. As shown in the figure, the priority encoder 10 of the present invention
Receive only one input signal with multiple match signals
Priority circuit means 12 for sequentially outputting an output signal containing two coincidence signals with a predetermined priority (priority) according to a predetermined priority; Encoding circuit means 14 for encoding an address.

The priority circuit means 12 is composed of three layers. The lowest layer is composed of sixteen 4-input small-unit priority circuits (hereinafter referred to as unit circuits) 16, and the intermediate layer is composed of four similar units. It comprises a four-input small unit priority circuit 18, and the uppermost layer comprises one similar four-input small unit priority circuit 20. Therefore, the priority circuit means 12 determines that the priority
The six unit circuits 16 can have 64 inputs. That is, the 64 inputs of the circuit means 12 are grouped into 16 groups, four in one group. Then, a small unit priority circuit 16 using four inputs of one group as a unit is formed, and 16 units are used. The sixteen small unit priority circuits 16 are grouped into four groups, and one group is composed of four unit circuits 16, and the four unit circuits 16 forming one group are divided into four groups.
Are connected to one small unit priority circuit 18 constituting the intermediate layer. And these four unit circuits 1
8 are connected as a group to the small unit priority circuit 20 of the highest hierarchy.

The priority circuit means 12 shown in FIG.
Has 64 inputs and 4 input unit circuits 16, 18
Although the present invention is not limited to this, the number of inputs, the number of elements of the unit circuit, and the number of layers can be appropriately selected as necessary. The hierarchical structure may be appropriately selected according to the total number of inputs and the number of inputs of the unit circuit to be used. In addition, the unit circuits 16, 18, and 20 constituting each layer have the same number of inputs, but the present invention is not limited to this and may be different. The smaller the number of inputs of the unit circuit, the more convenient it is to increase the priority change speed.However, if the number is too small, the number of required unit circuits will increase and the number of required layers will increase. Is not preferable because it increases. Therefore,
In the present invention, the total number of inputs and the number of unit circuit inputs (may be one type or multiple types) that can be used for each layer are selected, and the number of layers is determined so as to conform to this.
What is necessary is just to make it a multi-layer structure.

The small unit priority circuit 16 is shown in FIG.
As shown in (a), the upper part, that is, the upper part has a higher priority, and the four input units I ₀ , I ₁ , I
₂ and I ₃ , four output terminals O ₀ , O ₁ , O ₂ and O ₃ , an enable signal input terminal e and a logical sum (OR) output terminal or, and four priority circuit elements 22 (2
2 ₀ , 22 ₁ , 22 ₂ and 22 ₃ ). Wherein one priority circuit element (hereinafter, referred to as circuit element) 22, explaining the second circuit element 22 ₁ as a representative example, an inverter 24 for inverting an input signal inputted to the input terminal I _1, the inverter 24 The output and its gate electrode are connected and mutually exclusive (reverse) by the input signal
N-channel MOS transistor 26 (N
₁ ) and a P-channel MOS transistor 28 (P
₁ ) and the source and drain electrodes of the NMOS transistor 26 as inputs and the output terminal O ₁ as output,
A logic operation circuit 30 activated by an enable signal input from an enable signal input terminal e.

[0027] Here, one electrode of the NMOS transistor N ₁ (e.g., source electrode) is connected at node Q ₀ other electrode of the NMOS transistor N ₀ of the upper circuit element 22 ₀ (e.g., a drain electrode) to, NMOS the other electrode of the transistor N ₁ (e.g., the drain electrode),
One electrode of the lower circuit component 22 _{and second} MOS transistor N ₂ at node Q ₁ (e.g., source electrode) is connected to. Thus, the NMOS transistors N ₀ , N ₁ , N
₂ and N ₃ are serially connected by nodes Q ₀ , Q ₁ and Q ₂ . The node Q ₃ below the NMOS transistor N ₃ is connected to the OR output terminal or. The upper (one) electrode (eg, source electrode) of the uppermost NMOS transistor N ₀ is fixed to a potential (signal state) indicating “0” or grounded. Whereas one of the electrodes (e.g., source electrode) of the PMOS transistor _{P 0, P 1, P 2} , P 3 is connected to "1" or is fixed to the potential (signal state) shown, or to the power source V _pp, other (For example, a drain electrode) are connected to nodes Q ₀ , Q ₁ , Q
It is connected to _2, Q _3. Thus, the unit circuit 16 having four inputs and four outputs is configured.

Next, the priority of the unit circuit 16
Operation, that is, when a plurality of match signals “1”₀ ~
I_Three , Only the highest priority address
Is the match signal "1" and the output operation with the priority
explain about. The circuit element 22 of the unit circuit 16
₁ Note that I₁ N if input is 1₁ Transis
26 turns off and P₁ The transistor 28 turns on. Obedience
What this P₁ Q by transistor 28₁ Node is
Set to 1. I₁ N if input is 0₁ Transis
26 turns ON and P₁ The transistor 28 turns off.
Therefore, Q₁ The node is the next higher Q₀ Same as the logical value of the node
Be the same. If I_k If the input is 1, Q_k Is 1
So Q after that_n (N ≧ k + 1) is I_n Is 1
No matter whether it is 0 or 1 it can only be 1. That is, I
_{k + 1} = 1, the node Q_{k + 1}(Signal state of) is 1,
While I_{k + 1} = 0 if Q_{k + 1} = Q_k And Q_k = 1
Q _{k + 1} = 1.

As a result, as shown in FIG.
The input is 1 and the corresponding serial connection NMO
When the S transistor 26 (N) is OFF, the propagation control signal “0” is transmitted to the uppermost NMOS transistor 26, but the propagation control signal is transmitted to each lower Q node. “0” is not transmitted and all become “1”. Therefore, it is sufficient that the logical operation circuit 30 detects how far the control signal “0” is transmitted. O if 4 inputs I ₀ ~I ₃ of the unit circuit 16 is all "0"
The control signal "0" is transmitted to the R output terminal or to inform that there is no "1" in all four input signals. In order to form a hierarchy, this OR output or may be used as the input of the upper unit circuit 18.

FIGS. 2B and 2C are schematic diagrams of the unit circuits 18 and 20, respectively forming the intermediate layer and the uppermost layer. The unit circuits 18 and 20 shown in the figure have exactly the same configuration as the unit circuit 16 of the lowest hierarchy shown in FIG. 2A except for signals input / output to the input / output signal terminals. Illustration of the configuration is omitted. Unit circuit 1 shown in FIG.
8 input terminals or ₀ , or ₁ , or ₂ , or ₃ are shown in FIG.
Are OR outputs or ₀ , or ₁ , or ₂ , and or ₃ of the four unit circuits 16 ₀ , 16 ₁ , 16 ₂ , and 16 ₃ of the unit circuit 16 constituting the lowest hierarchy. Output Ot _k of this unit circuit 18 (k = 0, 1, 2, 3)
To the enable terminal e _{k of} the circuit 16 _k (k = 0, 1, 2, 3) corresponding to the input signal or _k (k = 0, 1, 2, 3)
(K = 0, 1, 2, 3), the k-th circuit 16 _k can be selectively activated only when Ot _k = 1. Therefore, 1 is included in the or input of this unit circuit 18.
The presence or absence of the OR can be seen with the OR output.
The output is ultimately the multiple unit circuits 1
This indicates whether or not there is a signal of 1 among all the I input signals of No. 6.

FIG. 2C shows another unit circuit 20 of the higher hierarchy which receives the OR output of the circuit 18 as an input. The configuration of this unit circuit 20 is shown in FIGS. 2A and 2B. As described above, the configuration may be exactly the same as the unit circuits 16 and 18 shown respectively. FIG.
The unit circuit 20 shown in (c) outputs the OR outputs of all four unit circuits 18 constituting the intermediate hierarchy to the OR input O.
R _k (k = 0, 1, 2, 3) input and this O
Output O corresponding to R input OR _k (k = 0, 1, 2, 3)
UT ₀ , OUT ₁ , OUT ₂ , and OUT ₃ are input to respective enable signal inputs E as enable signals of all four unit circuits 18 in the middle hierarchy. In this way, whether or not there is 1 in the OR input OR _k of the unit circuit 20 is determined by the OR output GO of the unit circuit 20.
You can see it in R. The enable signal ENB of the unit circuit 20 itself is OUT _k (k = 0, 1, 2, 3)
Output all "0", that is, OR output GO
A predetermined clock signal is separately input until R becomes “0”. Conversely, the output OUT _k of the unit circuit 20 is “1”
Is output, the signal having only one "1" at the highest priority address selected from the input signals of the priority circuit means 12 (hereinafter referred to as a signal with priority) outputs "1". This means that a small unit priority circuit having "1" (coincidence signal) exists in the lower group corresponding to the address.

Here, the logical operation circuit 3 shown in FIG.
0 is an NMOS connected serially as in the example of FIG.
The signal state between the drain and the source of the transistor 26 (N ₁ ), that is, the exclusive OR of the logical values between the nodes Q ₀ and Q ₁ (Exclusive OR)
R) (Exclusive OR gate)
R gate: anti-coincidence circuit) 32, and A which takes the logical product of the output of the exclusive OR gate 32 and the enable signal e
It comprises an ND gate 34. This logical operation circuit 30
Then, the node Q ₀ does not match the node Q ₁ , that is, the propagation control signal “0” is propagated up to the node Q ₀ of the NMOS transistor 26 (N ₁ ) of the circuit element 22 ₁ , but up to the node Q ₁ When the propagation control signal “0” is not propagated, the exclusive OR gate 32 outputs “1”. At the same time, if the enable signal e is “1”, that is, active, the AND gate 34 outputs “1” to the output terminal O ₁ . 1 "is output. If the node Q ₀ matches the node Q ₁ or the enable signal e is “0”, the output of the output terminal O ₁ is “0”. The logical operation circuit 30 is not limited to the example illustrated in FIG. 3 and may be configured to perform a desired logical operation by combining various gates. The input of the logic circuit 30 is not limited to between the node Q ₀ and the node Q _1, may be the one with the input signal or the inverted value thereof, the contents of the logical operation, signal What is necessary is just to select suitably according to a value.

By using the priority circuits 16, 18, and 20 of the small units configured as described above, a circuit configuration for hierarchically selecting the priority as described above is realized.
The speed can be significantly increased as compared with the case where all the N transistors 26 are serially connected in a single layer in the form of the unit circuit 16. As the or output or OR output can be used a signal state of the node Q _M of the circuit element 22 _M of the lowest priority circuit 16 (lower side) as shown in FIG. 2 and FIG. 4 (Boolean) . As described above, the use of the logical value of the node Q _M has a great advantage that a special circuit for obtaining an OR output (OR output) is unnecessary, but the present invention is not limited to this. In order to further increase the speed, a normal OR gate 36 or the like may be used to directly obtain an OR output from the input signals I ₀ , I ₁ , to I _M as in the priority circuit 16 shown in FIG. Then, the signal transmission between the layers becomes faster, and the speed can be further increased. This is because the number M of the inputs I _{0 to} I _M does not increase so much because the priority circuit of a small unit can be used by hierarchization. That is, by using the OR gate 36, the OR output can be speeded up, the input to the upper hierarchy can be speeded up, and the overall response can be sped up.

Next, from an input signal having a plurality of coincidence signals,
Highest priority output with one match signal
When a signal is output, the next higher priority match signal is
If the dresses are in the same small unit priority circuit
Reset the input using the output.
No. That is, for example, the prioritizer shown in FIG.
In the circuit 16,₁ = 1, I_Three = 1
And the output O when the enable signal e is "1".₁ only
It is “1”. This O₁ Output directly to circuit element 22
₁ Input I₁ And reset it, I
₁ = 0 and therefore N transistor 26 (N₁ ) Is on,
p transistor 28 (p₁ ) Is turned off and the node Q₁ 
= Q₀ = 0, where N transistor N_Two Is on
So node Q ₀ = Q₁ = Q_Two = 0, node Q_Three Only one
And the next priority I_Three = 1 is selected as the next output signal.
Bar, O_Three = 1.

On the other hand, the matching signal having the next highest priority is
FIG. 6A shows a case where the signal exists in the priority circuit.
This will be described with reference to FIGS. First, the highest priority match
The signal H is the higher priority circuit 16₀ Input terminal I
_Two (Third), and the next priority match signal H
Priority circuit 16₁ Was at the second input terminal of
Then, now, the unit circuit 16₀ Enable signal
e₀ Is H, the unit circuit 16₀ The third circuit element 22 of
_Two Input I_Two = H, the logic of the logical operation means 30
Output of the active OR gate 32, that is, the AND gate 3
4 is also H, and therefore the output O of the AND gate 34 is_Two Also
H. On the other hand, in the unit circuit 18, the enable signal
Signal E = H, input or in the first circuit element₀ = H, AN
The input of the D gate 34 = H, and therefore the output Ot₀ = H
So e₀ = H, but the output Ot of the first circuit element₀ 
= H, so that the input or₁ 
= H, the input to the AND gate 34 = L,
Ot₁ = L, so e ₁ = Ot₁ = L. Follow
And the unit circuit 16₁ Then, the second circuit element 22₁ 
Is the highest priority, AND input = H from input = H.
However, the enable signal e₁ = L, output O
₁ = L and is in a waiting state.

Next, the circuit of the unit circuit 16 ₀ element 22
_After the output O _{2 of 2} is selected and output as an output signal with priority, the corresponding input I ₂ is reset, changes from H to L, and I ₂ = L. This gives O ₂ = L,
In addition, since I ₃ = L, or ₀ = L, the unit circuit 18
Since the first input or ₀ = L (even if the input to the AND gate 34 is L and E = H), the output Ot ₀ = L,
Output Ot ₁ = H next to the second circuit element, e ₁ = becomes H, the second circuit element of the unit circuit 16 ₁ 22 ₁
Changes to H, indicating that the input signal of the second priority is selected. In this manner, the priority can be easily changed between different unit circuits by changing the enable signal. Of course, at this time, prioritization in the priority circuits of all layers is performed in parallel for all of the layers. By doing so, the speed can be increased.

Next, a priority encoder according to a fourth embodiment of the present invention will be described. The priority circuit means 12 of the priority encoder according to the present embodiment is composed of a priority circuit 40 shown in FIG. The priority circuit 40 shown in FIG. 7 includes a PMOS transistor 28 (p ₀ , p ₁ ,
p ₂ , p ₃ ) and the nodes Q ₀ , Q ₁ , Q ₂ , Q ₃ and the serially connected NMOS transistor 26
2 (a) and FIG. 3 except that each end of the priority circuit 1 is grounded via a gate.
6 has the same configuration as that of No. 6, the same components are denoted by the same reference numerals, and description thereof is omitted.

In the priority circuit 40, since the circuit elements 22 (22 ₀ , 22 ₁ , 22 ₂ , 22 ₃ ) have exactly the same configuration, the second circuit element 22 ₁ will be described as a representative example. ₁ ) is P
Are connected via a MOS transistor 42 ₁ to the node to Q ₁ lower, it is also connected to the upper node Q ₀ through the PMOS transistor 44 _1. The PMOS transistors 42 ₀ , 42 ₁ , 42 ₂ , 42 ₃ connected to the lower side
Have their respective gate electrodes connected to one control signal line 46, and the PMOS transistors 44 ₀ ,
44 _1, 44 _2, 44 ₃ is the gate electrode of each of which is connected to one control signal line 48. In the priority circuit 40, the uppermost NMOS transistor N ₀
The upper electrode of the NMOS transistor N ₃ is grounded (or fixed to “0” potential) via the transistor 50, and the lower electrode of the lowermost NMOS transistor N ₃ , that is, the node Q ₃ is also grounded via the transistor 52 (or “0”). (Fixed to "potential").

The priority circuit 40 having such a configuration
In FIG. 8A, as shown in FIG.
To control the PMOS transistors 42 ₀ , 42 ₁ , 42
_2, 42 ₃ is turned on (ON), further the transistor 50
Is turned on, the propagation control signal “0”
8 can be configured to propagate from top to bottom, and the higher the priority, the higher the priority.
As shown in (b), the control signal line 48 is controlled to
The S transistors 44 _0, 44 _1, 44 _2, 44 ₃ is turned on (ON), further by turning on (ON) the transistors 52, configured to propagation control signal, "0" is propagated from bottom to top , The lower the priority, the higher the priority. By doing so, it is possible to output the matching address from both directions.

Next, a priority encoder according to a second embodiment of the present invention will be described. FIG. 9 is a configuration diagram of an embodiment of the priority encoder according to this aspect. The priority encoder 60 of the present invention shown in FIG.
The priority encoder 12 shown in FIG. 1 uses the priority circuit means 12 and the address encoder 14 does not use the conventional address encoder shown in FIG. 11, but expresses required bits for each layer. It is. That is, in this embodiment, when the priority circuit means is composed of N layers, the number of inputs of the small unit priority circuit of the highest hierarchy is 2 ^a (a ≧ 1) or less, and the number of inputs of the small unit priority circuit of the lowest hierarchy is 2 ^b (b ≧
1) Hereinafter, the number of inputs of the small unit priority circuit of the intermediate layer is 2 ^c (c ≧ 0) or less and the intermediate layer is N−2
When there are (N ≧ 2) hierarchies, an encoding circuit is provided for each hierarchy to encode upper a bits, lower b bits, and intermediate (N−2) × c bits, respectively.
The a, b, and c address lines are independently controlled for each layer by using the ground transistor by the output of the small unit priority circuit constituting each layer. The output lines of the priority circuits in each of the small units control the address lines using ground transistors in accordance with the signal states thereof, so that the address lines express "0" or "1".

Priority encoder 1 shown in FIG.
Since the 0 priority circuit means 12 has 64 inputs, 6 bits are required for address code conversion, and 6 address lines are required. When using conventional address encoder, 1 of the 6 address lines and the lowermost layer
By connecting four output lines of each of the six priority circuits 16, that is, a total of 64 output lines via transistors according to a predetermined method, a 6-bit address encoder can be configured. As described above, the priority encoder of the present invention includes, for example, FIG.
However, the number of transistors connecting the output line and the address line increases as the number of inputs increases.

For this reason, the priority encoder 60 shown in FIG. 9 of this embodiment has an address encoder 62 for encoding 2 bits for each layer of the priority circuit means 12 having the above-mentioned three-layer structure. If a coincidence output is included, an output signal with priority is output.
The priority circuit means 12 has one output terminal for outputting “1” H (high) for each layer among the priority circuits 16, 18, and 20 constituting each layer. Accordingly, the 16 priority circuits 16 of the lowest hierarchy are connected to the two address lines 71 and 70 that determine the lower two bits A ₁ and A ₀ . The four priority circuits 18 of the middle hierarchy are connected to two address lines 73 and 72 for determining A ₂ and A ₃ of two intermediate bits. The priority circuit 18 of one uppermost layer stores the upper two bits A
_5, is connected to two address lines 75, 74 to determine the A _4.

[0043] In each hierarchy where representative connection between one priority circuit and two address lines and the connection priority circuit of typically lowest hierarchy is identical 16 ₀ and address lines 71 and 70 This will be described as an example. The first output line O ₀ priority circuit 16 ₀ are grounded address lines 71 and 70 (or "0" fixed potential)
Connected to the gate electrodes of the transistors 63 and 64. Therefore, only the output of the first output line O ₀ is “1” [(O
_{When (0} , O ₁ , O ₂ , O ₃ ) = ( ₁ , ₀ , ₀ , ₀ )], the transistors 63 and 64 are turned on, and A ₀ = A ₁ = 0. Then, the second output line of the priority circuit 16 ₀ O
₁ indicates that the address line 71 is grounded (or fixed at "0" potential)
Connected to the gate electrode of the transistor 65. Therefore, only the second output line O ₁ is “1” [(O ₀ , O ₁ , O
_[2 , O ₃ ) = ( ₀ , ₁ , ₀ , ₀ )], the transistor 65 is turned on, and (A ₁ , A ₀ ) = (0, 1). Further, the third output line O ₂ of the priority circuit 16 ₀
Indicates that the address line 70 is grounded (or fixed at “0” potential)
Connected to the gate electrode of the transistor 66. Therefore, only the third output line O ₂ is “1” [(O ₀ , O ₁ , O
If ( ₂ , O ₃ ) = ( ₀ , ₀ , ₁ , ₀ )], the transistor 66 is turned on, and (A ₁ , A ₀ ) = (1, 0). Here, only the fourth output line O ₃ is “1” [(O ₀ , O
₍₁ , O ₂ , O ₃ ) = ( ₀ , ₀ , ₀ , ₁ )], then (A ₁ , A ₀ ) = (1, 1).

The address encoder 62 can be configured by performing such a connection for each priority circuit for two address lines for each layer. Here, in the address encoder 62, the address lines 70 to 70
Since the number of transistors used for connection between the priority circuit 75 and each of the priority circuits 16, 18, and 20 is four for one priority circuit, 64 transistors are used in the lowest hierarchy,
There are 16 in the middle tier and 4 in the top tier, for a total of 84
On the other hand, in the case where all of the six address lines are connected to the 16 priority circuits 16 in the lowest hierarchy as in the conventional address encoder, 192 are required. Therefore, the magnitude of the speed-up effect of this embodiment is clear.

Next, in the priority encoder 80 according to the third embodiment of the present invention, as shown in FIG. 10, a portion is provided between the output line of the 4-input priority circuit 16 and the two address lines 70 and 71. An encoder is provided. For example, the first and second output lines O ₀ priority circuit 16 ₀
And O ₁ are connected to the input of an OR gate 81,
The output of gate 81 is connected to the gate electrode of ground transistor 82 on address line 71. Meanwhile, the first and third output lines respectively, and the O ₀ and O ₂ of the priority circuit 16 ₀ is connected to the input of OR gate 83, the output of OR gate 83 is connected to the gate electrode of the grounded transistor 84 address lines 70. By using such a partial encoder, the number of ground transistors connected to one address line can always be one. On the other hand, when the partial encoder is not used, when the number of inputs of the priority circuit is 4, 8, and 16, the number of transistors connected to one address line is 2, 4, and 8, respectively.
Individual. Therefore, by providing a partial encoder for each priority circuit, the number of ground transistors connected to the address line can be reduced, and the encoding operation can be speeded up.

As a priority circuit which constitutes the priority circuit means of the priority encoder of the present invention, a priority circuit having an N-channel transistor serially connected as shown in FIG. However, the present invention is not limited to this, and as shown in FIG. 13, a priority circuit having a configuration in which P-channel transistors are serially connected is structured in a hierarchical structure as a small-unit priority circuit, or a configuration in which bidirectional priority is possible. Are also included in the scope of the present invention.

Although the priority encoder according to the present invention has been described with reference to various embodiments, the present invention is not limited to this. For example, the priority circuit, the number of inputs of the encoding circuit, the number of layers, the configuration, and the like. It goes without saying that design changes and various improvements can be made without departing from the spirit of the present invention.

[0048]

As described above in detail, according to the first aspect of the present invention, in the content addressable memory (CAM), a plurality of addresses from which a coincidence signal is output are sequentially output one by one. It is possible to provide a priority encoder which has a simple configuration, is configured with a small number of elements, and operates at high speed, and can be applied to a large-capacity CAM.

Further, according to the second and third aspects of the present invention, the number of transistors connected to the address line can be greatly reduced as compared with the prior art, and a high-speed encoding operation can be performed with a simple configuration. It can be a priority encoder with an address encoder.

Further, according to the fourth aspect of the present invention, prioritization can be performed in both directions, and a large capacity C
A search such as an AM, in particular, a specific search can be efficiently performed, and the degree of freedom of the search can be increased .

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of an embodiment of a priority encoder according to the present invention.

FIGS. 2A, 2B, and 2C are schematic configuration diagrams of an embodiment of a small-unit priority circuit used in a priority encoder according to the present invention.

FIG. 3 is a configuration diagram of an embodiment of a logical operation circuit used in a small-unit priority circuit of the priority encoder according to the present invention.

FIG. 4 is a partial configuration diagram of another embodiment of the priority circuit used in the priority encoder according to the present invention.

FIG. 5 is a partial configuration diagram of another embodiment of the priority circuit used in the priority encoder according to the present invention.

FIGS. 6 (a) and (b) are explanatory diagrams of prioritizing operation of a priority circuit used in a priority encoder according to the present invention.

FIG. 7 is a configuration diagram of another embodiment of the priority circuit used in the priority encoder according to the present invention.

FIGS. 8A and 8B are explanatory diagrams illustrating different usages of the priority circuit shown in FIG. 7;

FIG. 9 is a schematic configuration diagram of another embodiment of the priority encoder according to the present invention.

FIG. 10 is a partial configuration diagram of another embodiment of the priority encoder according to the present invention.

FIG. 11 is a configuration diagram of a conventional address encoder.

FIG. 12 is a configuration diagram of a conventional priority encoder.

FIG. 13 is a configuration diagram of a priority circuit of a conventional priority encoder.

[Explanation of symbols]

10 priority encoder 12 priority circuit means 14 encoding means 16,18,20,40 small unit priority circuit 22 priority circuit element 24 inverter _{26 N 0, N 1, N} 2, N 3 NMOS transistors 28 P _0, P _1, P ₂ , P ₃ PMOS transistor 30 Logical operation circuit 32 Exclusive OR gate 34 AND gate 36 OR gate I Input terminal O Output terminal e Enable signal terminal or OR output terminal

Continued on the front page (58) Fields investigated (Int.Cl. ⁷ , DB name) G11C 15/00-15/06 G06F 7/00 H03M 7/20 WPI (DIALOG)

Claims (7)

(57) [Claims] When a plurality of input signals include a signal to be coded at at least two addresses, the input signal includes a signal to be coded at only one address. divided, and priority means for sequentially outputting with a predetermined priority, the Puraiorite
Receiving, as an input signal, an output signal containing a signal to be coded only in the one address, which is output with priority assigned by the encoding means, and separating the encoding means from the encoding means for encoding and outputting the address. A priority encoder, wherein the priority means is hierarchically structured using a small unit priority circuit that receives a smaller number of input signals than the plurality of input signals, and a logic of a lower unit small unit priority circuit is provided. The sum output is used as one input signal of the small unit priority circuit of the upper hierarchy, and the output signal of the priority circuit of the upper hierarchy at the address corresponding to the address of the one input signal is used as the enable signal of the priority circuit of the lower hierarchy. Priority encoder. 2. The priority circuit according to claim 1, wherein said priority circuit comprises a plurality of priority circuit element strings. The priority circuit element string uses a signal input terminal and a prior or subsequent priority signal using an input signal input to said signal input terminal. A first switch circuit for generating a propagation control signal to the circuit element sequence, and a propagation control which is exclusively controlled by the input signal to the first switch circuit and propagates from a subsequent or previous priority circuit element sequence A second switch circuit for propagating the signal to the preceding or subsequent priority circuit element sequence, and between the propagation control signals before and after the priority circuit element sequence, or between one of these propagation control signals and the input signal. Logic operation means for performing a logical operation and outputting the result when the enable signal is activated. Priority encoder according to claim 1 is. 3. The priority encoder according to claim 1, wherein said priority means is composed of N layers, and the number of input signals of a small unit priority circuit of an uppermost layer is 2 ^a (a ≧ 1); The number of input signals of the small unit priority circuit of the lowest hierarchy is 2 ^b (b ≧ 1), and the small unit priority circuit of the middle hierarchy is (N−2 (N ≧ 2))
When the number of input signals is 2 ^c (c ≧ 0), the encoding means is attached to 2 ^a outputs of the highest-order priority circuit, and
The upper encoder circuit which encodes the upper a bits of the address of the coded should do signal, attached to the output of the 2 ^b the priority circuit of the lowest layer, the lower the encoding circuit for encoding the lower b bits of the address And a N-2 intermediate encoding circuit attached to each of the 2 ^c outputs of the intermediate layer priority circuit and encoding an intermediate C bit of the address. 4. The priority encoder according to claim 3, wherein a portion is provided between the priority circuit and at least one of the lower encoding circuit, the intermediate encoding circuit of (N-2), and the upper encoding circuit. Priority with an encoder
Encoder. 5. The priority encoder according to claim 1 , wherein said priority circuit can selectively define said priority in one direction or the other direction. 6. The priority encoder according to claim 1, wherein said priority circuit sets said propagation control signal output from said lowermost or uppermost priority circuit element sequence as said OR output. 7. The priority encoder according to claim 1, wherein said priority circuit has means for directly performing a logical operation on all of said input signals and outputting as a logical sum output.