JP3101608B2 - Imaging device and imaging signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an image pickup apparatus for digitizing an image pickup signal and performing digital signal processing, and an image pickup signal processing circuit.

[0002]

2. Description of the Related Art Conventionally, the output of an image pickup device such as a two-dimensional CCD is digitized using an AD converter, and this is processed using a signal processing circuit using digital technology to obtain a television signal. 2. Description of the Related Art There has been proposed an imaging apparatus that performs focus adjustment, exposure adjustment, white balance adjustment, and the like using a video signal.

[0003]

However, in the above conventional example, focus adjustment, exposure adjustment,
Circuits for automatically adjusting white balance and the like are controlled by a microcomputer via different signal paths, which complicates the configuration of the entire image pickup apparatus and increases the number of integrated circuit chips used. And it is difficult to integrate. Therefore, it is an obstacle to the miniaturization of the entire imaging device, and although the control is performed by a microcomputer, the circuit and configuration are complicated, and it is hard to say that efficient control is broken. Met.

It is an object of the present invention to simplify a circuit configuration of an image pickup apparatus, simplify and efficiently connect a microcomputer and data communication, and further smoothly control an image pickup apparatus for processing an image pickup signal. It is another object of the present invention to provide an image pickup apparatus and an image pickup signal processing circuit which can perform the processing efficiently.

[0005]

According to the first aspect of the present invention, there is provided an imaging apparatus for converting a subject image into an electric signal, and an electric signal from the imaging apparatus. Image signal processing means for processing a signal to output an image signal including a synchronization signal, and forming a plurality of mutually different automatic adjustment signals based on signals in a plurality of frames of the image signal in the image signal processing means. A plurality of adjustment signal forming means, each adjustment signal forming means, a frame counter for counting the signal corresponding to the position of the frame,
A frame register for storing frame setting data, a plurality of adjustment signal forming means for setting the frame based on a comparison between the count value of the frame counter and the frame setting data stored in the frame register; Transmitting the signal for automatic adjustment from the adjustment signal forming means, and interface means for receiving the frame setting data and supplying it to the frame register, connected via the interface means,
Control means for transmitting the frame setting data to the frame register, receiving the automatic adjustment signal from the adjustment signal forming means, and adjusting the adjustment unit of the imaging means or the imaging signal processing means; Wherein the adjustment signal forming means performs an operation of updating the frame setting in a blanking period of the synchronization signal in synchronization with the synchronization signal of the imaging signal based on the frame setting data from the control means. It is characterized by.

Further, according to the invention described in claim 2 of the present application, the adjustment signal forming means and the interface means are integrated on the same integrated circuit.

According to a third aspect of the present invention, the adjustment signal forming means forms a signal for automatic focus adjustment.

Further, according to the invention described in claim 4 of the present application, the adjustment signal forming means forms a signal for automatic exposure adjustment.

According to the invention described in claim 5 of the present application, the adjustment signal forming means forms a signal for automatic white balance adjustment.

According to the invention described in claim 6 of the present application, the interface means inputs the automatic adjustment signal from the adjustment signal forming means via an internal bus, and inputs the automatic adjustment signal via a parallel bus. It is configured to output to control means. According to the imaging signal processing apparatus of the invention described in claim 7 of the present application, an imaging signal processing for processing an electric signal from an imaging unit that converts a subject image into an electric signal and outputting an imaging signal including a synchronization signal Means, and a plurality of adjustment signal forming means for forming a plurality of mutually different automatic adjustment signals based on signals in a plurality of frames of the imaging signal in the imaging signal processing means, wherein each adjustment signal forming means is A frame counter for counting a signal corresponding to the position of the frame, and a frame register for storing frame setting data, wherein the count value of the frame counter and the frame setting data stored in the frame register A plurality of adjustment signal forming means for setting the frame based on the comparison; And interface means for receiving the frame setting data from the control means and supplying it to the frame register, based on the frame setting data from the control means, The adjustment signal forming means performs the update operation of the frame setting in synchronization with the synchronization signal of the imaging signal during a blanking period of the synchronization signal. According to the invention described in claim 8 of the present application, the adjustment signal forming means and the interface means are integrated on the same integrated circuit. According to the invention described in claim 9 of the present application,
The adjustment signal forming means forms a signal for automatic focus adjustment. According to a tenth aspect of the present invention, the adjustment signal forming means forms a signal for automatic exposure adjustment. Further, according to the invention described in claim 11 of the present application, the adjustment signal forming means forms a signal for automatic white balance adjustment. According to the invention described in claim 12 of the present application, the interface means inputs the automatic adjustment signal from the adjustment signal forming means via an internal bus and sends the signal to the control means via a parallel bus. Is output.

[0011]

According to the first and seventh aspects of the present invention, when the adjustment of the image pickup apparatus is performed using the outputs of the plurality of adjustment signal forming means, the signals between the plurality of adjustment signal forming means and the control means are controlled. Since the number of paths can be greatly reduced, the circuit configuration of the entire imaging device can be simplified, and the reliability of the imaging device can be improved. Further, the setting of a plurality of frames for extracting the signal for automatic adjustment can be easily controlled from the control means via the interface means, and the frame setting operation does not adversely affect the operation of extracting the adjustment signal. Moreover, the adjustment signal forming means can be realized with a simple configuration.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 is a block diagram showing an embodiment of the present invention.

1 is an image pickup lens, 2 is an automatic focus (AF) motor for rotating a focus ring of the image pickup lens 1, 3 is an aperture, 4 is an IG meter for controlling the aperture of the aperture 3, and 5 is a minute color separation filter. And a two-dimensional color image pickup device including a CCD. However, the image sensor of the present invention has a CC
Not limited to D, but may be an image pickup tube or an XY address sensor. 6 is a CCD driver for driving the CCD 5, 7 is C
Correlated double sampling circuit (CDS) for removing clock and reset noise from photoelectric conversion output of CD5, 8
Is an automatic gain control amplifier (AGC) for amplifying the output of the CDS 7 in accordance with the control signal AGCC, 9 is a clamp circuit for fixing the black level of the input voltage to a predetermined voltage,
Reference numeral 10 denotes an integrated circuit that processes an input CCD output signal to form a predetermined color video signal, and 12 receives digital data related to a signal from the integrated circuit 10,
Further, a microprocessor unit (MPU) for controlling the integrated circuit 10 and further forming signals for controlling the AF motor 2 and the IG meter 4 and the AGC 8, 13 is an AF driver circuit for driving the AF motor 2, and 14 is an IG meter An IG driver circuit for driving 4, an output terminal 15 for a chrominance signal (C), and an output terminal 16 for a luminance signal (Y).

Reference numerals 100 to 126 denote internal circuit elements of the integrated circuit 10. Reference numeral 100 denotes a clock pulse input from the timing generation circuit 11, a horizontal synchronization pulse HD, a vertical synchronization pulse VD, and an NTS input from the MPU 12.
C, PAL switching signal N / P, blanking pulse BLK for forming a standard television signal, burst flag pulse BF, color subcarrier SC, line sequential according to clock pulses of various frequencies required inside integrated circuit 10 Signal ALT
And a synchronizing signal generator for forming a composite synchronizing signal CSYNC and the like.

Reference numeral 101 denotes an AD converter that generates a digital signal corresponding to an input signal. Circuits subsequent to the AD converter handle digital signals. Reference numeral 102 denotes a color separation and luminance signal synthesis circuit, which includes two delay lines of one horizontal line, a matrix circuit, and a switching circuit.
G and B are separated, and the luminance signal Yc is synthesized. Further, the luminance signals Y- and Y + shifted vertically and downward by one line from Yc are synthesized. A low-pass filter 103 performs band limiting and time-division sampling, and a white balance (WB) circuit 104 varies the gain of each time-division color channel.

Reference numeral 105 denotes a gamma knee circuit for performing gamma correction and level compression of a high-luminance portion. 106 receives a time-division signal and converts it into a continuous parallel signal of three channels (R, G, B). , A low-pass filter for further limiting the band, and 107 is a low-band luminance signal Y from red R, green G, and blue B.
A matrix circuit for synthesizing L1 and YL2;
A color difference matrix circuit for forming color difference signals RY and BY from B and YL2, a color correction circuit 109 including a gain control and a color correction matrix for the color difference signal, a low pass filter 110, and a color filter 111 for each color difference signal. Subcarrier (S
This is a modulation circuit which adds after modulating by C) and further adds a color burst.

Reference numerals 112 and 121 denote DA converters for converting digital signals into analog signals, reference numeral 113 denotes a gamma correction circuit for performing gamma correction on the three input luminance signals, and reference numeral 11 denotes a gamma correction circuit.
Reference numeral 4 denotes a high-pass filter that transmits only a predetermined high-luminance component of the luminance signal.
Non-linear processing 10 for compressing signals near zero level,
118 is a delay line for delaying the input signal by the delay time of the high-pass filter 114, 119 is an adder, 120
Is a fader for changing the gain of the luminance signal and performing a blanking process.

When the MPU reads signals necessary for control of automatic focus adjustment (AF), automatic exposure control (AE), automatic white balance (AWB), etc., of signals from various parts of the integrated circuit 10, This is a preprocessing unit that performs processing in such a manner that data can be easily transferred to and processed by the MPU. Reference numerals 123 to 126 are provided in the preprocessing unit 122, 123 is an AF preprocessing circuit for performing AF preprocessing, 124 is an AE preprocessing circuit for performing AE preprocessing, and 125 is an AWB preprocessing circuit for performing AWB preprocessing. Process circuit 126 outputs the output of each pre-process circuit to MPU1
2 is an MPU interface circuit that receives the control data from the MPU 12 or receives control data of each unit of the integrated circuit 10 from the MPU 12.

Next, the operation will be described. The amount of light of a subject image (not shown) is adjusted by the imaging lens 1 and the aperture 3, and C
The color is separated through the above-mentioned minute color separation filter of CD5,
An image is formed on the photoelectric conversion surface of the CD 5, photoelectrically converted for each pixel, and sequentially output as an imaging signal in accordance with a driving pulse of the driver circuit 6. This imaging signal is first sent to the CDS
The clock component and reset noise are removed by the circuit 7, amplified by the AGC circuit 8 with a gain corresponding to the AGCC signal, and the black level is reduced by the clamp circuit 9 to the ADC circuit 101.
Is fixed to the reference voltage at the lower limit of the input range, and is converted into a digital signal by the AD converter 101 in the integrated circuit 10.

The digital signal is first decomposed into R, G, and B color components by a color separation / Y synthesis circuit 102, and at the same time, the luminance signal YC and the luminance signal and one horizontal line above (before). The luminance signal Y− of one horizontal line and the luminance signal Y + below (after) one horizontal line are synthesized. The R, G, and B signals are limited to a predetermined band by a low-pass filter 103, are further converted into a time-division signal in three phases, become a one-channel signal, and a predetermined signal set by the MPU 12 in the WB circuit 104. Is amplified with a gain of At this time, R
If only the gain of the signal and the B signal is changed, white balance adjustment is performed, and the overall gain can be controlled by simultaneously changing the gains of the R signal, the G signal and the B signal.

This output is subjected to gamma correction and compression of a high-luminance portion in a gamma-knee circuit 105, returned to R, G, and B signals again in a low-pass filter 105, and subjected to a predetermined band limitation. , R, G, and B color signals are added at a predetermined ratio by the matrix circuit 107 to form low-frequency luminance signals YL1 and YL2. Of these, YL1 is re-sampled at the same sampling rate as the high-band luminance signal to form a high-band luminance signal as described later, and YL2 is used only to form a color difference signal. Not sampled.

The YL2, R, and B are subtracted at a predetermined ratio by the color difference matrix circuit 108, and the color difference signal R-B is subtracted.
Y and BY are formed. The color difference signal is subjected to gain adjustment and a predetermined matrix operation and color correction by a color correction / fader circuit 109.
Is instructing a fade operation, the gain is gradually varied. This output is re-sampled by the low-pass filter 110 at a sample rate required for color modulation, for example, four times the frequency of the color sub-carrier SC, subjected to a predetermined band limitation, modulated by the color sub-carrier SC by the modulation circuit 111, and subjected to barr modulation. A burst signal is superimposed according to the strike flag signal BF. At this time, if the N / P signal specifies PAL, PA
The burst signal and the chrominance signal are inverted at a predetermined phase according to the ALT signal so as to conform to the L standard.

This output is digitally converted by a DA converter 112.
The signal is analog-converted, output as a chrominance signal C from a C output terminal 15, and supplied to a VTR (not shown), a television monitor, or the like.

The luminance signals Yc, Y−, Y + output from the color separation / Y synthesis circuit 102 are
After receiving the gamma correction in step S13, the high-pass filter 114 first forms YH1 as a high-frequency luminance signal and YH2 as an outline emphasis signal. Here, Y
H1 is, for example, equal to or higher than the band of the low-frequency luminance signal YL1 for forming the above-described luminance signal, and YH2 is equal to or higher than 3 to 4 MHz.

YH2 is a horizontal contour emphasizing signal E that has been compressed by the non-linear processing circuit 115 near the zero level.
H. The output of the gamma correction circuit 113 is added and subtracted by an adder 116, and also subjected to compression near zero level by a non-linear processing circuit 117.
And becomes the vertical contour emphasizing signal EV. Adder 119
Then, the above-mentioned YL1, YH1, EH, and EV are added,
The luminance signal Y is formed, subjected to a blanking process by the fader 120, and the gain is gradually changed during the fade operation as described above.

The output signal is digital-to-analog converted by a DA converter 121, added to a composite synchronizing signal CSYNC by an adder 16, and output from a Y output terminal 17.
Like the above-mentioned C, it is supplied to a VTR, a television monitor and the like (not shown).

Also, Yc, Y-, and Y + are processed by the AF pre-processing circuit 123 to form data necessary for AF, and Yc is processed by the AE pre-process 124 to form data required for AE. Is done. Further, the outputs RY and BY of the color difference matrix circuit 108 are A
The data is processed by the WB pre-processing circuit 125 to form data necessary for AWB, and these data are read out to the MPU circuit 12 through the MPU interface circuit 126.

FIG. 2 shows the AF pre-processing circuit 12 shown in FIG.
3, 201 is an adder, 202 and 206 are absolute value circuits for obtaining the absolute value of the input signal, 203 and 207 are gate circuits for gating the input signal according to the gate signal SG1, and 204 and 208 are the input circuits. A maximum value holding circuit for holding the maximum value of the signal; 205, a band-pass filter;
9 is an AF frame register for holding the position and size of the AF frame,
210 is a comparator, 211 is an H counter reset by the horizontal synchronizing signal HD to count clocks, 21
Reference numeral 2 denotes a V counter which is reset by the vertical synchronizing signal VD and counts HD, and 213 denotes an AF preprocessing circuit 1.
23, an internal bus that connects the AE preprocessing circuit 124, the AWB preprocessing circuit 125, and the MPU interface circuit 126.

First, the H counter 211 and the V counter 21
A signal corresponding to the current scanning position on the screen of the image pickup signal is generated by 2 and the frame data previously written in the AF frame register 209 is compared by the comparator 210 to generate a frame signal SG1.

On the other hand, the input luminance signal Yc is applied to a band required for AF by the band-pass filter 205, for example, 1 to 3 MHz.
z is taken out, an absolute value is obtained by an absolute value circuit 206, and the AF is performed by a gate circuit 207 in accordance with the above gate signal SG1.
Gate in the range according to the frame, and the maximum value hold circuit 208
Holds the maximum value EH of the high frequency component in the horizontal direction in the AF frame.

At this time, for example, during the vertical blanking period, the AF reset signal B is generated from the MPU interface circuit 126 to reset the maximum value hold circuit 208, and thereafter, the maximum value hold circuit 2
The maximum value EH held at 08 is output to the internal bus 213 when the AF read signal B is generated at the beginning of the next vertical blanking interval.

Further, the luminance signals Yc, Y− and Y + are added and subtracted in the adder 201 by Y−, Y + and Yc.
A high frequency component in the vertical direction is obtained, and this is
, And the gate circuit 203 outputs the gate signal S
The gate is gated according to G1, and the maximum value hold circuit 204 holds the maximum value EV of the high frequency component in the vertical direction in the AF frame.

At this time, similarly to the maximum value hold circuit 208, the reset operation and the read operation of the held data to the internal bus 213 are performed according to the AF reset signal A and the AF read signal A, respectively.

The maximum values of the high frequency components in the horizontal and vertical directions read in this way are used for AF control according to an algorithm shown in FIG.

FIGS. 3 and 4 are explanatory views of the AF frame of FIG. The outer frame of each figure shows the imaging screen, and the inner frame is A
The F frame is shown. The AF frame is, for example, x1, as shown in FIG.
When the coordinate values of y1, x2, and y2 are written in the AF frame register 209, a relatively large AF frame is obtained for the imaging screen, and when x3, y3, x4, and y4 are written as shown in FIG. A relatively small AF frame is obtained for the screen. This switching is performed by SW1 in FIG. 10 described later.

FIG. 5 shows the AE preprocessing circuit 124 in FIG.
FIG. 3 is a detailed view of a gate circuit 301;
Reference numerals 4 and 305 denote integrators, 303 denotes a switch circuit, 306 denotes a frame C register, 307 denotes a comparator, 308 denotes an H counter which is reset by the HD and counts a clock, 309
Is a V counter that is reset by VD and counts HD, and 310 is a decoder that forms a predetermined frame signal.

First, the H counter 308 and the V counter 30
9 generates a signal corresponding to the scanning position of the imaging signal on the screen, and compares this signal with the frame C data previously written in the frame C register by the MPU interface circuit 126 by the AE frame C register write pulse. Then, a frame signal SG2 is generated. At the same time, the outputs of the H counter 308 and the V counter 309 are input to the decoder 310, and form a predetermined frame signal SG3.

On the other hand, the input luminance signal Yc is first gated by the gate circuit 301 according to the gate signal SG2 of the movable frame, and is integrated by the integrator 302. At this time, for example, during the vertical blanking period, the MPU interface circuit 126 generates the AE reset signal C, and the integrator 302 is reset. When the AE read signal C is generated from the MPU interface circuit 126 at the beginning of the next vertical blanking interval, data integrated by the integrator 302 so far is output to the internal bus 213.

The luminance signal Yc is supplied to the switch circuit 303.
Are switched according to the gate signal SG3 of a predetermined frame, and are integrated by the integrator 304 or the integrator 305, respectively.

At this time, the integrator 3 responds to the AE reset signals A and B and the AE read signals A and B as described above.
Reset of 04 and 305 and output of data are performed.

FIGS. 6 and 7 are explanatory diagrams of the operation of FIG. The outer frame of each figure shows the imaging screen. In FIG. 6, the outside of the frame represented by the predetermined coordinate values (X1, Y1) and (X2, Y2) is A, and the inside is B, and the luminance signal at each is input to the integrators 304 and 305 in FIG. Have been. In FIG. 7, (x5, y5), (x6, y
When 7) is written, a frame C as shown is obtained, and the luminance signal inside the frame C is input to the integrator 302 in FIG.

The integrator 30 thus read out
The outputs 2, 304 and 305 are used for AE control in accordance with the algorithm shown in FIGS.

FIG. 8 shows the AWB pre-processing circuit 1 shown in FIG.
25 is a detailed view of the gate circuit, and 401 and 403 are gate circuits, 4
02 and 404 are integrators, 405 is an AWB frame register, 4
06 is a comparator, 407 is an H counter which is reset by HD and counts a clock, and 408 is a V counter which is reset by VD and counts HD.

First, the H counter 407 and the V counter 40
8, a signal corresponding to the scanning position of the image signal on the screen is generated.
The AWB frame data previously written to the AWB frame register 405 by the WB frame register write pulse is compared with the comparator 40.
6, the gate signal SG4 is generated.

On the other hand, the input color difference signals RY, BY
Are firstly gated by gate circuits 401 and 403 in response to the gate signal SG4 of the AWB frame, respectively.
404. At this time, for example, during the vertical blanking period, the MPU interface circuit 126
The RY reset signal and the BY reset signal are generated, the integrators 402 and 404 are reset, and the RY read signal and the BY read signal are generated at the beginning of the next vertical blanking interval. Data is transferred to internal bus 2
13 is output.

FIG. 9 is a diagram for explaining the operation of FIG. The outer frame in the figure shows the imaging screen. In the AWB frame register 405,
When the coordinates (x7, y7) and (x8, y8) are written, an AWB frame as shown is obtained, and each color difference signal inside the AWB frame is input to the integrators 402 and 404 in FIG.

The outputs of the integrators 402 and 404 are output to the AW according to the algorithm shown in FIGS.
Used for B control.

FIG. 10 shows the MPU circuit 12 and MPU in FIG.
FIG. 3 is a detailed diagram of an interface circuit 126. 501 to 509 are inside the MPU circuit 12, and 501 is a C
PU circuit, 502 is a memory for holding predetermined programs and data, 503 is the internal bus of the MPU circuit, 504, 5
05 is a DA converter, 506, 507 and 508 are input / output (IO) ports, and 509 is an interrupt generation unit. 51
0 and 511 are switches connected to the IO port 506 of the MPU circuit 12, 512 to 514 are inside the MPU interface circuit 126 in the integrated circuit 10,
Reference numerals 12 and 513 denote bus buffers that operate in accordance with control signals, and 514 interprets an input command and outputs the integrated circuit 1.
This is a command decoder that generates a signal for controlling each unit within 0.

According to the program in the memory 502, the CPU 501 switches SW1 connected to the IO port 506,
The status of SW2 is read, and IO ports 507 and 5
08, input and output data and commands to and from the MPU interface circuit 126,
05, an AF motor control voltage AFMC and an IG control voltage IGC are generated. Also, the interrupt generation unit 5
In step 09, when the vertical synchronizing signal VD is input, an interrupt signal is generated in the CPU 501, whereby the CPU performs a process at the time of the interrupt.

SW1 is a switch for setting the size of the AF frame, and the operator selects one of the two sizes of the AF frame shown in FIGS. 3 and 4 by switching this switch. I can do it. SW2 is a switch for performing a fade operation, and an operator can fade out or fade in an image by pressing this switch. The command decoder 514 receives a command from the IO port 507 according to the chip select signal CS generated from the IO port 508, interprets the command, activates the bus buffer 512 at the time of a write command, and simultaneously outputs the corresponding write pulse. When a read command is issued, the bus buffer 513 is activated and, at the same time, a corresponding read pulse is generated.

Further, a reset pulse, an NTSC / PAL switching pulse, a fade signal, and the like are generated in response to a reset command, a setting command of each section, and the like.

FIGS. 11 to 19 show the MPU circuit 12 in FIG.
4 is an operation flowchart of FIG.

FIG. 11 shows the operation when the power is turned on. 601
Start at 602, switch between NTSC and PAL,
The fixed value in the integrated circuit 10 such as the initial setting of the gain
It is set via the interface circuit 126. 60
3, the maximum value of the AF, AE, and AWB pre-processing circuits,
Alternatively, the integral value is reset, the initial value of each frame register is set at 604, the interruption by the vertical synchronization signal VD is permitted at 605, and the hold state is entered at 606. Thereafter, the operation is performed in response to an interrupt generated by VD.

FIG. 12 shows the operation when an interrupt by VD occurs.
At 608, the maximum value and the integrated value of each pre-processing circuit are read, at 609, the values of the AF, AE, and AWB frame registers are updated, and at 610, the values of the R and B gain controls are updated,
At 611, each maximum value and integral value are reset. The operations from 608 to 611 are completed within the vertical blanking period. At 612 to 614, AF, AE, and AWB controls, which will be described later, are performed, and at 615, the apparatus enters the hold state again and waits for a VD interrupt. The operations from 607 to 615 are completed within one vertical period (16 ms to 20 ms).

FIG. 13 shows the details of the AF control 612 in FIG. First, the processing starts at 616, and at 617, the read maximum value EV of the high frequency component in the vertical direction is compared with the maximum value EH of the high frequency component in the horizontal direction. When the EH is large, the AF operation is performed using the high frequency component in the horizontal direction. To do so, at 618 the current value of the high frequency component, Eno
Substitute EH for w. Also, when EV is larger in 617, Eno is used to use a high frequency component in the vertical direction.
Substitute EV for w.

At 620, the change amount Ed of the high frequency component is compared with the current high frequency component Enow and the previous high frequency component Eold.
Is subtracted, and Enow is substituted for Eold. At 621, Ed is compared with predetermined threshold values Eth and -Eth. First, if Ed is smaller than -Eth, AF
Since the high frequency component is reduced by the rotation of the motor, that is, the focus moves in the opposite direction, or the focus changes while the motor is stationary.
It is determined whether the AF motor control voltage is 0 at 2 or not. If it is 0, the AFM is turned at 624 to rotate the AF motor.
A predetermined value SAF is substituted for C. In addition, AFMC
Is not 0, the polarity of the AFMC is reversed to move the focus in the opposite direction.

At 621, Ed is greater than -Eth and E
If it is smaller than th, it is considered that focus is achieved, so AFMC is set to 0 at 625 and the AF motor is stopped. If Ed is larger than Eth in 621, the focus control direction is matched, so that AFMC is left as it is.

At 626, the AFM set as described above
The C voltage is output from the DA converter 504 in the MPU 12. At 627, the state of SW1 in FIG. 10 is determined.
If it is off, the frame size is set to a large value as shown in FIG. 3 at 628, and if it is on, the frame size is set to a small value as shown in FIG. Move on.

FIG. 14 shows an AE control step 613 in FIG.
FIG. Starting at 631, a weighted average value AB of the A region and the B region in FIG. That is, the integral value A of the A region obtained as the output of the integrator 304 of FIG. 5 is multiplied by the weight K1, the integral value B of the B region obtained as the output of the integrator 305 of FIG. 5 is multiplied by the weight K2, and each is added. To obtain a weighted average value AB.
Further, the difference between AB and the reference value ABr is obtained to obtain ABe.

At 633, the value obtained by multiplying the ABe by a predetermined coefficient K3 is subtracted from the current IG drive voltage IGC to obtain the next IG drive voltage IGC.

On the other hand, at 634, the integrated signal C in the C frame read from the integrator 302 of FIG. 5 is substituted into the data Cij of the current position of the C frame, and j is incremented by 1 at 635. At 636, j is compared with the predetermined horizontal division number n, and if it is smaller or equal, the process directly proceeds to 640;
At 7, j is set to 1 and i is increased by 1.

Further, i is compared with a predetermined number m of divisions in the vertical direction in 638, and if smaller or equal, i is set to 1 in 639 if larger or equal. Then, at 640, the minimum value CDmin of C in the D area in FIG.
At 41, the average value CEavg of C in the E area in FIG. 16 is obtained. At 642 in FIG. 15, the ratio between CDmin and CEavg is compared with a predetermined threshold value Cth, and if it is equal to or larger than Cth, the process proceeds to 644. For example, since the background brightness is large relative to the subject, that is, in a so-called backlight state, a predetermined exposure correction value VBC is subtracted from the IGC in 643.

Since the frame is once reset to C11 at 604 in FIG. 11, the frame C is sequentially switched in units of one field after the power is turned on.
vg will change.

In step 644, the IGC is output from the DA converter 505. To find the next position of the C frame at 645, x5
y5, x6, y6 are the horizontal size a, vertical size b of the frame,
The AE control is completed at 646 from the horizontal position j and vertical position i of the frame. FIG. 17 is an explanatory diagram of the AE control. The outer frame is an imaging screen, which is divided into n in the horizontal direction and m in the vertical direction, and the current position of the C frame in the frame is represented by i and j. You. At 646, the AE control ends, and the process proceeds to the next AWB control.

FIG. 18 is a detailed diagram of the AWB control step in FIG. 12, starting at 647 and starting with 648 the current AW control.
Data (R-Y) ij, (B-
Y) The read data RY and BY are substituted for ij, j is incremented by 1 at 649, and j is compared with the number n of screen divisions in the horizontal direction of the AWB frame at 650. If it is larger, j is set to 1 in 651 and i is increased by 1. In step 652, i is compared with the number m of screen divisions in the vertical direction. If smaller or equal, i is set to 1 in step 653 if smaller or equal.

The AWB frame is reset to the upper left corner of the screen when the power is turned on, similarly to the AE frame, and then shifted in units of fields.

At 654, the weighted total value SR-Y of (RY) ij is obtained, and at 655, the weighted total value SB-Y of (BY) ij is obtained. 656 If SR-Y is equal to a predetermined threshold-
If it is smaller than (RY) th, the predetermined value RG0 is subtracted from the control value RGAIN of the R gain at 657. 656, if SR-Y is greater than or equal to-(RY) th and (RY) t
When it is less than h, the predetermined value RG0 is added to RGAIN at 658 when it is larger than (RY) th. FIG.
9 at 659, if SB-Y is equal to the predetermined threshold value-(B-
Y) If it is smaller than th, the control value BG of the B gain at 660
The predetermined value BG0 is subtracted from AIN.

659 If SB-Y is-(BY) th
When the value is equal to or more than (BY) th and is equal to or less than (BY) th,
Y) When it is larger than th, a predetermined value BG0 is added to BGAIN at 661. In order to obtain the next position of the AWB frame at 662, x7, y7, x8, y8 are set to the horizontal size a,
From the vertical size b, the horizontal position j of the frame, and the vertical position i,
At 646, the AE control ends. Note that n in FIG.
m, a, and b may be the same as those in FIG. 14 or may be different. FIG. 20 is an explanatory diagram of the AWB control. The outer frame is an imaging screen, which is divided into n in the horizontal direction and m in the vertical direction.
The position of the WB frame is represented by i and j.

[0069]

As described above, according to the first and seventh aspects of the present invention, when adjusting the imaging apparatus using the outputs of the plurality of adjustment signal forming means, the plurality of adjustment signal formations are performed. Since the signal path between the means and the control means can be greatly reduced, the circuit configuration of the entire imaging device can be simplified, and the reliability of the imaging device can be improved. Further, the setting of a plurality of frames for extracting the signal for automatic adjustment can be easily controlled from the control means via the interface means, and the frame setting operation does not adversely affect the operation of extracting the adjustment signal. Moreover, the adjustment signal forming means can be realized with a simple configuration.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a detailed view of an AF pre-process in the embodiment of FIG.

FIG. 3 is an explanatory diagram when the AF frame in FIG. 2 is enlarged.

FIG. 4 is an explanatory diagram when the AF frame in FIG. 2 is reduced.

FIG. 5 is a detailed view of an AE pre-process in the embodiment of FIG. 1;

FIG. 6 is an explanatory diagram for describing a center-weighted AE photometric distribution in FIG. 5;

FIG. 7 is an explanatory diagram for describing a backlight measurement frame in FIG. 5;

FIG. 8 is a detailed view of an AWB pre-process in the embodiment of FIG. 1;

FIG. 9 is an explanatory diagram of the AWB frame of FIG. 8;

FIG. 10 is a detailed view of an MPU interface in the embodiment of FIG. 1;

11 is an operation flowchart when the power of the MPU in the embodiment of FIG. 10 is turned on.

12 is an operation explanatory diagram when an interrupt due to VD occurs in the operation flowchart of the MPU in the embodiment of FIG. 10;

13 is an operation explanatory diagram of AF control 612 in the operation flowchart of FIG.

14 is an operation explanatory diagram of the AE control 613 in the operation flowchart of FIG.

FIG. 15 is an explanatory diagram of the operation continued from the operation flowchart of FIG. 14;

FIG. 16 is an explanatory diagram of a backlight detection operation of 640 to 642 in the operation flowcharts of FIGS. 14 and 15;

17 is an explanatory diagram of a frame C for AE control in FIG. 12;

FIG. 18 is a flowchart showing the operation of AWB in the operation flowchart of FIG. 12;
Operation explanation diagram of control 614

FIG. 19 is an explanatory diagram of the operation continued from the operation flowchart of FIG. 18;

FIG. 20 is an explanatory diagram of the AWB frame of FIG. 19;

──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Shin Shimokoriyama 3-30-2 Shimomaruko, Ota-ku, Tokyo Inside Canon Inc. (56) References JP-A-2-1499073 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04N 5/232-5/243 H04N 9/04

Claims (12)

(57) [Claims] An imaging unit that converts a subject image into an electric signal; an imaging signal processing unit that processes an electric signal from the imaging unit to output an imaging signal including a synchronization signal; A plurality of adjustment signal forming means for forming a plurality of mutually different automatic adjustment signals based on signals in a plurality of frames of the signal, wherein each adjustment signal forming means counts a signal corresponding to a position of the frame. And a frame register for storing frame setting data, and a plurality of frames for setting the frame based on a comparison between the count value of the frame counter and the frame setting data stored in the frame register. Adjusting signal forming means; and an interface for transmitting the automatic adjustment signal from the adjusting signal forming means, receiving the frame setting data and supplying the frame setting data to the frame register. Source means, connected via the interface means, transmits the frame setting data to the frame register, receives the automatic adjustment signal from the adjustment signal forming means, and receives the automatic adjustment signal from the imaging means or the Control means for adjusting the adjustment unit of the imaging signal processing means, and based on the frame setting data from the control means, the adjustment signal forming means updates the operation of the frame setting with the synchronization signal of the imaging signal. An imaging apparatus which performs the synchronization signal during a blanking period of the synchronization signal. 2. The imaging apparatus according to claim 1, wherein the adjustment signal forming means and the interface means are integrated on the same integrated circuit. 3. The imaging apparatus according to claim 1, wherein said adjustment signal forming means forms a signal for automatic focus adjustment. 4. The apparatus according to claim 1, wherein said adjustment signal forming means forms a signal for automatic exposure adjustment. 5. The imaging apparatus according to claim 1, wherein said adjustment signal forming means forms a signal for automatic white balance adjustment. 6. The device according to claim 1, wherein the interface means inputs the automatic adjustment signal from the adjustment signal forming means via an internal bus and outputs the signal to the control means via a parallel bus. An imaging device characterized by being configured. 7. An imaging signal processing means for processing an electric signal from an imaging means for converting a subject image into an electric signal and outputting an imaging signal including a synchronization signal, and a plurality of frames of the imaging signal in the imaging signal processing means. A plurality of adjustment signal forming means for forming a plurality of mutually different automatic adjustment signals based on the signals in the frame, wherein each adjustment signal forming means is a frame counter for counting a signal corresponding to the position of the frame. And a frame register for storing frame setting data, and a plurality of adjustment signal forming means for setting the frame based on a comparison between the count value of the frame counter and the frame setting data stored in the frame register. Transmitting the automatic adjustment signal from the adjustment signal forming means to a control means for adjusting the adjustment section of the imaging means or the imaging signal processing means; Interface means for receiving frame setting data from the means and supplying the frame setting data to the frame register, and the adjustment signal forming means performs an update operation of the frame setting based on the frame setting data from the control means. An image signal processing apparatus, wherein the image signal processing is performed during a blanking period of the synchronization signal in synchronization with the synchronization signal of the image signal. 8. The apparatus according to claim 7, wherein said adjustment signal forming means and said interface means are integrated on the same integrated circuit. 9. The imaging signal processing apparatus according to claim 7, wherein said adjustment signal forming means forms a signal for automatic focus adjustment. 10. The imaging signal processing apparatus according to claim 7, wherein said adjustment signal forming means forms a signal for automatic exposure adjustment. 11. The apparatus according to claim 7, wherein said adjustment signal forming means forms a signal for automatic white balance adjustment. 12. The interface means is configured to input the automatic adjustment signal from the adjustment signal forming means via an internal bus, and to output the signal to the control means via a parallel bus. The imaging signal processing device according to claim 7, wherein: