JP3100221B2 - Traffic data collection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

(Table of Contents) Industrial Application Field Conventional Technology (FIG. 19) Problems to be Solved by the Invention Means for Solving the Problems (FIG. 1) Operation (FIG. 1) Example Embodiment of the Traffic Data Collection Apparatus Schematic description (FIGS. 2 to 6) Detailed description of the embodiment (FIGS. 7 to 18) Effects of the invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching system such as a telephone exchange, a data exchange or an ISDN exchange for displaying traffic data in real time. The present invention relates to a traffic data collection device for collecting traffic data such as the number of calls, the line busy status, and the operation status (processor usage rate, various trunk usage rates, line usage rate, etc.).

[0003]

2. Description of the Related Art FIG. 19 is a block diagram for explaining a conventional traffic data collection and display system. In FIG. 19, reference numeral 901 denotes a communication path as an electronic exchange main body. A subscriber terminal 904 is accommodated via a subscriber circuit 902 and a subscriber circuit 903, and is connected to a transit exchange via a trunk circuit 905.

[0004] The communication path 901 is connected to the control device 90.
6 is controlled by the memory 90 via a bus line 916.
7 and the CPU 908 are connected.
9 and a maintenance console input / output interface 910 are connected. The communication control device 909 is connected to the traffic data processing center 911 via a communication line, and the input / output interface 910 is connected to the maintenance console 912.

The maintenance console 912 is a CRT 9
13, a keyboard 914, a printer 915, and the like. In general, current exchanges collect and display traffic data by the following functions. (1) A function of displaying traffic data on a display device (in this case, a traffic data processing program is built in the exchange). (2) periodically transmitting traffic information to the traffic data processing center 911 by a program of the exchange itself,
This traffic data processing center 911 processes
The function of distributing tally results to each station.

[0006]

However, such a conventional device has the following problems. (1) The collection cycle is long. That is, since the data collection process places a large processing capacity load on the exchange itself, it is difficult to perform detailed collection, and therefore the collection cycle must be lengthened. (2) In the case of center processing, the response is slow. That is, when the data is transmitted to the traffic data processing center and distributed after data processing, the response is in the order of time. (3) There is no flexibility in data display. That is, in the case of collection using the software of the exchange itself, it is difficult to devise a collection display for each station.

[0007] Here, the problem of the prior art is that the switch itself collects traffic data. Nevertheless, it is natural that the exchange itself collects traffic data, and it is necessary to provide at least a minimum necessary data collection and display function. However, in order to perform detailed data collection processing and display in real time, the exchange requires an excessive processing capacity, and it becomes difficult to provide exchange equipment at a reasonable cost.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and is intended to realize a real-time and detailed data collection and display process by a subsystem connected to an exchange without requiring the exchange itself. It is an object to provide a data collection device.

[0009]

FIG. 1 is a block diagram showing the principle of the present invention. In FIG. 1, reference numeral 1 denotes an interface adapter.
And extracts the address information and the store information of the memory access in the exchange EX. 2 is an interface device, the interface device 2, Ru der extracts a traffic information from the address information from the interface adapter 1.

[0010] Also, the interface unit 2, a memory circuit 2-1 corresponding to the exchange memory space, the address in advance in each address corresponding data in the storage circuit 2-1 whether traffic data address storing identifying information, accesses the memory circuit 2-1 by the address information from the interface adapter 1, the address information is outputted whether traffic information, Torahi' in the storage circuit 2-1
According to the classification code obtained by converting the
Memo for collecting traffic data in chronological order
2-2 and the exchange memory address in the storage circuit 2-1.
Is the acquisition memory address for accumulated data obtained by converting
The same traffic data accumulation type data
And the cumulative memory 2-3 to collect has come to Yu
You.

The storage circuit 2-1 stores information for identifying whether the data is of a type collected in time series or of a type collected cumulatively. that has become. Also,
The memory circuit 2-1 stores the classification code of the traffic data if the type of traffic data to be chronologically collected, in the case of traffic data type that cumulatively collected and cumulatively collected that it has adapted to store the address of the memory.

Further, the interface device 2 has a processing section 2-4 for program control, and reads and processes the traffic information of the sequential memory 2-2 sequentially and time-sequentially when the information is stored. On the other hand, the traffic information of the accumulation type memory 2-3 is read out at regular intervals.
You.

[0013]

In the above traffic data collecting apparatus of the present invention, the address information and the store information of the memory access in the exchange EX are extracted by the interface adapter 1, and the traffic is calculated by the interface apparatus 2 from the address information from the interface adapter 1. Ru Nodea that information is extracted.

Furthermore, in the interface device 2, by sequential memory 2-2, the traffic data chronologically collected, a cumulative memory 2-3, to gather the same traffic data cumulatively. Then, the traffic information of the sequential memory 2-2, when the information is stored, sequentially, while processing time series read out, to read out the traffic information of the cumulative memory 2-3 at predetermined intervals.

In the interface device 2, information for identifying whether or not the address is a traffic data address is stored in advance in data corresponding to each address in the storage circuit 2-1. accesses the memory circuit 2-1, the address information is outputted whether traffic information, the sequential memory 2-2
In this case, the traffic data address is stored in the storage circuit 2-1.
Traffic is converted according to the classification code
Data is collected in chronological order and stored in the accumulation memory 2-3.
The exchange memory address is converted by the storage circuit 2-1.
The accumulated memory address for accumulated data
And the same traffic data accumulation type data is collected cumulatively
Is done. At this time, the storage circuit 2-1 stores information for identifying traffic data of a type collected in time series or traffic data of a type collected cumulatively. You.

[0016] The storage circuit 2-1, in the case of traffic data type that chronologically collected, stored classification codes of the traffic data, in the case of traffic data type that cumulatively collected, It stores the address of the memory cumulatively collected.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. (A) Schematic description of the present traffic data collection device First, FIG. 2 shows an example of a system configuration including the present traffic data collection device. As shown in FIG. 2, the traffic data collection device is installed in the exchange EX and installed in the exchange EX.
An interface adapter (IFADP) 1 for extracting address information and store information of memory access in the memory 1, a traffic data collection interface unit (TCIE: interface device) 2 for extracting traffic data from processing data, and processing / editing / display / processing of traffic data It is composed of a work station unit 3 for storing.

The interface unit 2 and the workstation 3 are connected to a LAN (ETHER-NET).
(LAN) 4. Further, the exchange E
In the X processor unit 7, the interface adapter 1 is connected to the bus 71, and the main controller (CC)
72, a main storage device (MM) 73, and input / output interfaces (IOC) 74-1 and 74-2 are connected.

The workstation section 3 includes workstations (WS) 31, 32, a display controller (DPC) 33, and a display (DSP).
34-1 to 34-3 are provided. The interface adapter 1 and the interface unit 2 are related to the gist of the present invention. The traffic data collecting apparatus according to the present invention includes the following three elements.

First, the first element of the present apparatus is to extract the processing data in the exchange by the interface adapter 1. That is, the interface adapter 1
It is connected to a bus of a processor in the exchange, and the processor extracts traffic information stored in a memory from address information. Next, the second element of the device is:
The purpose is to extract only traffic data in the interface unit 2 from the memory address / store data extracted in the interface adapter 1.

Further, the third element of the present apparatus is to process the traffic data in the work station unit 3 and display the traffic transition of the exchange in real time on the display. With the above configuration, the interface adapter 1 immediately notifies the interface unit 2 of the exchange processing status in conjunction with the processing speed of the exchange, and the interface unit 2 extracts traffic data at high speed mainly by hardware logic, and At 3, it is possible to display the traffic status in real time.

Therefore, the traffic data collecting apparatus enables a more detailed grasp of the driving situation than the traffic data collection of the conventional operation report, and makes it possible to preliminarily catch the abnormal congestion of the planning type and to quickly control the detour when the line is congested. Can be used, and it is possible to obtain detailed information on the line usage rate, busy rate, and overflow rate, so that it is also possible to obtain useful information for switching equipment planning and to compare it with traffic processing by conventional switching equipment. As a result, innovative traffic data services can be provided.

Further, in the present traffic data collecting apparatus, how to extract and edit the traffic data from the memory address / store data extracted by the interface adapter 1 has the following three problems. First, the first problem is that the memory address / store data extracted by the interface adapter 1 naturally has a large amount of data unrelated to traffic, and it is necessary to extract only traffic data from the data. It is scattered in the memory in the exchange and how to identify the traffic data.

The second problem is to classify traffic data.
How to speed up editing. That is, when the extracted traffic data is transmitted to the workstation 3 as it is (memory address / store data), the workstation 3 needs to associate the data with the data from the memory address. However, in this case, a very high-speed address table reference process is required, and it is difficult to realize the process using a relatively inexpensive workstation.

A third problem is that a transaction is hunted every time a call is generated, such as the number of times of use of a transaction. It is meaningless to perform data processing for each hunt, and it puts pressure on data processing capacity. The following is a detailed description of each of the above-mentioned issues and how to deal with them.

FIG. 3 shows the first problem. That is, in FIG. 3, the interface unit 2 is provided with an address collation circuit 2-5 and a collection memory 2-6, and a memory address from the interface adapter 1 is input to the address collation circuit 2-5, and the corresponding It is first conceivable to determine whether or not the data is traffic data. In such a case, if the traffic data is scattered in several tens of places in the switch memory, the address matching circuit 2-
5 is tens of places, which requires an enormous number of gates, which is impractical.

The solution is shown in FIG. That is, in the traffic data collecting apparatus, an index memory (storage circuit) 2-1 is prepared in the interface unit 2 as an address collating function. The index memory 2-1 has the same space as the memory space of the exchange, and has one-to-one correspondence with the exchange memory address. However, the exchange memory is 1
While there are 32 bits of data in the address, the index memory 2-1 is basically 1 bit.

In the index memory 2-1, data "1" is written in advance at the address of traffic data, and data "0" is written in advance at addresses other than the traffic data. Then, the index memory 2-1 is accessed based on the memory address, and whether or not the data is traffic data is determined based on “0” and “1” of the data indexed from the index memory 2-1.

As a result, the traffic data collection device of the present invention does not require an enormous amount of circuits, and can easily extract traffic data by installing the index memory 2-1. See Figure 5 for measures against the second issue.
It will be described according to the following. As described above, the index memory 2-1 corresponds to the memory address of the exchange, and the meaning of the traffic data can be determined by the memory address.

Therefore, as the data to be stored in the index memory 2-1, not only the identification of the traffic data of "0" and "1", but also the classification code of the traffic data are stored together. That is, when a certain memory address is traffic data, the identification as traffic data and its classification code are output from the index memory 2-1. Therefore, the classification code and its data are transmitted to the workstation section 3 instead of transmitting the memory address and data, and the corresponding processing in the workstation section 3 becomes unnecessary.

Since classification is automatically performed by index memory access, high-speed classification processing is realized as a system. In FIG. 5, reference numeral 2-2 denotes a sequential memory (sequential memory) for storing a data classification code and traffic data, and reference numeral 2-3 denotes a memory (cumulative memory) for receiving the conversion address information and storing the traffic data. ). The sequential memory 2-2 and the accumulative memory 2-3 will be described later.

As for the third problem, the nature of the traffic data will be described first. Traffic data consists of sequential data that needs to be collected and processed every time data is generated,
It can be divided into two types of cumulative data to be sampled at a certain fixed time interval and processed by comparison with the previous sample value. As sequential data, data with high novelty that is not related to the previously collected data, such as the usage rate of the switch processor and the line usage rate, is applicable.
It is count data and overwritten type data, such as the total number of outgoing calls and the number of incoming calls.

With respect to the third problem of collecting accumulated data, the traffic data collecting apparatus of FIG.
The problem is solved by the method shown in FIG. First, in the present traffic data collection device, the accumulation type memory 2-3 (hereinafter, referred to as accumulation type memory 2-3)
The memory 2-3 is sometimes referred to as a cumulative data collection memory 2-3). The capacity of the accumulation type memory 2-3 is basically equal to the total number of words of the accumulation type data.

The accumulative data collection memory 2-3
And the corresponding data address in the exchange memory, and when the cumulative data in the exchange memory is updated,
The data at the corresponding address in the accumulative data collection memory 2-3 of the apparatus is also updated at the same time. The correspondence between the exchange memory address and the accumulation type data collection memory address is as follows.
The aforementioned index memory 2-1 is used. As described above, the index memory 2-1 has a one-to-one correspondence with the address of the exchange memory, and the accumulation memory for accumulation type data 2-3 is stored in the index memory 2-1 corresponding to the address of the accumulation type data.
Is stored.

As described above, when the cumulative data is updated in the exchange, the data at the corresponding address in the cumulative data collection memory 2-3 in the apparatus can be updated at the same time. Summarizing the above, one of the features of the traffic data collection device lies in the function of the index memory 2-1. The index memory 2-1 has the following functions. (1) A function of extracting traffic data from exchange memory address information. (2) A function of converting a traffic data address to a data classification code (only the sequential memory 2-2). (3) The function of converting the exchange memory address into the accumulation type data collection memory address in the accumulation type data.

(B) Detailed Description of the Embodiment FIG. 7 is a block diagram showing an embodiment of the present invention. As shown in FIG.
Basically, an interface adapter (IFAD) that is mounted in the exchange EX and extracts processing data in the exchange EX
P) 1, a traffic data collection interface unit (TCI) for extracting traffic data from processing data
E: interface device 2 and a workstation 3 connected to the interface unit 2 via the LAN 4 for processing, editing, displaying and storing traffic data, as described above.

First, the interface adapter 1 is connected to a bus in the exchange EX as shown in FIGS.
In order to monitor the write operation from the switch processor to the switch memory and extract the memory address information and the store information, the extracted address data is transmitted to the interface unit 2.
As shown in FIGS. 7 and 8, the interface adapter 1 includes a bus signal receiving circuit 11, a data extracting circuit 12, and a data transmitting circuit 13. The interface adapter 1 creates an ACT system identification signal of the exchange and transmits the signal to the interface adapter 1. The interface adapter 1 is also duplicated because the exchange EX is duplicated.

Here, the bus signal receiving circuit 11 receives a signal from the bus, and includes a plurality of receiver circuits 111.
Is provided. The data extraction circuit 12 extracts memory address information and store information from a received signal. For this purpose, a bus reception control circuit (BRCTL) 12
1, address buffer / data buffer (ABUF / D
BUF) 122 and 123 are provided.

First, the bus reception control circuit 121 controls reception of a bus signal, and controls the control device (processor) CC of the exchange.
Is a circuit for identifying that the command issued from the switch has a write command to the memory MM of the exchange. The address buffers / data buffers 122 and 123 receive multiplexed information (for example, 32 bits) of address / data written from the control device CC to the memory MM, and store address information (for example, 24 bits) and data information (for example, 32 bits). And a circuit for latching each.

Further, the data transmission circuit 13 transmits the extracted address data to the interface unit 2. Therefore, the address / data information transmission control circuit (SDCTL) 131 and the ACT-related CC determination circuit (AJDG) 132, an address / data information transmission selection switching circuit (ADSEL) 133, an address / data information transmission selection circuit (SEL) 134, a parity signal creation circuit (PTYGN) 135, and a transmission driver 136.

Here, when the address / data information transmission control circuit 131 receives the multiplexed address / data information transmitted from the interface adapter 1 by the traffic data collection interface unit 2, for example, a 150 ns pulse This is a circuit that creates a sample timing signal (TSYN) having a width and transmits it.

The ACT CC determining circuit 132 removes the access to the memory MM from the off-line CC, and
In order to extract only the access information from the C (exchange controller), it is determined whether the system is an ACT / CC (active system) and the result is used as an ACT signal (TACT) as a traffic data collection interface unit. This is a circuit for transmitting to the second side.

The address / data information transmission selection switching circuit 133 converts the address / data information already latched in the ADR / DTRs 122 and 123 into multiplexed address / data information (TAD00 to TAD32), and a traffic data collection interface. This is a circuit for switching the selector output system for sending to the unit 2 side. address/
The data information transmission / selection circuit 134 outputs the ADR / DTR 12
2 and 123, the information of the address information (24 bits) and the data information (32 bits) already latched are selected by the switching signal created by the ADSEL 133, and the multiplexed address / data information (TAD00) is selected.
To TAD32) is a circuit to be sent to the traffic data collection interface unit 2 side.

The parity signal generation circuit 135 is a circuit for generating a parity bit signal (TAD32) to be added to the address / data information transmitted to the traffic data collection interface unit 2 side. In the case of the address information in the above address / data information, TA
D24 to TAD31 = “0” are transmitted to the traffic data collection interface unit 2 side. Also,
TAD32 is a parity bit.

With this configuration, the interface adapter 1 monitors the write operation from the exchange processor 73 to the exchange memory 73 and extracts the memory address information and the store information as shown in FIGS. , And the extracted address data can be transmitted to the interface unit 2. The address strobe (A
DS), write / read switching (W / R), memory / input / output interface switching (M / IO), address (A
FIG. 10 shows a time chart for each signal of D), acknowledgment (ACK), and synchronization (SYN).

By the way, the interface unit 2
As shown in FIG. 7, a data collection unit (DCOL) 21, a data processing unit (DPR) 22, a communication processing unit (CPR) 2
3, a system memory unit (SM) 24, a test data transmission circuit 25, a transceiver 26 and the like. Here, the data collection unit 21 collects data from the interface adapter 1, and includes a data reception circuit (RCV) 211, a data selection circuit (SLCT) 21
2, a sequential data collection circuit (SQCOL) 213, an accumulation type data collection circuit (AQCOL) 214, a control circuit 215, and the like.

The data receiving circuit 211 receives the memory (MM) store address data from the interface adapter 1, synchronizes with the internal clock, selects an ACT system of the exchange, and receives information from the ACT interface adapter 1. And the interface adapter 1 is duplexed (see # 0, # 1).

The data selection circuit 212 includes a memory (MM)
The traffic data is selected based on the address information, and the traffic data is identified as a sequential type or a cumulative type. In the case of the sequential type, the classification information is output, and in the case of the cumulative type, the converted address is output. The data selection is performed by the index memory. Sequential data collection circuit 2
Reference numeral 13 stores sequential acquisition data in a sequential memory. The sequential data acquisition circuit 213 reads the contents of the memory sequentially according to an instruction from the data processing unit 22.

The accumulative data collection circuit 214 has a memory for storing accumulative data, and writes traffic data to the memory based on the conversion address from the data selection circuit 222. The contents of the memory are read from a specified address in accordance with an instruction from the data processing unit 22. Further, the above data receiving circuit 211
The data receiving circuit 211 asynchronously receives the memory address and data information from the interface adapter 1 and synchronizes the information with the internal clock TSYN of the interface unit 2. As shown in FIG. 11, an address buffer / data buffer (ADBUF / DTBUF) 211
-1, 211-2, address registers / data registers (AR / DR) 211-3, 211-4, and the like.

Address buffer / data buffer 211
-1, 211-2 receive the multiplexed address / data information (33 bits) transmitted from the interface adapter 1 on the exchange side as data information to be written from the control device CC to the memory MM, and receive the address information (25 bits). ) And data information (33 bits). It should be noted that one of the 33 bits of the address / data information is a parity bit.

Address register / data register 211
Reference numerals -311 and 211-4 are for sending address / data information read from the register file to the data selection circuit 212. Thus, the data receiving circuit 211 can asynchronously receive the memory address / data information from the interface adapter 1 and synchronize it with the internal clock TSYN of the interface unit 2.

The data selection circuit 212 has the above-described index memory (16 MW) 212-1. The index memory 212-1 is obtained from the exchange memory address information from the data receiving circuit.
, Identification information of traffic data or not, collection type identification information (sequential type / cumulative type), classification information in case of sequential type, conversion address information to accumulation type collection memory in case of cumulative type (see FIG. 13). Therefore, as shown in FIG. 12, the index memory (index memory) (X.MEM) 212-1, the index
Address counter (XAC) 212-2, index write register (XWR) 212-3, index read register (XRR) 212-4, index data register (XDR) 212-5, data register (DR1) 212-6. And so on.

Here, the index memory (index memory) (X.MEM) 212-1 is a data memory of 16 MW × 16 bits (2-bit parity). It selects traffic data of the type and outputs a data classification code and a conversion address. The index / address counter 212-2 receives the IN / IN from the data processing unit 22.
An address counter capable of reading / writing data from / to the index memory 212-1 by an OUT instruction.

Index write register 212-3
Is a register that enables data writing to the index memory 212-1 in response to an OUT instruction from the data processing unit 22. The index read register 212-4 stores the index memory 21 in response to an IN instruction from the data processing unit 22.
This register enables data to be read from 2-1.

Index data register 212-5
Is a register for transferring data information (conversion address / data classification code) of the index memory 212-1 to the accumulation type / sequential type data collection circuits 213 and 214. The data register 212-6 is a buffer for transferring memory (MM) store data to the data collection circuits 213 and 214.

With this configuration, the data selection circuit 212 accesses the index memory 212-1 based on the exchange memory address information from the data reception circuit 211, and identifies whether the data is traffic data or not and the collection type identification information. (Sequential type / cumulative type), the classification information in the case of the sequential type, and the conversion address information (see FIG. 13) to the accumulation type collection memory in the case of the cumulative type.
12-5.

The sequential data collection circuit 213 generally has a 32 KW collection memory, a collection memory write counter or a read memory counter, and sequentially stores sequential traffic data. 14, as shown in FIG. 14, a sequential data acquisition memory (SQ. MEM) 213-1, a sequential write counter (SWC) 213-2, a sequential up / down counter (SUDC) 213-3, and a sequential address. Counter (SAC) 213-4, sequential write register (SW
R) 213-5, Sequential read register (SRR) 21
3-6, a diagnostic read buffer (DRB) 213-7 is provided.

The sequential data collection memory 213-1 is
This is a 32 KW × 47 bit (1-bit parity) sequential data collection memory for storing traffic data and data classification information of the index memory 212-1. The sequential write counter 213-2 is an address counter for data collection, and writes traffic data and data classification information of the index memory 212-1 to the collection memory 213-1 according to the counter.

Successive Up / Down Counter 213-3
Is an up / down counter for data collection / readout,
It counts up (+1) when collecting data and counts down (-1) when reading data. The value of the sequential up / down counter 213-3 indicates the number of unread data words. Sequential address counter 21
Reference numeral 3-4 denotes an address counter capable of reading / writing data from / to the collection memory 213-1 in response to an IN / OUT instruction from the data processing unit 22.

The sequential write register 213-5 stores the collection memory 21 in response to an OUT instruction from the data processing unit 22.
This register enables writing of data 3-1 (test data). The sequential read register 213-6 receives the IN command from the data processing unit 22 and
-1 data (traffic data and data classification information,
Test data) is a register that enables reading.

The diagnostic read buffer 213-7 is a buffer that can read the current access address in response to an IN instruction from the data processing unit 22 during the sequential acquisition memory diagnosis. With such a configuration, the sequential traffic data can be sequentially stored in the collection memory 213-1 by the sequential data collection circuit 213, but the sequential up / down counter 213-3.
However, when data is collected, the count is incremented by one, and when data is read, the count is decremented by one, so that the number of unread data words can always be known. Note that the sequential data collection circuit 213 can also write and read test data using the sequential write register 213-5.

The accumulation type data collection circuit 214 has a capacity of 16 KW.
Has a collection memory 214-1 and a read counter,
Writing of cumulative traffic data is performed by the data selection circuit 2.
12, the traffic data is written using the conversion address output from the index memory 212-1 as the collection memory address. Therefore, as shown in FIG. 15, the accumulation memory for accumulation type data (AQ.MEM) is used. 21
4-1, Cumulative address counter (AAC) 214-
2, an accumulation type write register (AWR) 214-3, an accumulation type read register (ARR) 214-4, and the like.

Here, the accumulative data collection memory 214
-1 is a memory of 16 KW × 33 bits (1 bit parity), which stores traffic data using the exchange address information of the index memory 212-1 as an address. The accumulation type address counter 214-2 is an address counter capable of reading / writing data from / to the collection memory 214-1 in response to an IN / OUT instruction from the data processing unit 22.

The accumulative write register 214-3 receives the OUT command from the data processing unit 22 and stores the data in the collection memory 21.
This register enables data (test data) writing of 4-1. The accumulative read register 214-4 receives the IN command from the data processing unit 22 and
This register enables reading of data (traffic data, test data) of 4-1.

With such a configuration, the accumulation type data collection circuit 214 uses the conversion address output from the index memory 212-1 of the data selection circuit 212 as a collection memory address, and stores the accumulation type traffic data in the collection memory 214-1. Is written. It should be noted that this accumulation type data collection circuit 213 also has the accumulation type write register 2.
14-3 enables writing and reading of test data.

The control circuit 215 controls various parts of the data collection unit 21. The control circuit 215 includes a flip-flop SY for displaying address data existence.
C0F to SYC3F (described later) are also provided. The above is the description of each unit of the data collection unit 21,
Next, the data processing unit 22 includes a 16-bit processor unit including, for example, an 80286 microprocessor (MPU) 22-1 and a program memory 22-2 and a local memory 22-3. The data is read, edited, and stored in the system memory unit 24. The data processing unit 22
In this example, a 16-bit MPU 221 is mainly configured, and each circuit of the data collection unit 21 is connected to a local bus with a buffer.

FIG. 16 shows a detailed configuration of the data processing section 22. That is, as shown in FIG. 16, the data processing unit 22 includes a microprocessor 22-1, a program memory 22-2, a local memory 22-3, a clock generator (CLK GEN.) 22-4, and an interrupt controller ( PIC) 22-5, Reset circuit (RESET)
22-6, Local Bus 22-7, Buffered Local Bus 22-
8, wait control circuit (WAIT CTL) 22-9, address latch (ADDR.LATCH) 22-10, data buffer (DA
TA BUFFER) 22-11, local bus control circuit (BU
SC) 22-12, interval timer (PIT) 22
-13, interrupt display register (IDR) 22-14, address decoder (ADDRESS DEC.) 22-15, DRAM control circuit (DRAMC) 22-16, ramp register (LA
MP REG.) 22-17, switch register (SW.RE)
G) It is configured with 22-18 and the like.

Here, as the microprocessor 22-1, for example, a 16-bit microprocessor (8028
6) is adopted and used at an operation clock of 8 MHZ. The program memory 22-2 is a memory for storing programs, and is constituted by a 64 KB EPROM. The local memory 22-3 has 896 KB (with 1-bit parity)
For example, a DRAM is used as the data memory.

The clock generator 22-4 has a 16M
Receives an external clock of HZ, and 16MHZC with 50% duty
LK is supplied to the MPU 22-1, and the frequency is divided by 2 (8M
HZ) is distributed to peripheral circuits. In addition, RDY control for the MPU 22-1 is also performed. The interrupt controller 22-5 is a program-controllable interrupt controller, which can control an eight-level priority interrupt.

The reset circuit 22-6 detects power-on and a reset key operation, and supplies a reset signal to the MPU 22-1 and the like. Local bus 22-7
Is an MPU of 20 bits of address and 16 bits of data.
The local bus with buffer 22-8 is a bus obtained by expanding the local bus 22-7 via a buffer, and connects the memory and the I / O port with the local bus with buffer 22-8.

The weight control circuit 22-9 is provided with the MPU 22
-1 is inserted into the memory and IO via the local bus 22-7, and a wait cycle is inserted to adjust the access time. Address latch 22-10
Latches the address information of the local bus 22-7,
It is sent to the buffered local bus 22-8.

The data buffer 22-11 connects the local bus 22-7 and the local bus with buffer 22-8 by a bidirectional buffer element. The local bus control circuit 22-12 decodes the status signal of the MPU 22-1 and generates various signals for controlling a local bus with a buffer. The interval timers 22-13 have three program-controllable timers, one of which is used as a failure detection timer (TF).

The interrupt display register 22-14 receives and latches an interrupt request signal and generates an interrupt signal. The interrupt factor can be read by an IN instruction. The address decoder 22-15 decodes address information and generates an access destination signal for the local bus 22-7. A DRAM control circuit (local memory control circuit) 22-16 performs access and refresh control of the data memory by the DRAM. A lamp register 22-17 is a 16-bit register for latching lamp display information. −
Reference numeral 18 denotes a register that allows the switch state to be read out via the local bus 22-7.

With such a configuration, traffic data can be read from the data collection unit 21, edited, and stored in the system memory unit 24. The above is the description of each unit of the data collection unit 21 and the data processing unit 22. Next, the test data transmission circuit 25 shown in FIG.
A test address and data transmission circuit for simulating the output of the interface adapter 1, and a communication processing unit 23
Is a 16-bit processor configured to be composed of, for example, a program memory 232 and a local memory 233 with an 80286 MPU 231 at the center, and further transmits traffic data stored in the system memory 24 to an Ethernet control circuit (LANCE) 234 and a transceiver 2.
6 to the workstation 3. In addition, RS-
A general-purpose transmission / reception circuit (URT circuit) 235 for connecting the personal computer 9 by 232-C is provided.

That is, the communication processing unit 23 is connected to the workstation 3 by the ETHRNET-LAN.
4 is mainly performed, and the configuration is almost the same as that of the data processing unit 22. The system memory unit 24 is a memory circuit used for transmitting and receiving collected data between the data processing unit 22 and the communication processing unit 23 and communicating order / response from the workstation unit 3.

With this configuration, according to the present traffic data collection device, the address information and the store information of the memory access in the exchange are extracted by the interface adapter 1, and the interface unit 2
The traffic information is extracted from the address / data information from the interface adapter 1. Further, in the interface unit 2, the sequential data collection circuit 213 collects traffic data in time series,
The accumulation type data collection circuit 214 collectively collects the same traffic data.

Then, when the information is stored, the traffic information in the sequential collection memory 213-1 is sequentially read out in a time series and processed, while the accumulation type collection memory 214-
One traffic information is read out at regular intervals. In the interface unit 2, information for identifying whether or not an address is a traffic data address is stored in advance in the index memory 212-1 in data corresponding to each address, and the index memory 212-1 is stored in accordance with address information from the interface adapter 1. 1 and outputs whether or not the address information is traffic information.

At this time, the index memory 212-1 stores information for identifying whether the data is of a type collected in time series or of a type collected cumulatively. In the case of traffic data of a type to be collected in time series, the classification code of the traffic data is stored, and in the case of traffic data of a type to be collected cumulatively, an address of a memory to be collected is stored. Is done.

The operation of the interface unit 2 will be described in detail with reference to FIGS. 17 and 18. First, when the data reception circuit 211 of the data collection unit 21 receives address data from the interface adapter 1,
In synchronization with the internal clock, a flip-flop (SYCOF) indicating the presence of address data is fired. The address data is processed in a pipeline with the data receiving circuit 211, the data selecting circuit 212, and the data collecting circuits 213 and 214, and at the same time, the flip-flop SY
Shift to C1F and SYC2F, and display the presence at each stage.

The data processing unit 22 is, for example, 32 m
The contents of the collection memories 213-1 and 214-1 are read and processed for each s.
Between the write cycles to the collection memory 213-1,
214-1 needs to be read, and therefore, the flip-flop SYSC1F indicating the existence of data is monitored. If this flip-flop SYSC1F is OFF, the timing of the next flip-flop SYC2F becomes empty. Collection memory 2 using
13-1 and 214-1 are read out.

The flip-flops SYSCOF, S
YSC2F is turned on at the rising edge of the 4M clock, and flip-flops SYSC1F and SYSC3F are turned on at the falling edge of the 4M clock. Here, the internal clock of the data collection unit 21 is 4 MHZ and can be collected every 250 ns, but the memory address / data information coming from the exchange is:
The interval is 500 ns on average, and an empty cycle is generated once every two cycles, so that reading of the data processing unit 21 and writing (collection) of traffic data can be performed in a time-division manner.

FIG. 18 shows a time chart at each point in this case. An outline of a processing example of the data processing unit 22 is as follows.
As described above, with respect to traffic data collection, each time data is generated, there are sequential data to be collected and accumulated data in which data is updated one after another, and a collection memory is individually prepared for each. Therefore, the software of the data processing unit 22 reads and processes the contents of the collection memory 213-1 each time data is collected in principle for sequential data. Further, the accumulated data is meaningless even if it is processed each time data is collected, and is read out at a certain interval to calculate a difference from a previous value to obtain a change in traffic over a certain period of time.

That is, the cumulative data is used to grasp the traffic volume at a certain time, and the sequential data is processed as event-like traffic data. As described above, the embodiments of the present invention have been described. According to the traffic data collecting apparatus, it is possible to collect the traffic information related to the exchange in a very real time and reduce the load on the exchange. It is possible to display detailed traffic information, and as a result, the operation management of exchanges becomes more fulfilling and a very useful system can be provided as a network management supporting the progress of the advanced information society. is there.

[0084]

As described above in detail, according to the traffic data collecting device of the present invention, Ri collecting traffic data related to the exchange is Do allow very real time, and reduce the burden on the switch This makes it possible to display detailed traffic data, and as a result, the operation management of exchanges becomes more fulfilling, providing an extremely useful system for network management that supports the development of an advanced information society. There is.

[Brief description of the drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a block diagram showing the overall configuration of one embodiment of the present invention.

FIG. 3 is a diagram illustrating a data collection method.

FIG. 4 is a diagram illustrating a configuration of an address matching circuit.

FIG. 5 is a diagram illustrating a data structure of an index memory.

FIG. 6 is a diagram illustrating a method of collecting accumulated data and accumulated data.

FIG. 7 is a block diagram showing a main configuration of an embodiment of the present invention.

FIG. 8 is a block diagram showing an interface adapter.

FIG. 9 is a diagram illustrating an outline of a processor bus in the exchange.

FIG. 10 is a time chart showing an example of a memory write sequence on a processor bus in the exchange.

FIG. 11 is a block diagram illustrating a data receiving circuit.

FIG. 12 is a block diagram illustrating a data selection circuit.

FIG. 13 is a diagram illustrating the contents of data stored in an index memory.

FIG. 14 is a block diagram illustrating a sequential data collection circuit.

FIG. 15 is a block diagram illustrating an accumulative data collection circuit.

FIG. 16 is a block diagram illustrating details of a data processing unit and a connection relationship between the data processing unit and another circuit.

FIG. 17 is a diagram illustrating the operation of the data collection unit.

FIG. 18 is a diagram illustrating operation timing in a data collection unit.

FIG. 19 is a block diagram showing a conventional example.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 Interface adapter (IFADP) 2 Interface unit (interface device) 2-1 Storage circuit 2-2 Sequential memory 2-3 Cumulative memory 2-4 Program control processing unit 2-5 Address verification circuit 2-6 Collection memory 3 Workstation unit 4 LAN 7 Processor unit 8 Personal computer 11 Bus signal receiving circuit 12 Data extraction circuit 13 Data transmission circuit 21 Data collection unit (DCOL) 22 Data processing unit (DPR) 22-1 Microprocessor 22-2 Program memory 22-3 Local memory 22-4 Clock generator (CLK GEN.) 22-5 Interrupt controller (PIC) 22-6 Reset circuit (RESET) 22-7 Local bus (Local Bus) 22-8 Buffered local bus (Buffered Local)
Bus) 22-9 Wait control circuit (WAIT CTL) 22-10 Address latch (ADDR.LATCH) 22-11 Data buffer (DATA BUFFER) 22-12 Local bus control circuit (BUSC) 22-13 Interval timer (PIT) 22 -14 Interrupt display register (IDR) 22-15 Address decoder (ADDRESS DEC.) 22-16 DRAM control circuit (DRAMC) 22-17 Lamp register (LAMP REG.) 22-18 Switch register (SW.REG) 23 Communication Processing Unit (CPR) 24 System Memory Unit (SM) 25 Test Data Transmission Circuit 26 Transceiver 31, 32 Workstation 33 Display Controller 34-1 to 34-3 Display 71 Bus 72 Main Controller 73 Main Storage Device 74-1, 74 -2 I / O interface 111 Over bus circuit 121 bus reception control circuit 122 and 123 the address buffer / data buffer 131 address / data information transmission control circuit (SDCT
L) 132 ACT CC determination circuit (AJDG) 133 Address / data information transmission selection switching circuit (A
DSEL) 134 Address / data information transmission / selection circuit (SEL) 135 Parity signal creation circuit (PTYGN) 136 Transmission driver 211 Data reception circuit (RCV) 211-1, 211-2 Address buffer / data buffer (ADBUF / DTBUF) 211 -3, 211-4 Address register / data register (AR / DR) 212 Data selection circuit (SLCT) 212-1 Index memory (index memory) 212-2 Index / address counter (XA
C) 212-3 Index Write Register (XWR) 212-4 Index Read Register (XRR) 212-5 Index Data Register (XDR) 212-6 Data Register (DR1) 213 Sequential Data Collection Circuit (SQCOL) 213 -1 Sequential data acquisition memory (SQ.ME
M) 213-2 Sequential write counter (SWC) 213-3 Sequential up / down counter (SUD)
C) 213-4 Sequential address counter (SAC) 213-5 Sequential write register (SWR) 213-6 Sequential read register (SRR) 213-7 Diagnostic read buffer (DRB) 214 Cumulative data collection circuit (AQCOL) 214-1) Accumulation type data collection memory (AQ.ME)
M) 214-2 Cumulative address counter (AAC) 214-3 Cumulative write register (AWR) 214-4 Cumulative read register (ARR) 215 Control circuit 231 Microprocessor 232 Program memory 233 Local memory 234 Ethernet control circuit (LANCE) 235 General-purpose transmission / reception circuit 901 Communication path as electronic exchange main body 902 Concentrator circuit 903 Subscriber circuit 904 Subscriber terminal 905 Trunk circuit 906 Controller 907 Memory 908 CPU 909 Communication controller 910 Maintenance console input / output interface 911 Traffic data processing center 912 Maintenance console 913 CRT 914 Keyboard 915 Printer 916 Bus line EX exchange

──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Toshio Awaji 1015 Uedanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Ryuichi Kato 1015 Kamikodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited ( 72) Inventor Akira Ueda 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Shingo Tanaka 1-6-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Inventor Kitano Hidetaka 1-6, Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Inventor Shohei Nakajima 1-1-6, Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (56) References JP 57-52256 (JP, A) JP-A-63-276954 (JP, A) JP-A-3-101354 (JP, A) JP-A-56-122564 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H04M 3/36

Claims (5)

(57) [Claims] And 1. A switching equipment installed at the interface adapter to draw the address information and store information of the switching equipment of the memory access, and an interface equipment for extracting traffic information from the interface adapter or these address information provided , The interface device has a storage circuit corresponding to a switch memory space, and the storage circuit
The address is previously stored in the data corresponding to each address on the path.
Information that identifies whether the data address is
According to the address information from the interface adapter,
Access to the storage device, and the address information is traffic information.
Whether or not the traffic data address is converted by the storage circuit.
The classification code obtained Te, and sequential memory for collecting traffic data in time series, and switch the memory address is converted by the storage circuit resulting et al
The collected memory address for cumulative data, and having a cumulative main <br/> mode Li cumulatively collect same traffic data cumulative data, traffic data collection device. 2. A memory installed in an exchange and installed in the exchange.
An interface that derives access address information and store information
From the face adapter and the address information from the interface adapter, the
Interface device for extracting traffic information
The interface device has a storage circuit corresponding to the exchange memory space, and the storage circuit
The address is previously stored in the data corresponding to each address on the path.
Information that identifies whether the data address is
According to the address information from the interface adapter,
Access to the storage device, and the address information is traffic information.
Outputs whether, characterized by storing information identifying whether in the storage circuits, when a series manner type of traffic data or collected for a type of traffic data is to be accumulatively collect the to, door La Hick data collection device. 3. A memory installed in an exchange and installed in the exchange.
An interface that derives access address information and store information
From the face adapter and the address information from the interface adapter, the
Interface device for extracting traffic information
The interface device has a storage circuit corresponding to the exchange memory space, and the storage circuit
The address is previously stored in the data corresponding to each address on the path.
Information that identifies whether the data address is
According to the address information from the interface adapter,
Access to the storage device, and the address information is traffic information.
Outputs whether, in the storage circuits, when in the case of the type of traffic data to be sequentially collected, and to store the classification code of the traffic data, collected by La Hick data collection device. 4. A memory installed in an exchange and installed in the exchange.
An interface that derives access address information and store information
From the face adapter and the address information from the interface adapter, the
Interface device for extracting traffic information
The interface device has a storage circuit corresponding to the exchange memory space, and the storage circuit
The address is previously stored in the data corresponding to each address on the path.
Information that identifies whether the data address is
According to the address information from the interface adapter,
Access to the storage device, and the address information is traffic information.
Whether to output, to the storage circuits, in the case of traffic data type that cumulatively collected, and to store the address of the memory cumulatively collected, preparative La Hick data collection device. 5. A memory installed in an exchange and installed in the exchange.
An interface that derives access address information and store information
From the face adapter and the address information from the interface adapter, the
Interface device for extracting traffic information
In addition, the interface device transmits traffic data in time series.
And the same type of traffic data
And a cumulative memory that product collects, includes a processing unit of the program control to the interface instrumentation 置内, the traffic information該逐following type memory, when the information is stored, sequentially in time series reading while processing, and wherein the reading the traffic information of the cumulative memory at predetermined time intervals, preparative La Hick data collection device.